94 CPU (CM8051) Incompatible Instruction ERRATA AND DATASHEET CLARIFICATION V1.0. Leader of Microcontroller Technology A Fabless Semiconductor Company

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1 94 CPU (CM8051) Incompatible Instruction ERRATA AND DATASHEET CLARIFICATION V1.0 Leader of Microcontroller Technology A Fabless Semiconductor Company Document information Info Keywords Abstract Content MC94F1202A / MC94F1102AS / MC94F1102AM A94B114FR / A94B114FD / A94B114AE This errata describe incompatible instructions between the 8051 and the CM8051. ABOV Semiconductor V of 9 -

2 Revision history Version Date Revision list V Initial preliminary version V1.0 Published by AE team 2017 ABOV Semiconductor Co. Ltd. all rights reserved. Additional information of this document may be served by ABOV Semiconductor offices in Korea or distributors. ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable. However, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this document. Contact information For more information, please visit : fae@abov.co.kr ABOV Semiconductor V of 9 -

3 1. Product identification Above's device name rule is: The device described in this document is a device corresponding to 94 of (2) CPU type. Device type 94 represents the CM8051-S version, which is compatible with The sections in this document describe some incompatible instruction. The corresponding devices are Cm8051-S_R0 devices and will be changed in future CM8051-S_R1 devices. The devices corresponding to CM8051-S_R0 are MC1202A and A94B114 series devices. 1.1 DA A instruction Intel MCS Instruction set summary DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-bcd format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If Accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. If the carry flag is now set or if the four high-order bits now exceed nine (1010XXXX-1111XXXX), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn t clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator and PSW conditions. Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction. DA A C AC F0 RS1 RS0 OV F1 P ABOV Semiconductor V of 9 -

4 1.1.2 incompatible operation example MCS & CM8051-S_R0 Operation example (Compatible Operation) Instruction ADD A,R0 before ADD A,R0 After DA A Execute Register Value Value Value Value Value Value Value ACC 0x13 0x89 0x80 0x08 0x08 0xF3 0x87 R0 0x14 0x97 0x90 0x09 0x07 0x28 0x33 ACC 0x27 0x20 0x10 0x11 0x0F 0x1B 0xBA AC CY ACC 0x27 0x86 0x70 0x17 0x15 0x81 0x20 AC CY CM8051-S_R0 Operation example (Incompatible Operation) Instruction ADD A,R0 before ADD A,R0 After DA A Execute Register Value Value Value Value Value Value ACC 0x35 0x35 0x35 0x35 0x35 0x35 R0 0x65 0x66 0x67 0x68 0x69 0x6A ACC 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F AC CY ACC 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 AC CY When the value of 0x9A to 0x9F is converted to DA A, it is out of BCD range. MCS Operation Example Instruction ADD A,R0 before ADD A,R0 After DA A Execute Register Value Value Value Value Value Value ACC 0x35 0x35 0x35 0x35 0x35 0x35 R0 0x65 0x66 0x67 0x68 0x69 0x6A ACC 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F AC CY ACC 0x00 0x01 0x02 0x03 0x04 0x05 AC CY ABOV Semiconductor V of 9 -

5 1.2 PUSH instruction Intel MCS Instruction set summary The PUSH instruction increments the stack pointer and stores the value of the specified byte operand at the internal RAM address indirectly referenced by the stack pointer. No flags are affected by this instruction. PUSH Direct Function Push onto stack Description The Stack Pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location address by the Stack Pointer. Otherwise no flags are affected. Example On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the value 0123H. The instruction sequence, PUSH DPL PUSH DPH will leave the Stack Pointer set to 0BH and store 23H and 01H in internal RAM locations 0AH and 0BH, respectively. Bytes 2 Cycles 2 Encoding Direct Operation PUSH (SP) (SP) + 1 ((SP)) (Direct) ABOV Semiconductor V of 9 -

6 1.2.2 incompatible operation example The general operand of a PUSH instruction is compatible. However, when the operand is SP, the operation of 8051 core and CM8051-S_R0 are different. The above behavior will be modified to work the same way as the 8051 core in the subsequent product CM8051-S_R1. The examples below show incompatible instructions in the A94B114 series and MC94F1202A series. MCS & CM8051-S_R0 Operation example (Compatible Operation) Previous state : SP = 0x07, Stack0 = 0, Stack1 = 0, ACC = 0x55, (SP) = Stack0 PUSH ACC; SP SP + 1, ((SP)) (Direct) Next state : SP = 0x08, Stack0 = 0, Stack1 = 0x55, ACC = 0x55, (SP) = Stack1 CM8051-S_R0 Operation example (Incompatible Operation) Previous state : SP = 0x07, Stack0 = 0, Stack1 = 0, (SP) = Stack0 PUSH SP; SP SP + 1, ((SP)) (SP) Next state : SP = 0x08, Stack0 = 0, Stack1 = 0x08, (SP) = Stack1 MCS Operation Example Previous state : SP = 0x07, Stack0 = 0, Stack1 = 0, (SP) = Stack0 PUSH SP; SP SP + 1, ((SP)) (SP) Next state : SP = 0x08, Stack0 = 0, Stack1 = 0x07, (SP) = Stack1 Note: In MCS-51 and other companies, the operation is as follows. PUSH SP; SP NEXT SP PREVIOUS + 1, ((SP NEXT )) (SP PREVIOUS ) CM8051-S_R0 operates as follows. PUSH SP; SP NEXT SP PREVIOUS + 1, ((SP NEXT )) (SP NEXT ) ABOV Semiconductor V of 9 -

7 1.3 POP instruction Intel MCS Instruction set summary The POP instruction reads a byte from the address indirectly referenced by the SP register. The value read is stored at the specified address and the stack pointer is decremented. No flags are affected by this instruction. POP Direct Function Pop from stack Description The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected. Example The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively. The instruction sequence, POP DPH POP DPL will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this point the instruction, POP SP will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was decremented to 2FH before being loaded with the value popped (20H). Bytes 2 Cycles 2 Encoding Direct Operation POP (direct) ((SP)) (SP) (SP) - 1 ABOV Semiconductor V of 9 -

8 1.3.2 incompatible operation example The general operand of a POP instruction is compatible. However, if the operand is an SP, it should be treated as an exception, but it is treated the same in CM8051. MCS & CM8051-S_R0 Operation example (Compatible Operation) Previous state : SP = 0x08, Stack0 = 0, Stack1 = 0x55, ACC = 0, (SP) = Stack1 POP ACC; (ACC) ((SP)), (SP) (SP) - 1 Next state : SP = 0x07, Stack0 = 0, Stack1 = 0x55, ACC = 0x55, (SP) = Stack0 CM8051-S_R0 Operation example (Incompatible Operation) Previous state : SP = 0x08, Stack0 = 0, Stack1 = 0x30, (SP) = Stack1 POP SP; (SP) ((SP)), (SP) (SP) - 1 Next state : SP = 0x2F, Stack0 = 0, Stack1 = 0x30, (SP) = Stack0 MCS Operation Example Previous state : SP = 0x08, Stack0 = 0, Stack1 = 0x30, (SP) = Stack1 POP SP; (SP) ((SP)) Next state : SP = 0x30, Stack0 = 0, Stack1 = 0x30, (SP) = Stack0 Note: If the operand of the POP is SP, this is a special case and SP does not decrease after the value has moved. In CM8051-S_R0, it is reduced to the same as other operands. ABOV Semiconductor V of 9 -

9 Table of contents Revision history Product identification DA A instruction Intel MCS Instruction set summary incompatible operation example PUSH instruction Intel MCS Instruction set summary incompatible operation example POP instruction Intel MCS Instruction set summary incompatible operation example... 8 ABOV Semiconductor V of 9 -

Microcontroller. Instruction set of 8051

Microcontroller. Instruction set of 8051 UNIT 2: Addressing Modes and Operations: Introduction, Addressing modes, External data Moves, Code Memory, Read Only Data Moves / Indexed Addressing mode, PUSH and POP Opcodes, Data exchanges, Example