Folding. Hardware Mapped vs. Time multiplexed. Folding by N (N=folding factor) Node A. Unfolding by J A 1 A J-1. Time multiplexed/microcoded

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1 Folding is verse of Unfolding Node A A Folding by N (N=folding fator) Folding A Unfolding by J A A J- Hardware Mapped vs. Time multiplexed l Hardware Mapped vs. Time multiplexed/mirooded FI : y x(n) h h h h y(n) sample/ N fixed multipliers li N- adders N k n hk xn k MUX N /sample generalized multiplier adders oeffiient memory + ontrol Hardware mapped 5 mult with fixed oeffeients adders delays Lateny= Biquad Filter Mirooded mult adder Lateny=5 Coeff Memory egisters Controller M MUX MUX

2 Folding Time-shared Arhiteture l+ l+ b(n) (n) b(n) (n) l+ l+ a(n) y(n) a(n) y(n) y ( n ) n a ( n ) b ( n ) ( ) l+ Folding is a tehnique to redue the silion area by time-multiplexing many operations into single funtional units. Folding introdues registers/storage Computation time inreased, e.g. one output sample every The right figure shows a timesfolded arhiteture where additions are folded, or time-multiplexed, to a single adder a() a() Folding, example y( n) a( n) b( n) ( n) Cyle b() l+ l+ l+ y(-) a()+b() l+ Cyle l+ () Cyle Cyle b() l+ l+ l+ a()+b()+() l+ () l+ a(n) Control Unit b(n) l+ l+ (n) l+ l+ l+ ontrol signal(s) y(n) Finite State Mahine -/ S S -/ Folding edue hardware by N-folding T omputation inreased by N Latey xtremes Fully parallel Time multiplexed = unit per algorithmi operation Folding extra registers, i.e. extra storage ontrol unit lateny

3 N=folding fator Nr. of operations folded to a single unit Nl+u HW-unit U Folding Transformation H u U (e) V l = iteration HW-unit Nl+v V P u F (UV) H v P v Level of Pipeline elays in folded graph u and v are folding order, i.e. sheduled time u, v N Folding Transformation Nl+u H u P u F (UV) Nl+v H u is pipelined by P u stages and its output is available at Nl + u + P u. dge UV has w(e) delays the l-th iteration of U is used by (l+w(e)) th iteration of node V, whih is exeuted at N(l + w(e)) + v. v So, the result should be stored for : F (UV) = [N(l + w(e)) + v] [Nl + P u + u] F (UV) = Nw(e) - P u + v u (i independent d of fl l ) H v P v Folding Set A folding set is an ordered set of operations to be exeuted on the same funtional unit. ah set ontain N entries, N=folding fator. S N=, A, A A belongs to folding set S with folding order Null operation S Three onepts Alloation - determine arhitetural t resoures Assignment - binding operations to hardware Sheduling - determine exeution order

4 Alloation and Assignment (S -) (S -) a b (S -) (S -) (S -) (S -) d (S -) (S -) Alloate adder, S, and one multiplier, S Assignment beomes trivial Sheduling (S ) (S ) a b (S ) (S ) ) (S ) (S ) d (S ) (S ) ) Folding of N= folding order,,, How do I get the folding order? Is it orret? Folding of Biquad filter Unit, Folding order (S ) (S ) Node nr. a b 5 6 (S ) (S ) (S ) ) (S ) ) d 7 8 (S ) (S ) So why didn t the filter look like this? (S ) (S ) a b 5 6 (S ) (S ) ) (S ) (S ) d 7 8 (S ) (S ) )

5 So why didn t the filter look like this? (S ) (S ) a b 5 6 (S ) (S ) ) (S ) (S ) d 7 8 T adder (S ) (S ) ) Additions Multipliation,,, S 5,8,6,7 T mult P P adder S mult Folding of Biquad filter, N= reeive send F (UV) = Nw(e) - P u + v u (S ) (S F () = - ) F( F (5) = F (6) = F (7) = 7 a F (8) = 5 b 5 6 (S F () = ) (S ) (S ) (S ) F () = ) ) F (5) = d F (6) = F (7) = - F (8) = - (S ) (S ) F ( U VV ) Not Valid folding Folding of Biquad filter, N= Folding of Biquad filter (S ) (S ) a b 5 6 (S ) (S ) (S ) ) (S ) ) d 7 8 Feedforward etiming utset Split and (S ) (S ) Pipelining move delay (S ) (S ) a b 5 6 (S ) (S ) (S ) ) (S ) ) 7 8 d (S ) (S )

6 Folding of Biquad filter, N= (S ) (S ) a b 5 6 (S ) (S ) ) (S ) (S ) T mult d 7 8 T adder P P adder (S ) ) (S ) ) Additions Multipliation,,, S 5,8,6,7 S mult Folding of Biquad filter, N= reeive send F (UV) = Nw(e) - P u + v u (S (S ) ) F () = () + = F (5) = () + = a b F (6) = () + = 5 6 F (7) = () + = (S ) (S ) F (8) = () + = 5 (S ) (S ) F () = () + = 7 8 d F () = () + = F (5) = () + = (S ) (S ) F (6) = () + = F (7) = () + = Valid folding F (8) = () + = F ( U V ) Folding of Biquad filter, N= reeive send P adder F (UV) = Nw(e) - P u + v u (S (S ) ) F () = () + = F (5) = () + = a b F (6) = () + = 5 6 F (7) = () + = (S ) (S ) F (8) = () + = 5 (S ) (S ) F () = () + = 7 8 d F () = () + = F (5) = () + = (S ) (S ) F (6) = () + = F (7) = () + = Valid folding F (8) = () + = F ( U V ) Folding of Biquad filter, N= 5 delays Additions S,,, S Multipliation 5,8,6,7 F (8) = () + = 5 path from add to mult with 5 Node 8 has folding order swith lose at

7 Folding of Biquad filter Folding of Biquad filter Additions S,,, S Multipliation 5,8,6,7 F () = () + = path from add to add with Node has folding order swith lose at Node is also onneted to the input Additions S,,, S Multipliation 5,8,6,7 xeution of node (input from node and ) : F () = () + = path from add to add with Node has folding order swith lose at F ( ) = () + = path from add to add with Folding of Biquad filter, N= reeive send F (UV) = Nw(e) - P u + v u (S (S ) ) F () = () + = F (5) = () + = a b F (6) = () + = 5 6 F (7) = () + = 7 (S ) (S ) F (8) = () + = 5 (S ) (S ) + = F () = () 7 8 d F () = () + = F (5) = () + = (S ) (S ) F (6) = () + = F (7) = () + = - Not valid folding F (8) = () + = F ( U V ) Hardware Mapped vs. Mirooded d Hardware mapped 5 mult with fixed oeffeients adders delays Lateny= Biquad Filter Mirooded mult adder Lateny=5 Coeff Memory egisters Controller M MUX MUX

8 r(u) U U (e) etiming for Folding V r(v) If F (UV) is the folded delays of the edge UV for the retimed graph then F (UV) Nw r (e) P U + v u r (e) N(w(e) + r(v) r(u) ) - P U + v u V r (e) = (e) + r(v) - r(u) reeive send N(r(U) r(v)) Nw(e) - P U + v u r(u) r(v) F (UV) /N r(u) ( ) r(v) F F( (UV) /N (floor sine retiming values are integers) egister/storage Minimization Folding inserts register. Lifetime analysis is used for register minimization tehniques in a SP hardware. A variable is live from the time it is produed until the time it is onsumed. After that it is dead. Linear lifetime hart : epresents the lifetime of the variables in a linear fashion. Convention: a variable is not live during the lok yle when it is produed but live during the lok yle when it is onsumed. One iteratiom 6 N=6 egister Minimization i i Max. number of live variables Min. number of registers egister Minimization i i Max. number of live variables Min. number of registers Use previous iter. to avoid drawing lifetime hart over several iterations 6 6 live variables But if several iterations live variables in iteration live variables But if several iterations live variables in iteration

9 a d g x Matrix Transpose b e h f i i h g f e d b a Matrix Transposer a b One iteration = 9 lok yles d e f g h i i f h e b g d a Lifetime Table - x Matrix Transpose i h g f e d b a Matrix i f h e b g d a Transposer Sample T in T zlout T diff T out Life a b 6 before d - e f 5 7 g 6 h 7 5 i 8 8 Lifetime Table - x Matrix Transpose i h g f e d b a Matrix Transposer Sample T in T zlout T diff T out Life a b 6 d - e f 5 7 g 6 - h i 8 8 T diff = T zlout T input, T zlout = zero lateny i f h e b g d a x Matrix Transpose Sample T in T zlout T diff T out Life a b 6 d - 5 e f 5 7 g 6 - h i 8 8 if T diff < not ausal add lateny = T negative diffmax for all nodes

10 x Matrix Transpose Lifetime hart x Matrix Transpose Sample T in T zlout T diff T out Life a b d e 8 8 f g h i if T diff < not ausal add lateny = T negative diffmax for all nodes Sampl T in T zlout T diff T out Life e a b d e 8 8 f g h i One iteration = 9 lok yles yle a b d e f g h i #live Contribution from next iteration Lifetime hart x Matrix Transpose Sampl T in T zlout T diff T out Life e a b d e 8 8 f g h i One iteration = 9 lok yles yle a b d e f g h i #live += += += += The total yle One iteration = 9 lok yles a b d e f g h i Lifetime hart #live yle a b d e f g h i #live Contribution from next 5 6 iterationti 7 8

11 Lifetime hart x Matrix Transpose Sampl T in T zlout T diff T out Life e a b d x x x x e 8 8 f g h i max #live = registers Cirular lifetime hart Useful to represent the periodi nature of the SP programs. Forward Bakward egister Alloation Tehnique Steps for Forward-Bakward egister alloation :. etermine the minimum number of registers using lifetime analysis.. put eah variable at the time step orresponding to the beginning of its lifetime. If multiple variables are input in a given yle, these are alloated to multiple registers with preferene given to the variable with the longest lifetime.. ah variable is alloated in a forward manner until it is dead or it reahes the last register. forward alloation, if the register i holds the variable in the urrent yle, then register i + holds the same variable in the next yle. If (i + )-th register is not free then use the first available forward register.. Being periodi the alloation repeats in eah iteration. So hash out the register j for the yle l + N if it holds a variable during yle l. 5. For variables that reah the last register and are still alive, they are alloated in a bakward manner on a first ome first serve basis. 6. epeat steps and 5 until the alloation is omplete. Forward Bakward egister Alloation Tehnique Forward Forward Bakward Forward Forward Forward

12 Folded Arhiteture for Matrix Transposer Controller for Folded Arhiteture egisters Controller for Swithes First--First-, FIFO Moving data onsumes power FIFO, ontinued Conneting outputs to remove lateny and remove data shifts Lateny sine data has to move through all registers Controller to hoose output Controller

13 FIFO, ontinued Conneting inputs. What do we have? a AM FIFO with pointers AM OUT Address (pointer) alulation IN Address alulation No moving of data but omplexity in address alulation Lifetime hart x Matrix Transpose egister Minimization i i of Biquad filter registers Possible to use memory with positions One entry for eah node: T input = u + P u, u=folding order, P u =pipeline time unit data is produed TT output t = u+p u +max V { F (U V)}, max V { F (U V)} = (longest folded path)

14 egister Minimization i i of Biquad filter F (UV) = Nw(e) - P + v u send u F () = F (5) = reeive F F( (6) = node,5,6,7,8 F (7) = F (8) = 5 F () = F () = F (5) = F (6) = F (7) = F (8) = One entry for eah node: T input = u + P u = + = T output = u + P u + max V { F (U V)} = + + maxv{,,,,5} = 9 egister Minimization of Biquad filter Node T in T out 9 F () = -- F (5) = += F (6) = ++= F (7) = +=5 F (8) = 5 ++=5 F () = 5 += F F( () = += F (5) = 6 += F (6) = += F (7) = 7 +=5 F (8) = ++=6 8 += ++= One entry for eah node: T input = u + P u T output = u + P u + max V { F (U V)} Lifetime hart of Biquad filter......and egister Alloation Node T in T out 9 st iter. -- nd iter rd iter. st iter. nd iter. rd iter.

15 Folded d arhiteture t is drawn with minimum # of registers. Previous arhiteture M MUX MUX Biquad Filter Implementation using registers, setion Implementation using memories Used for a speeh srambler with 8 x setion biquads. Whih approah to use? epends on: number of positions number of moves omplexity of address alulation et... As the number of positions inrease a memory solution beomes more favorable. eide on ase by ase basis.