Large Exploration for HW/SW partitioning of Multirate and Aperiodic Real-Time Systems

Transcription

1 Large Exploration for HW/SW partitioning of Multirate and Aperiodi Real-Time Systems Abdenour Azzedine, Jean-hilippe Diguet, Jean-Lu illippe Université de Bretagne SUD; LESTER lab.; Lorient, Frane ABSTRACT This paper addresses the domain of fine and oarse grain HW / SW odesign for Real-Time System On-Chip. We propose a new method for the real-time sheduling and the HW / SW partitioning of multi-rate or aperiodi tasks. The large design spae exploration is based on parallelism/delay trade-off urves. Keywords HW / SW Codesign, system design exploration, RT sheduling. INTRODUCTION The use of on-hip heterogenous real-time systems is ontinuously growing in various areas like mobile ommuniations, automotive, avionis, robots,... These trends are sustained by the numerous advantages the real-time SOC (system-on-hip)) approah offers : the use of an RTOS failitates the management of aperiodi tasks and real time onstraints; dediated HW modules an be implemented on the same hip to speed up ritial appliations tasks; the hip apaity enables to implement omplex appliations with a large set of arhitetural alternatives; the on-hip ommuniation bandwidth makes HW / SW odesign really attrative; the proessor ore an be tailored reagrding the appliation in terms of o-proessors and dediated memory hierarhy. However, the assoiated design spae is onjointly exploding and onsequently requires methods and tools to guide the designer towards an (the) interesting solution. First, the inrease of appliation omplexity means an inrease of the speifiation granularity. Thus, for eah task of an appliation, a lot of parallelism / ost / time trade-offs should be onsidered in order to perform an effiient system-level design. Seondly, the system must be able to optimally handle a set of appliations whih are haraterized by both periodi (e.g. audio deoding) and aperiodi tasks whih an have hard (e.g. game pad management) or soft (mail loading) realtime onstraints. Then, depending on ritiality and periodiity aspets, a design tool must address the trade-off between the respet of response times and the area and power requirements. In this paper we propose a framework to ombine the HW / SW partitioning and sheduling problems of real-time systems onto monoproessor arhitetures. The speifiation is a multi-rate periodi and aperiodi task graph. Eah task is desribed with a hierarhial ontrol data flow graph. This graph is estimated for various time onstraints in order to produe area/time trade-off urves. The method is based on an aurate stati sheduling and a large branh and bound exploration. The rest of the paper is organized as follows. Setion 2 plaes our work within the state of the art. Setion 3 details our odesign ontext. In Setion 4 we present the different steps of our exploration, partitioning and sheduling method. Setions 5 and 6 ontain respetively results from a real-life appliation and a onlusion about this work and future developments. 2. STATE OF THE ART Design of omplex system on hip requires a speifiation based on a oarse grain granularity. Suh a speifiation an be data-flow [2, 22], ontrol-data flow (CDFG) [9, 3] or task-graph oriented [23, 8]. Furthermore, embedded systems an be both aperiodi or periodi and even multirate. Moreover, to perform an effiient design spae exploration, a large set of parallelism/delay trade-offs must be assoiated with eah node of the speifiation. For these reasons, we have hosen to speify the appliation with a hierarhial task graph whih is well-adapted to the task-level real-time sheduling. Eah task is then desribed with funtions (i.e. CDFG) in order to effiiently explore several arhiteture solutions. The step detailed in this paper is loated after a funtional (CDFG) deomposition of the appliation followed by a task merging step [8]. Three kinds of arhitetures are usually targeted, the first one is based on monoproessor arhitetures with hardware aelerators whih an [2, 2] or not run simultaneously [20]. The seond one addresses multiproessor arhitetures [23, 5, 22] and the last one inludes ASI [7, 2] designs. In this paper, we fous on monoproessor arhitetures where the proessor an be parameterized with fine-grain oproessors and ommuniate with oarse-grain aelerators. We first make this hoie beause their low-ost and low-power harateristis make them very interesting in pratie for embedded systems [6]. Seondly, on-hip HW / SW monoproessor systems an meet hard real-time onstraints. Atually, integrated HW aelerators an benefit from the fat that intra and inter task parallelism an be exploited thanks to atual and future

2 hip apaities [24]. Moreover, on-hip ommuniations redue the penalty due to ommuniation overhead. Note that in this ontext, we onsider that an HW aelerator an be a DS used as a slave module (dediated to a single task). Our goal is to ombine a large design spae exploration with a real-time sheduling suitable to real-life ases in terms of multirate tasks and low or high priority aperiodi tasks. In the area of multiproessor arhitetures single-rate [7] but also multi-rate preemptive [23, 3, 9] sheduling tehniques have been proposed. However, in that ase dependent tasks (or proesses) have the same period and are lustered in independent subgraphs. Moreover, multiproessor researh don t really target a full design spae exploration, basially hardware implementations are just onsidered as proessors limited to a single task exeution. In [8] Dave and al. propose the assoiation array and task lustering to solve the multirate problem in odesign, but these onepts are really interesting only in the ontext of multiproessors arhitetures. The method is extended in [3] to aperiodi tasks for whih time slots are reserved within the hyperperiod. This tehnique is valuable if aperiodi tasks have strit response times but an lead to very ostly design if the tasks are rarely launhed or if their exeution is not ritial. In [2] aperiodi tasks are not inluded but the multirate issue is onsidered in the ontext of a monoproessor HW / SW arhiteture. The method is based on the fixed priority sheduling theory [4, 6], however the design spae exploration is limited to a fine grain solution (proessor + oproessor) or separately to a oarse grain arhiteture whih inlude a proessor and parametrized ASIC.The dependene question is solved while using the Inverse Deadline tehnique, but like in [3] the question of dependent tasks with distint periods is not onsidered (for instane the issue of tasks release time). We have also hosen a stati sheduling as it is the only solution to guaranty real time onstraints but we ve added a low ost sheduling tehnique for low priority aperiodi tasks. We onsidere an ayli task graph mapped on HW / SW mono-proessor arhiteture, we adress the dependenies between task while using task pipelining and priority assignments. Regarding previous work, the originality is a ombination of the three following points (i) multirate real-time stati sheduling (ii) ritiality-based sheduling of aperiodi tasks (iii) large design spae exploration ombining fine and oarse grain HW / SW odesign. 3. FRAMEWORK 3. System speifiation Basially, the system is speified with an ayli task graph (TG). In our approah, a TG is one of the hierarhy level of the speifiation (f. fig.). The system level desribes system inputs and outputs. At the task level (TG), a node represents a periodi or aperiodi task and an edge a data (ommuniation hannel) or a ontrol (event) dependene between tasks. Note that task deadline onstraints an be derived, for periodi tasks, from system input/output onstraints as desribed in []. The resoure onstraints due to data sharing is indiated with a speial node ( ). Aordingly to real-time theory, the funtion level is a luster of sequential or mutually exlusive CDFG whih ompose a task. Finally, at the instrution level a fontion is desribed as a hierarhial CDFG. A HCDFG top-down deomposition is performed as follows: a CDFG is built eah time a onditionnal instrution is found, when no more onditionnal instrution is present a DFG is reated (basi blok). Thus, in a CDFG a node represents a onditionnal instrution, a data transfer, (H)CDFG or a DFG. In a DFG, whih means the lowest hierarhy level, only remain elementary nodes representing data-transfer or data-proessing. System level Tasks level Funtions level Instrutions level ost en e en f2 e D32 inputs T f22 2 T HCDFG de f32 C322 T4 C3 Environment system T5 T4 D323 D324 f32 f33 Tn T6 Tn T6 sm outputs Figure : multi-level speifiation HW HW 2 Cop Cop 2 SW Figure 2: Task dynami estimations sm s s Exeution time. 3.2 Target Arhitetural Model In the ontext of the Design Trotter tool, eah node (i.e. task) an be linked to a CDFG speifiation. Suh a speifiation is an entry point for our dynami estimation tool [5] whih an provide a set of implementations from a sequential software to a highly parallel hardware module. The estimation result is a parallelism/delay trade-off urve as showed in fig.2. There are three kinds of implementations. The first one is totally software and its ost is given by the program and data memory sizes. The seond one, alled oproessor solution, is a software implementation but the proessor ore is upgraded with oproessors. This is what is usually alled a fine-grain odesign where speifi instrutions an be speed up by the use of dediated funtionnal units (multiplier, butterfly, MAC...). There is no ommuniation delay sine the additionnal funtional units are aeeded through the proessing unit registers. Its ost is based in the program and data memory sizes and the oproessors area. Note, that as oproessors an be shared between tasks, the ost omputation must take into aount previous task implementations. Finally a hardware implementation represents a dediated hardware module with its own ontrol. Contrary to previous solutions, a HW module an run simultaneously with the proessor but also implies ommuniation delays. For instane, the different HW solutions orrespond to different loop unfolding solutions [5], so to various trade-offs between parallelism exploitation (speed) and loal memory size. A hardware module is dediated to a given task. The different osts are omputed as follows :

3 D D C SW DataMemSize gmmemsize C Cop C SW ost i Max revcop i Cop i i C HW HWarea LoalMemSize C R + R + 2 Figure 4: Tasks parameters Time revcop i and Cop i are respetively the number of oproesseur of type i required by previous and urrent tasks. The arhiteture model is given in fig.3, it has been implemented on a FGA Virtex 800 with the free soft I LEON [] whih ommuniates with HW modules (for instane a DCT aelerator) through the amba bus. Moreover, the Leon s RTOS is RTEMS designed for multiproessor arhitetures. Real Time OS Main memory and I/O r o e s s o r M A Cpr Cpr 2 Cpr n Hw/Hw Bus Sw/Hw Bus Coproessors for Critial operations aeleration M A 2 M A n Figure 3: Arhitetural model Communiation memory Aelerators, distributed ontrol When a periodi task is implemented on a hardware module, the proessor RTOS initiliazes the task exeution by ativating the module timer, then the hardware module runs independently from the proessor sheduler. We will see in 4.3 that a real aperiodi task an not be sheduled on a HW omponent. The proessor ontrols HW / SW ommuniations by reading and writing data in dediated hardware modules. 4. ARTITIONING / SCHEDULING METHOD 4. Basi onepts Eah task k is haraterized by the following parameters (see fig.4): Task Id T k Absolute Deadline D k eriod k Release time R k Exeution vetor : Ck CM k where Ck M is the delay assoiated with the M th implementation. Regarding aperiodi tasks, the period means the minimum delay between two suessive exeutions of the task. In the ase of hard real-time onstraints (RTC), this delay is the lower bound but with soft RTC this delay is an average value. 4.2 Sheduling oliy 4.2. Shedulability analysis In order to guaranty RTC, we use a fixed priority stati and preemptive sheduling. The small omplexity of stati shedulers is also an important issue in the domain of embedded real-time systems. Sine the aim is to minimize resoure slak time we don t use the rate monotoni analysis but we ompute the task response time with the basi exat analysis [4, 6]. This analysis onsiders independent periodi tasks with the highest priority first (HF) poliy. The fixed priorities are omputed as the inverse of the deadline. The exat analysis priniple is detailed in, the omplete formulation is given in 2. Thus, a task an be sheduled if the response time RT i of T i is suh as : T j hp i RT i D i with RT i C i j hp i RT i j C j () where hp i is the set of SW tasks whith a higher priority than task i. As t is present on both sides in, it must be omputed iteratively until RT i n RT i n or RT i n D i Resoure sharing onstraints A task T i an be delayed by lower priority tasks T i if they share a ritial resoure (shared memory or I/O). Atually, a ritial resoure an t be used simultaneously by different tasks and a task must ends its job with this resoure even if a higher priority task is waiting for it during its exeution. B i is defined as the longest lok time of the task i due to lower priority task T j with j l p i where l p i is the set of tasks with a lower priority than task T i. The omplete response time analysis (eq.2) takes into aount this loking time Communiation delays Communiations delays are inluded in the exeution time of software and oproessor implementations. (They also inlude an average value of the RTOS overhead). In the HW / HW ommuniations ase, the data are transfered through shared memory and the memory aesses are inluded in estimated exeution times. So, only SW / HW or HW / SW ommuniations introdue new delays. These delays are due to the read and write instrutions that exeute the proessor in the loal HW aelerator memory. Thus, the exat analysis of task shedulability is finally : T j hp i RT i D i with RT i C i B i Tom i j hp i RT i j C j T om j (2) This is not the sope of this paper to detail preisely how HW/SW ommuniation are orrelated with the size of the HW aelerator, but we an indiate that it depends on four parameters given in eq.3 : T init is the initialization delay of the ommuniation, T data is linked with the data format, D mem is the number of data transfered to/from the loal memory of an aelerator and N it the number of times the aelerator is fired to exeute the task (in a given period).

4 Thus, we observe a trade-off between the aelerator parallelism (i.e. memory and proessing unit sizes) and the number of times the hardware module is used during the task exeution. Tom i T init N it D mem T data (3) ) j = i : simple dependeny onstraint 2) nj = mi with n or m > : generalized dependeny onstraint j Dj Rj Cj Communiation hannel Tj Ti i Di Ri Ci Remark: we don t take into aount the release jitter within the omputation as explained in [6] and improved in [0], sine the predeessors of a given task are either sheduled on the same proessor or exeuted on a remote hardware module whose the exat exeution delay is known and the sheduling date hoosen in order to produe data intime as explained in Aperiodi tasks sheduling Like in [3], we onsider the lower bound of the delay between two suessive exeutions as the strit period of an aperiodi task with a hard real time onstraints. For instane the tool detailed in [] produes an intervalle min max for eah aperiodi (sporadi) task within the appliation. Thus by seleting min one an guaranty real time onstraints while systematially alloating time slots (HW or SW) to this task. In pratie, suh a method annot be applied if the task ritiity doesn t justify a ostly alloation of hardware resoures or proessor yles. This trade-off between hard RTC and resoure savings is handled by a task server [4]. This task has the lowest priority. The task server, whose period is fixed by the designer, represents an amount of time slots available for non ritial aperiodi tasks whih will be triggered in a FIFO order. 4.4 Dependent tasks sheduling 4.4. riority assignement & Release time shifting In real life examples, tasks ommuniate so are not independent as speified in 4.2. Usually, before applying the exat response time analysis, the dependenies whih an be related to preedene onstraints are eliminated while modifying absolute deadlines and release times. However, if we onsider generalized data dependenies as shown in fig.5 we an avoid the dependenies onstraints while onsidering a pipeline and stati exeution of dependent tasks. In that ase, the dependenies problem resolution an be redued to a orret hoie of release times. In a ase as depited in fig.5, we assume that n j m i means that the task i needs the data produed by n previous periods of task j, these data are then used during m periods of the task i (if the asumption is not true, the sheduling poliy is not optimal but orret sine this is the worst ase). Atually, T i and T j an be onsidered as independent if T i proesses n data sets previously omputed by the task T j while T j omputes the n next data sets. Thus, the dependeny onstraint an be avoided by orretly shifting release times. If n m this is a single rate dependeny. If n m! this is a single rate dependeny with lateny onstraints, i.e. the task T i starts with the same period after n exeutions of the task T j. So a new release time is omputed. So finally the priority asignment is simply given by : riority T k # D k Release time omputation The shedulability analysis is performed while onsidering independent tasks, then when an implementation solution is found, the Figure 5: reedene generalized onstraints new release times R"i are omputed in order to respet the assumption, namely the preedene onstraints. The omputations are performed in the preedene order within the task graph. Four ases must be distinguished regarding the tasks T j # T i from fig. 5. HW # SW or HW # HW. R"i max $ R i ;R"j % n j C j & T j is implemented on a hardware module so its response time is equal to C j (no interruption). 2. SW # HW. R"i max $ R i ;R"j ' n j TR j Tom j & TR j is the response time of T j and Tom j is the ommuniation delay to be added to TR j for the transfer of data from the proessor to the hardware module memory 3. SW # SW and priority (T j ) priority (T i ) R"i max $ R i ;R"j ' n j & 4. SW # SW and priority (T j ) priority (T i ) R"i max $ R i ;R"j % n j T R j & TR j is omputed with the method of exat analysis (eq.2) but the set of onfliting tasks is no more hp j but hpp j whih inludes two kinds of software tasks : i) the predeessors of T j and ii) higher priority tasks whih are not suessors of task T j. Remark : if T i has several predeessors, R"i is omputed for all its predeessors and the maximal result is seleted. In fig.6 an example of dependeny resolution is given. The exat analysis shows that the four tasks are an be sheduled. Then we ompute the assoiated release times while onsidering T om 0 for simpliity : R" R"2 0 R"3 max( R 3 ;max( R" TR ;R"2 4 2 T R 2)*)+ 520; R"4 max( R 4 ;R"3 2 3 C 3 ) = riniple of the partitioning algorithm We urrently use an exat Branh & Bound algorithm whih find out the lowest ost solution regarding the silion area (so the FGA or Chip size). The B&B tree is organized as follows : on a given branh, tasks are ordered aording to their priority (highest first). And for a given level, implementations are ordered aording to their osts (i.e. left edge solution is fully software).

5 T T : = 300, D = 80, C = 00, R = 0. : 2 = 20, D2 = 80, C2 = 40, R2 = 0. T3 : 3 = 200, D3 = 00, C3 = 40, R3 = 0. T4 : 4 = 300, D4 = 240, C4 = 60, R4 = 0. T, produe data for T3. T3 R3 * T3 onsumes data produed by T and and produes data for T4. T4 R4 * Sw Sw T Hw Sw T3 T4 2* = 5*2 = 3*3 = 2*4 First, we only address ritial tasks, the task server is onsidered afterwards regarding the proessor slak time. The designer an define a minimum slak time alloated to tasks server, If this delay is no suffiient then the server task, with a minimum period, is inluded in the initial task vetor. So, our tool input data are the task vetor : V T T T 2 and the period / deadline vetor : V s, the implementation arrays (fig.8), the ommuniation desriptors (T init T data ), the task desriptors (D i R i ) and the task graph. T4 onsumes data produed by T3. Figure 6: Dependent graph sheduling example The tree is travelled from left to right. So, if a shedulable solution is found for a given task (aording to (2), the right side remaining solutions an be eliminated and the algorithm goes down to the next level (i.e. next task). The main diffiulty of the method appears during the tree exploration when an HW solution is seleted after a SW solution. In that ase the algorithm must go up to the previous level to add the SW/HW ommuniation time and rehek the shedulability of the SW solution. 4.6 Global Methodology Finally the global methodology an be divided in five main steps : / / / / / / / / / / / / In a first step, priorities y i are omputed : y 4, y 2, y 2 3, y 3 4, y 5 5, y 6 y 7 6, y 8 7, y 9 y 0 8, y 9, y 2 0 Seond step, B&B searh : best ost / 668 [(T,Sw), (T 2,Cop), (T 3,Hw), (T 4,Sw), (T 5,Sw), (T 6,Cop), (T 7,Cop), (T 8,Sw), (T 9,Sw), (T 0,Sw), (T,Sw), (T 2,Sw)] Third step, release time omputation : R20 / R30 / R0 / R20 / 288, R40 / 348, R50 / R60 / R70 / R80 / R90 / R00 / In this example, the tasks T 3 T 4 an be assigned to the tasks server (with a priority equals to ) beause the proessor slak time equals 0 %. Both tasks will be orretly sheduled if they don t require more than 0 % of the proessor time, in the opposite ase their exeution will be delayed.. Multi-level system speifiation; 2. System-level estimation : estimation tools are used to produe sw / sw+op / hw trade-off urves; 3. riority assignment & aperiodi task management : the priorities are omputed and set of independent tasks is then onsidered, hard RTC aperiodi tasks are transformed into periodi tasks and weak RTC aperiodi tasks alloated to the server task; T T 4 A.C ontrol = [228, 880] Wheel pulses 660 Dashboard Controller 2 T 5 T 3 B.L ontrol Aumulate pulses Read Speed Compute Total Km T 6 LCD Display T 9 Compute Driver artial Km T 8 T 7 = 2 = Speed ontrol Motor ontrol T T 2 2,3 = [456, 23760] T 3 Filter Speed 24 T 4 4 = [9, 990] 5,6,7,8,9,0 = [3868, ] Speedometer T 0 Speed ontroller Lifetime Odometer Resettable Trip Odometer 4. RT Stati Sheduling / partitioning : the B&B algorithm produes a low ost arhiteture. Regarding the proessor slak time, the task server is defined or step 4 restarted with a task server period onstraint. 5. Task release time omputation : regarding multi-rate and preedene onstraints, the orret task release times are provided to the RTOS. 5. RESULTS In order to get derived onstraints we reuse the Dashboard ontroller example given in [] and desribed in fig.7 (T i for i 0 ). These tasks are aperiodi but have hard real-time onstraints known through intervals min max. So, we onsider these tasks periodi with a period equal to min. In order to extend the appliation sope, we imagine new tasks to be handled by the system. First, we add two periodi tasks T, 2 whih address the speed ontrol. Then, some aperiodi tasks with soft RTC like air onditioning ontrol (T 3 ) or board light ontrol T 4 are introdued as andidates to luster within a the task server. Sine we don t have tasks odes neither HCDFG desriptions, we an only propose oarse sw / sw+op / hw estimates whih are given in fig.8. However, the goal here is mainly the illustration of our approah ombined with onstraint derivation methods. T SW C 60 Cost 20 T 5 SW 5 HW 5 C Cost T 9 SW 9 C 70 Cost 85 Cop Cop 2 Cop 3 Cost op 2 0 op 3 0 op op Figure 7: Car ontroller task graph T 2 SW 2 Cop 2 C Cost T 6 SW 6 Cop 6 C Cost T 0 Sw 0 C 50 Cost 96 T 3 SW 3 Cop 3 HW C Cost T 7 SW 7 Cop 7 C Cost T Sw Hw C Cost T 4 SW 4 C 6 Cost 90 T 8 SW 8 HW 8 C Cost T 2 Sw 2 Hw 2 C Cost Coproessor Implementation osts : The "Cop ij "' ost only inludes the Sw ost as "Cop ij " solution an share oproessors, the final ost is obtained by adding the ost of alloated oproessors. Figure 8: SW/Cop/HW solutions 6. CONCLUSION In this paper we have presented the Sheduling and artitioning task for Real-Time Embedded Systems of our design tool alled Design Trotter. The method is based on a stati fixed priority

6 sheduling and we propose a solution to shedule multirate and aperiodi tasks. The tehnique takes advantage from the task pipelining while the assumption of independent tasks is guaranteed by the shifting of release times. The partitioning algorithm is linked to dynami estimation task whih provides trade-off urves in order to perform a design spae exploration aording to the huge VLSI potential of future system on hip. Our future work will address the refinements of ommuniation and RTOS overhead aspets. Currently a heuristi approah of the B&B algorithm is under development in order to adress large task graphs. 7. REFERENCES [] A.Dasdan, D.Ramanathan, and R.K.Gupta. Rate derivation and its appliation to reative, real-time embedded systems. In 35 th ACM/IEEE Design Automation Conf., San Franiso, USA, 998. [2] A.Kalavade and E.Lee. Global ritiality/loal phase driven algorithm for the onstrained hw/sw partitioning problem. In Int. Work. on H/S Codesign, Sept [3] B..Dave, G.Lakshminarayana, and N.K.Jha. COSYN: Hardware-software o-synthesis of heterogeneous distributed embedded systems. IEEE Trans. on Software Engineering, 7(), Mar [4] B.Sprunt, L.Sha, and J..Lehozky. Aperiodi task sheduling for hard real-time systems. Journal of real-time systems, Sept [5] D.Kirovski and M.otkonjak. System-level synthesis of low-power hard real-time systems. In 34 th ACM/IEEE Design Automation Conf., San Franiso, USA, 997. [6] F.Balarin and A. Sangiovanni-Vinentelli. Shedule validation for embedded reative real-time systems. In 34 th ACM/IEEE Design Automation Conf., Anaheim, USA, 997. [7] F.Charot and V.Messé. A flexible ode generation framework for the design of appliation speifi programmable proessors. In 7 th Int. Work. on H/S Codesign, Roma, Italy, May 999. [8] H.Gomaa. Software Design Methods for Conurrent and Real-Time Systems. Addison-Wesley, 993. [9] H.Oh and S.Sha. A hw/sw o-synthesis tehnique based on heterogeneous multiproessor sheduling. In ACM Int. Symp. CODES, Roma, May 999. [0] J.C.alenia and M. Harbour. Exploiting preedene relations in the shedulability analysis of distributed real-time systems. In 20 th Real-time System Symp., Sottsdale, USA, De [4] M.Joseph and.andya. Finding response time in a real-time system. IEEE Design and Test of Computers, 29(5): , 986. [5] Y. Moulle, J-h.Diguet, and J-L.hilippe. Fast and adaptive dataflow and data-transfer sheduling for large design spae exploration. In 2 th ACM Great Lake Symposium on VLSI, New York, USA, Apr [6] N.Audsley, A.Burns, M.Rihardson, K.Tindell, and A.J.Welling. Applying new sheduling theory to stati priority preemptive sheduling. Software Egineering Journal, pages , sep 993. [7].Bjørn-Jørgensen and J.Madsen. Critial path driven osynthesis for heterogeneous target arhitetures. In 5 th Int. Workshop on H/S Codesign, Codes/CASHE 97, Braunshweig, Germany, Mar [8].Dave and N.K.Jha. CASER: Conurrent hardware-software o-synthesis of hard real-time aperiodi speifiation of embedded system arhitetures. In Design, Automation & Test in Europe Conf., aris, Frane, Feb [9].Eles, K.Kuhinski, Z.eng, A.Doboli, and.op. Sheduling of onditionnal proess graphs for the synthesis of embedded systems. In Design, Automation & Test in Europe Conf., aris, Frane, Feb [20] R.Gupta and G. Mihelli. Hardware-software osynthesis for digital systems. IEEE Design and Test of Computers, Sept [2] R.Kamden, A.Fonkua, and A.Zenatti. Hardware/software partitioning of multirate system using stati sheduling theory. In IEEE Int. Conf. on Computer Design, Texas, Sept [22] T.Grandpierre, C.Lavarenne, and Y.Sorel. Optimized rapid prototyping for real time embedded heterogenous multiproessors. In ACM Int. Symp. CODES, Roma, May 999. [23] T.Y.Yen and W.Wolf. Sensitivity-driven osynthesis of distributed embedded systems. In 8 th IEEE/ACM Int. Symp. on System Synthesis, Cannes, Frane, Sept [24] W.R.Davis, N.Zhang, K.Camera, F.Chen, D.Markovi, N.Chan, B.Nikoli, and R.W.Brodersen. A design environment for high throughput, low power,dediated signal proessing systems. In IEEE Custom Integrated Ciruits Conferene, CICC 200, San Diego, CA, May 200. [] J.Gaisler. Leon spar proessor ore. [2] K.Küçükakar. An ASI design methodology for embedded systems. In 7 th Int. Work. on H/S Codesign, Roma, Italy, May 999. [3] M.Auguin, L.Capella, F.Cuesta, and E.Gresset. Synthesis of signal proessing systems from binary ontrolled data-flow speifations. In Int. Conf. on Signal ro. Appli. & Tehno. (ICSAT), Dallas, USA, Ot