NETWORKS on CHIP A NEW PARADIGM for SYSTEMS on CHIPS DESIGN

Transcription

1 NETWORKS on CHIP A NEW PARADIGM for SYSTEMS on CHIPS DESIGN Giovanni De Micheli Luca Benini CSL - Stanford University DEIS - Bologna University

2 Electronic systems Systems on chip are everywhere Technology advances enable increasingly more complex designs Challenge: how to exploit deepsubmicron technologies efficiently? 2

3 Silicon technology roadmap Year Gate length (nm) Transistor count (million) Chip size (mm 2 ) Clock rate (GHz) Wiring levels Supply voltage (V) Max power (W)

4 Component-based design SoCs are designed (re)-using large macrocells e.g., processors, controllers, memories Goal: plug and play methodology Challenge: Provide a functionally-correct, reliable operation of the interconnected components Weak point: properties of physical interconnect 4

5 SoC trends Computation More, faster blocks Storage Most chip area Heavy, unpredictable data traffic Communication Speed, energy are critical SoCs are interconnect dominated 5

6 Systems on chips: a communication-centric view Design component interconnection under: uncertain knowledge of physical medium incomplete knowledge of data traffic Design interconnection as a micro-network Leverage network design technology Manage information flow To provide for performance Power manage components based on activity To reduce energy consumption 6

7 Micro-network stack Software application system Architecture and control transport network data link Design choices at each stack level affect: Communication speed Reliability Energy Physical wiring 7

8 Chips and networks The micro-network stack gives a way to model communication in chips and networks, but: Networks have non-deterministic behavior Stochastic design methods dominate Chips used to show predictable behavior Because of smaller scale As SoCs become more complex, their information flow will be less predictable 8

9 Micro-networks on SoCs Multi-processors on a chip Use differerent network architectures Designed for performance Application-specific SoCs Micro-network can be tailored to application Low-energy communication Satisfying Quality of Service (QoS) requirements Performance Reliability 9

10 Physical layer Software application system Architecture and control transport network data link Physical design: Voltage levels Driver design Sizing Physical routing Physical wiring 10

11 Physical layer Limitations come from interconnect physics RLC effects on wires -> propagation time Delay on global wires and delay uncertainty Electric signalling Trade-off noise immunity vs. energy vs. speed Small swings -> low energy and fast transitions Challenge: synchronization across large chips Is synchronization possible at high clock rates? What is the probability of synchronization failure? 11

12 Reliability of information Information transfer is inherently unreliable Major causes: Cross-talk Electro-magnetic interference (EMI) Timing errors Soft errors The problem will get more and more acute as technology scales down 12

13 Soft errors Due to charge injection created by: Charged ion (e.g., alpha particle) Neutron scattering (from cosmic rays) Soft error rate increase with: Environment (e.g., altitude, latitude) Decrease of node critical charge (capacitance*voltage) Used to be a problem for DRAMs Now important also for SRAM, registers, etc. 13

14 Modeling transient faults SoC will operate in presence of noise Model noise sources and their effects Single/multiple data upsets Similar to stuck-at models in testing Current design methods reduce noise Physical design (e.g., sizing, routing) Future methods must cope with noise Push solution to higher abstraction levels 14

15 Architecture and control Software application system Architecture and control transport network data link Physical wiring Architectures Shared medium Direct/indirect Hybrid Control protocols Layered Architecture dependent Implemented in Hw or Sw 15

16 Micro-network design Micro-network architectural choice Shared medium (e.g., bus) Router or switch-based Topology: Meshes, butterfly, octagon... Micro-network control Choice of protocols Architecture and protocol choices strongly affect energy/performance levels 16

17 Data link layer Provide reliable data transfer on an unreliable physical channel Most previous/current work addresses: Shared-medium architectures Bus encoding (for low-power) Example: Processor/memory sub-system 17

18 Bus encoding PE 1 PE 2 NET INT DATA CONTROL NET INT 18

19 Advanced bus techniques: CDMA on bus Motivation: many data sources Support multiple concurrent write on bus Discriminate against background noise Spread spectrum of information Driver/receiver multiply data by random sequence generated by LFSR LFSR signature is key for de-spreading Challenge: electrical design of drivers using charge pumps 20

20 Advanced bus techniques: Split transactions Daytona processor: Scaleable DSP multi-processor (MIMD) 128 bit split-transaction bus: Many simultaneous transaction requests Varying size, some large Varying priority Transactions IDs associated with transactions Goal: minimize average latency Round-robin arbitration 21

21 Advanced bus techniques: Error-resilient coding HRDATA AMBA BUS FROM EXT. ICACHE AMBA BUS MEM.CTRL. MEMORY INTERFACE H DECODER H ENCODER Four alternatives Original AMBA bus SEC coding SEC-DED coding ED coding Gaussian noise model (no correlation) 22

22 Reliability For a given residual error probability, what is the line error probability that can be tolerated by the code? 23

23 Energy efficiency The impact of Hamming encoders and decoders over power is negligible w.r.t. that of bus transitions (5pF bus) 24

24 Going beyond buses Buses: Pro: simple, existing standards Contra: performance, energy-efficiency, arbitration Other network topologies: Pro: higher performance, experience with MP Contra: Physical routing, need for transport and network layers Challenge: exploit appropriate network architecture and corresponding protocols 25

25 Network layer Information is in packets Issues: Network switching Circuit, packet, cut-through Network routing Deterministic and adaptive routing Trade-off: delivery time and channel utilization vs. predictability Choice depends on traffic regularity and on availability of computing nodes 26

26 SPIN Micro-network Applied to SoCs [Guerrier, Grenier] 32-bit packets header: destination trailer: checksum Fat-tree network architecture Cut-through switching Deterministic routing EOP Tree routing (for fat tree) Variable size payload Address 27

27 SPIN micro-network Router Router Router Router Router Router Router Router Address Stream Address Stream Address Stream FIR Other CPU RAM Other 28

28 Transport layer Decompose and reconstruct information Important choices Packet granularity Admission/congestion control Packet retransmission parameters All these factors affect heavily energy and performance. Application-specific schemes vs. standards 29

29 Silicon Backplane Micro-Network (SONICS) Bus with time-division multiplexing Node asks arbiter a time slot to communicate Arbitration introduces non-deterministic delay Protocol provides a form of slot reservation A node can reserve a time-slot Deterministic time allocation of bus bandwidth 30

30 Software layers Software application system Architecture and control transport network data link Physical wiring System software OS, RTOS, run-time scheduler Component and network dependent Application software User and standard applications 31

31 Systems software layer SoC modeling abstraction: Queuing network with service stations Control components and information flow Power manage service stations according to information traffic Reconfigure network according to traffic Synergistic design of communication protocols and control policies for computing and storage components 32

32 Control of networked SoCs Exploit widely-varying loads on components. Power-manageable components: Dynamic voltage scaling (DVS) [Transmeta] Adjust frequency and voltage Dynamic power management (DPM): Set idle components into sleep states. Dynamic information-flow management Reconfigure network and protocols dynamically 33

33 Power manageable components Components with several internal states Corresponding to power and service levels Abstracted as a power state machine State diagram with: Power and service annotation on states Power and delay annotation on edges There may be a penalty for a transition Transitions to lower-power state must be entered when overhead can be amortized 34

34 Example: SA-1100 RUN: operational at different f and v. IDLE: a sw routine may stop the CPU when not in use, while monitoring interrupts SLEEP: Shutdown of on-chip activity 50mW 400mW RUN 10us 160ms 10us 90us IDLE 90us SLEEP 160uW 35

35 Networked powermanageable systems Components may: Self-manage state transitions Be controlled externally Components may send requests to neighbors to: Change power states Adjust power/performance Power management policies: Policies encapsulate the control law: Predictive schemes Stochastic control 36

36 Example of randomized policy (one decision point) Policy computation off-line Table construction and storage Policy application at run-time On entry in to IDLE state: obtain a random number RND find first time jh for which RND>p(jh) if no arrival during jh seconds enter SLEEP state else enter RUN state During transition store user requests in the buffer Once in SLEEP state wait until user request comes place device in the RUN state IDLE Optimal Policy RUN Idle time Probability (ms) to lp state jh p(jh) SLEEP 38

37 Policy implementation levels Component Limited system view Component driver Detects busy and idle periods Process manager Knows multiple requesters Better idleness estimation Scheduler Orders processes and affects idle periods Application Inappropriate for multi-tasking application programs operating system scheduler process manager device driver Hw component 39

38 Network-aware system software Lightweight, modular, distributed system Supports component DPM at different levels Supports network re-configuration: Adapts to different modes of operation and environmental factors Challenges: Distributed environment factors: scaleability, re-configurability, robustness,... 40

39 Application layer Given a platform, the performance and energy to realize a function depends on software Different algorithms to embody a function (e.g., sorting) Different coding styles Different instruction streams (e.g. assembly) Software production tools need to address both performance and energy goals 43

40 Software synthesis Application layer Source-code generation Source-level optimizing transformations Application-specific compilation Choice of instructions, registers, schedule Software design tools need network awareness to be effective Balance computation, storage and communication 44

41 Applications and system software Applications should not control directly hardware components and network configuration Applications are aware of hardware resource needs: Component service levels Network configuration Applications can communicate with OS through APIs, by requesting and releasing components (that can be shut down) and connections 45

42 Summary Problem analysis Electronic embedded systems require SoCs with high QoS and low energy consumption The challenge of SoC design is in interconnecting high-level components Design has to cope with non-determinism High-level abstraction Physical properties of material The physical interconnection is unreliable 46

43 Summary Design strategies Reliable communication is achieved by layered design methods: Learn from network and MP design For application-specific SoCs, the network and protocols can be tailored to the application Encoding, packet switching and routing provide a new view of interconnect design The system and application software design are key to manage components and networks 47

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