OCB-Based SoC Integration

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Scarlett Hawkins
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1 The Present and The Future 黃俊達助理教授 Juinn-Dar Huang, Assistant Professor March 11, 2005 Department of Electronics Engineering National Chiao Tung University

2 1 Outlines Present Why Using AMBA 2.0 as an Example Example Platforms Future AXI (AMBA 3.0) as an Example Latency-Insensitive Protocols Other Directions Conclusions

3 2 IP-to-IP Interface FIFO-based (Traditional) FIFO-like input/output interface design become more complicated (unmanageable) when the number of IPs goes large, O(n 2 ) Bus-based (Modern) eliminate direct IP-to-IP link all IPs talk to a common bus handle IP-to-Bus problem only high reusability the backbone of IP-based SoC integration

4 3 Ideal IP-Based SoC

5 4 Without Standard IP Interface

6 5 Why Not Using Existing Bus Protocols? Short answer different goals under different environment For a traditional bus works on PCB I/O pins and PCB area are both precious shared I/O and even multiplexed address/data bus tri-state is unavoidable fixed (absolute) timing requirement for interoperability, e.g., PCI variants, IDE variants fixed address/bus width for interoperability, e.g., 8-bit ISA, 16-bit ISA

7 Modern OCB Protocols Operates on chip, not on PCB No pin issue Routing is not the most critical issue latency and bandwidth are also important Prefer uni-directional mux-based bus to bi-directional tristate bus ease verification, DFT, and timing closure Cycle-related (variable) timing requirement e.g., input delay is 20% of clock cycle time match the modern synthesis flow fast porting from 0.25um to 0.18um, 0.13um, Flexible user-configurable options width of address/data bus arbitration schemes 6

8 7 OCB Example AMBA 2.0

9 8 More Bandwidth Bandwidth provided by a single OCB may be not enough if there exist multiple data-hungry masters CPU + MPEG engine + LCDC + DMAC + DRAMC + increasing frequency and/or data bus width sometimes are not available options Multi-layer architecture is evolved

10 9 Example: Multi-Layer AHB 3-layer AHB System with 3 masters + 4 slaves 3 masters can simultaneously access 3 different slaves

11 10 Example OCB-Based SoC (1/2) Source: ARM Solutions Smart Phones and Communicators

12 Example OCB-Based SoC (2/2) CPU ROM/Flash Controller Expansion Interface LCD Controller AHB APB RTC Timer Counter H-to-P Bridge GPIO DMA Controller Interrupt Controller UART IrDA DRAM Controller Faraday s PDA Platform Touch Panel I/F Audio Codec I/F Source: Faraday s PDA platform,

13 12 What s Next Higher performance (more bandwidth) Higher operating frequency More flexibility

14 13 AXI (AMBA 3.0) AXI (Advanced extensible Interface) by ARM Also named AMBA 3.0 Debut in Embedded Professor Forum (EPF), 2003 Over 30 leading industry organizations Agere, Agilent, ARM, Cadence, Connexant, CoWare, Epson, Ericsson, Fujitsu, HP, Infineon, LSI, Mentor, Matsushita, Motorola, NEC, OKI, Philips, Qualcomm, Samsung, STM, Synopsys, Toshiba, Verisity,

15 Channel Architecture Write Address/Control AWREADY AXI Master Read Address/Control ARREADY Write Data WREADY Read Data RREADY Write Response BREADY 5 unidirectional channels AXI Slave 14

16 15 Read Transaction (1/2) AXI Master AXI Slave Read Address/Control ARREADY Read Data RREADY Master issues address and control

17 16 Read Transaction (2/2) AXI Master AXI Slave Read Address/Control ARREADY Read Data RREADY Slave returns data and response

18 Write Transaction (1/3) Write Address/Control AWREADY AXI Master Write Data WREADY Write Response BREADY Master issues address and control AXI Slave 17

19 Write Transaction (2/3) Write Address/Control AWREADY AXI Master BREADY Write Data WREADY Write Response Master sends data AXI Slave 18

20 Write Transaction (3/3) Write Address/Control AWREADY AXI Master Write Data WREADY Write Response BREADY Slave acknowledges AXI Slave 19

21 20 AMBA 2.0 AHB Burst A31 Address and Data are linked together (by HREADY signal)

22 AXI Burst Start Address for a Burst Reduce the address channel utilization A31 Use Address/Control channel more efficiently 21

23 22 Outstanding Transactions A31 Decouple the fixed link between address and data no HREADY-like signal to synchronize the pipeline Enable parallel processing of transactions Avoid a high-initial-latency slave blocking the channel

24 23 Out-of-Order Completion A31 Fast slaves may return data before slow slaves Complex slaves may return data out of order extremely helpful to DMAC and DRAMC Effectively reduce the transaction latency

25 24 Data Interleaving A31 Further boost the utilization of data bus Data within a burst is always in order each transaction has a unique ID

26 25 Interconnect Matrix Interconnection shared bus architecture multi-layer architecture something in-between Master-like port Slave-like port

27 26 AXI Summary Features channel architecture burst addressing multiple outstanding transactions out of order completion registers slicing Interconnect options shared bus, multi-layer, and hybrid

28 27 Interconnect Delay (1/3) As the complexity of SOC keeps growing RC delay of long wires becomes the timing bottleneck larger die size longer wire across the chip higher operating frequency desired The latency to transmit a signal across the chip may be up to 32 35nm and frequency > 15GHz Paradigm shift from computation-bound to communication-bound

29 Interconnect Delay (2/3) local wires global wires Source: 2001 technology roadmap for semiconductors, Computer, pp , Jan

30 29 Interconnect Delay (3/3) In a 60 nm process, a signal can reach only 5% of the die s length in a clock cycle

31 30 Impacts to OCB OCB protocols with fixed latency requirements become infeasible as wire delay increases Example: AMBA 2.0 specifies that a slave must return HREADY low to the master at the next cycle if it needs wait cycles What if HREADY cannot be returned in one cycle? Current workaround OCB operates at a lower (½, ¼, ) clock rate provide limited bandwidth

32 Latency-Insensitive (LI) Protocols IP1 IP1 S = abcd IP2 IP2 IP1 IP1 Strict System Latency Equivalent (same data stream, different timing) S =...a.b.c...d Patient System IP2 IP2 A shell (wrapper) is required to become latency-insensitive Or, new LI OCB protocols should be developed & used 31

33 How LI Protocols Work (1/2) P1 P2 P3 Pearls (synchronous IP cores) Shells (interface logic blocks) Channels (short wires) Channels (long wires) P4 P6 P7 P5 32

34 How LI Protocols Work (2/2) P1 P2 RS RS P3 Pearls (synchronous IP cores) Shells (interface logic blocks) Channels (short wires) Channels (long wires) RS RS P4 P6 RS : Relay Station RS RS P5 RS P7 33

35 GALS GALS Globally Asynchronous, Locally Synchronous Nexus-based SoC Source: Asynchronous interconnect for synchronous SoC design, IEEE Micro, pp , Jan/Feb

36 S S Network-on-Chip (NoC) S PE S S PE PE PE S S MPEG S Switch PE PE S PE PE S PE PE S Viterbi S FFT S S PE PE PE S PE S PE S PE 35

37 Raw Processor by MIT Proposed by MIT, 1999 Raw Facts IBM SA-27E, 6M Cu, 0.15um 18.2mm x 18.2mm die 122 million transistors 250MHz, 25W, 1080 I/O 4 x 4 = 16 tiles in 2D-mesh Each tile includes MIPS R switch + local memory Source: MIT Raw project 36

38 37 Conclusions OCB-Based integration systematic, flexible, fast turnaround enable platform-based designs facilitate design and verification reuse increase productivity while reducing TTM AMBA 2.0 OCB protocol is the current king Next-generation OCB protocols more flexible, higher bandwidth latency-insensitivity is likely to be a common feature Future for on-chip communication GALS?, NoC?

39 38 References AMBA 2.0 specification AMBA AHB-Lite overview AMBA multi-layer AHB overview AMBA AXI protocol specification, r0p0, June 2003 First Details of AMBA 3.0, Embedded Processor Forum (EPF), June 2003 Coping with latency in SOC design, IEEE Micro, pp , Sep/Oct 2002 Asynchronous interconnect for synchronous SoC design, IEEE Micro, pp , Jan/Feb 2004 MIT Raw project,

IMPROVES. Initial Investment is Low Compared to SoC Performance and Cost Benefits

IMPROVES. Initial Investment is Low Compared to SoC Performance and Cost Benefits NOC INTERCONNECT IMPROVES SOC ECONO CONOMICS Initial Investment is Low Compared to SoC Performance and Cost Benefits A s systems on chip (SoCs) have interconnect, along with its configuration, verification,