Announcements. Advanced Digital Integrated Circuits. No office hour next Monday. Lecture 2: Scaling Trends

Transcription

1 EE4 - Spring 008 Advanced Digital Integrated Circuits Lecture : Scaling Trends Announcements No office hour next Monday Extra office hours Tuesday and Thursday -3pm

2 CMOS Scaling Rules Voltage, V / α tox/α GATE WIRING W/α n+ source n+ drain L/α p substrate, doping α*na xd/α Å SCALING: Voltage: V/α Oxide: t ox /α Wire width: W/α Gate width: L/α Diffusion: x d /α Substrate: α *N A R. H. Dennard et al., IEEE J. Solid State Circuits, (974). RESULTS: Higher Density: ~α Higher Speed: ~α Power/ckt: ~/α Power Density: ~Constant 3 Some Recent Devices In production: 45nm high-k strained Si In research: 0nm device L = 0 nm g K. Mistry, IEDM 07 Corresponds to sub-nm node (>0 years) 4

3 Some Recent Devices Intel s 30nm transistor, circa 00 Ion = 570μA/μm Ioff = 60nA/ μm [B. Doyle, Intel] 5 More Recent Devices Intel s 0nm transistor, circa [B. Doyle, Intel] 6 3

4 More Recent Devices Ultra-Thin-Body (UTB) MOSFET SOI: Silicon-on-Insulator [Choi, UCB] 7 8nm FinFET Double-gate structure + raised source/drain Gate Silicon Fin Source BOX Gate X. Huang, et al, IEDM 999 Drain Si fin - Body! I d [ua/um] V V V V V V V d [V] 8 4

5 Sub-5nm FinFET Lee, VLSI Technology, Major Roadblocks. Managing complexity How to design a 0 billion transistor chip? And what to use all these transistors for?. Cost of integrated circuits is increasing It takes >$0M to design a chip Mask costs are more than $3M in 45nm technology 3. The end of frequency scaling - Power as a limiting factor Dealing with leakages 4. Robustness issues Variations, SRAM, soft errors, coupling 5. The interconnect problem 0 5

6 Transistor Counts Transistor Counts in Intel's Microprocessors 000 Itanium II Trans sistors [in millions] DX 8088 Pentium 4 Pentium II Itanium Pentium Pro Pentium Pentium III 486DX Pentium MMX 486DX4 Doubles every years Core Frequency Frequency Trends in Intel's Microprocessors requency [MHz] Fr DX 386DX Pentium II Pentium Pro Pentium 486DX4 Pentium III Pentium MMX Pentium 4 Core Itanium II Itanium 8088 Has been doubling every years, but is now slowing down

7 Power Dissipation Power [W] Power Trends in Intel's Microprocessors 8088 Has been > doubling every years DX 386DX Pentium Pro Pentium Pentium III Itanium II Itanium Pentium II Pentium 4 Has to stay ~constant Core 3 Active Power Scaling. If Vcc = 0.7, and Freq = Power = CV f ( ( ), 0.7 ) (0.7 ) ( ) 0.7 = =.3. If Power Vcc = 0.7, and = CV f Freq = = (.4 0.7, ) (0.7 ) () =.8 3. If Power Vcc = 0.85, and = CV f = ( 0.7 Freq.4 =, ) (0.85 ) () =.7 4 7

8 Microprocessor power 00 Power (Watts) P6 Pentium proc S. Borkar 999 Lead Microprocessors power continues to increase 5 Power Will Be a Problem Power (Watts) Pentium proc 8KW 5KW.5KW 500W Power delivery and dissipation will be prohibitive S. Borkar

9 Power Density Will Increase Power Density (W/cm m) Sun s Surface Rocket Nozzle Nuclear Reactor Hot Plate P6 Pentium proc S. Borkar 999 Power density too high to keep junctions at low temp 7 Power Delivery Challenges Icc (amp), P6 Pentium proc 486 L(di/dt)/Vdd E+07.E+06.E+05.E+04.E+03.E+0.E+0.E+00.E E-0.E-03.E P6 Pentium proc S. Borkar High supply currents at low voltage: Challenges: IR drop and L(di/dt) noise 8 9

10 The Power Challenge: Hottest chips published at ISSCC 000 Po ower per chip [W W] MPU DSP T. Kuroda, Keio University 9 Moore s Law - Logic Density 000 Logic Transistors/m mm Logic Density μ 386.0μ i860 Pentium II (R) 486 Pentium Pro (R) Pentium (R) 0.8μ 0.6μ 0.35μ 0.5μ x trend 0.8μ 0.3μ Source: Intel S. Borkar Shrinks and compactions meet density goals New micro-architectures drop density 0 0

11 Die Size Growth 00 Die size (mm) P6 486 Pentium proc ~7% growth per year ~X growth in 0 years Die size grows by 4% to satisfy Moore s Law S. Borkar Not Everything Scales G.E. Moore, ISSCC 03

12 Optical Lithography Issues Sub-wavelength lithography 000 micron Lithography 365nm Wavelength 48nm 93nm 80nm 30nm Gap 90nm 65nm Generation 45nm 3nm 3nm EUV nm Source: Mark Bohr, Intel 3 Mask Costs nm Cost [in $000] nm 90nm μm 0.3 μm 0.5 μm Mask costs follow Moore s law as well 4

13 FAB Costs Litho Tool Cost ($K) $00,000 $0,000 $,000 $00 $0 $ Litho Cost G. Moore ISSCC $0,000 Fab Cost ($M) $,000 $00 $0 FAB Cost $ Cost Increases Lithography is more complex Like painting a cm line with a 3cm brush 93nm laser Immersion Cost of exposure system Cost of proximity correction, phase shift masks Cost of mask repair But mask costs drop in subsequent years Economic settings for maskless lithography Design costs increase with added complexity Chip starts ~$0M 6 3

14 Process Variations Control of minimum features does not track feature scaling Relative device/interconnect variations increase Sources: Lithography Feature size, oxide thickness variations Random dopant fluctuations Temperature gradients, supply grid Effects: Speed Power, primary leakage Yield 7 The Interconnect Scare 8 4

15 EE 4 Technology vs. 45nm FEOL 0.5μm features Lg = 0nm 48nm lithography No OPC, liberal design rules SiO oxide, 3.5nm 0 6 dopant atoms LOCOS Nobody knew what is strain Velocity saturated No SD leakage No gate leakage One transistor flavor BEOL Al interconnect SiO ILD 4-5 M layers No CMP, no density rules FEOL 45nm technology Lg = 5nm 9nm immersion lithography OPC, restricted design rules SiO oxide,.nm (or Hf-based dielectric) <0 3 dopant atoms STI Strained silicon in channel Velocity saturated I DS,off ~ 00nA I g ~ 0nA Many transistor flavors BEOL Cu interconnect Lo-k ILD 8-0 M layers CMP, density rules 9 Technology Features. Lithography. Optical proximity correction 3. Shallow trench isolation 4. Hi-k/metal gate 5. Strained silicon 6. Cu interconnect 30 5