Routers Technologies & Evolution for High-Speed Networks

Transcription

1 Routers Technologies & Evolution for High-Speed Networks C. Pham Université de Pau et des Pays de l Adour Congduc.Pham@univ-pau.fr Router Evolution slides from Nick McKeown, Pankaj Gupta nickm@stanford.edu

2 The Internet is a mesh of routers IP Core router The Internet Core IP Edge Router 2

3 The Internet was a mesh of IP routers, ATM switches, frame relay, TDM, Access Network Access Network Access Network Access Network Access Network Access Network Access Network 3

4 Now, the Internet is a mesh of routers mostly interconnected by SONET/SDH TDM TDM TDM TDM Circuit switched crossconnects, DWDM etc. 4

5 Where high performance packet switches are used - Carrier Class Core Router - ATM Switch - Frame Relay Switch The Internet Core Edge Router Enterprise WAN access & Enterprise Campus Switch 5

6 Ex: Points of Presence (POPs) POP2 POP3 A POP1 POP4 D B POP5 E C POP6 POP7 POP8 F 6

7 What a Router Looks Like Cisco GSR Juniper M Capacity: 160Gb/s Power: 4.2kW Capacity: 80Gb/s Power: 2.6kW 6ft 3ft 2ft 2.5ft 7

8 Basic Architectural Components Admission Control Routing Protocols Routing Table Reservation Control Plane Packet Classification Policing & Access Control Forwarding Table Switching Output Scheduling Datapath per-packet processing Ingress Interconnect Egress

9 Basic Architectural Components Datapath: per-packet processing Data Hdr Header Processing Lookup IP Address Update Header Manager Data Hdr Address Table Memory Data Hdr Header Processing Lookup IP Address Update Header Manager Data Hdr Address Table Memory Data Hdr Data Hdr Header Processing Lookup IP Address Update Header Manager Address Table Memory 9

10 Routing constraints Year Throughput (Gbps) 40B (Mpps) 84B (Mpps) 354B (Mpps) GEthernet Added by C. Pham 10

11 RFC 1812: Requirements for IPv4 Routers Must perform an IP datagram forwarding decision (called forwarding) Must send the datagram out the appropriate interface (called switching) Optionally: a router MAY choose to perform special processing on incoming packets 11

12 Examples of special processing Filtering packets for security reasons Delivering packets according to a preagreed delay guarantee Treating high priority packets preferentially Maintaining statistics on the number of packets sent by various routers 12

13 Special Processing Requires Identification of Flows All packets of a flow obey a pre-defined rule and are processed similarly by the router E.g. a flow = (src-ip-address, dst-ipaddress), or a flow = (dst-ip-prefix, protocol) etc. Router needs to identify the flow of every incoming packet and then perform appropriate special processing 13

14 Flow-aware vs Flow-unaware Routers Flow-aware router: keeps track of flows and perform similar processing on packets in a flow Flow-unaware router (packet-bypacket router): treats each incoming packet individually 14

15 Memory limitation Access Time (ns) It s hard to keep up with Moore s Law: The bottleneck is memory speed. 100 Memory speed is not DRAM keeping up with x / 18months Moore s Law. 1 0,1 0, Line Capacity 2x / 7 months Moore s Law 2x / 18 months Router Capacity 2.2x / 18months 0,001 Added by C. Pham 0,

16 First Generation Routers Shared Backplane Fixed length DMA blocks or cells. Reassembled on egress linecard CPU Route Table Memory Line Interface MAC Line Interface MAC Line Interface MAC Most Ethernet switches and cheap packet routers Bottleneck can be CPU, hostadaptor or I/O bus Fixed length cells or variable length packets 16

17 First Generation Routers Queueing Structure: Shared Memory Input 1 Output 1 Input 2 Numerous work has proven and made possible: Fairness Delay Guarantees Delay Variation Control Loss Guarantees Output 2 Statistical Guarantees Input N Large, single dynamically allocated memory buffer: N writes per cell time N reads per cell time. Limited by memory bandwidth. Output N 17

18 Limitations (1) First generation router built with 133 MHz Pentium Instruction time is 7.51ns Mean packet size 500 bytes Interrupt is 10 µs, memory access take 50 ns Per-packet processing time is 200 instructions = µs Copy loop register <- memory[read_ptr] memory [write_ptr] <- register read_ptr <- read_ptr + 4 write_ptr <- write_ptr + 4 counter <- counter -1 if (counter not 0) branch to top of loop 4 instructions + 2 memory accesses = ns Copying packet takes 500/4 * = µs; interrupt 10 µs Total time = µs => speed is Mbps Amortized interrupt cost balanced by routing protocol cost 18

19 Limitations (2) First generation router built with 4 GHz i7 Instruction time is 0.25 ns Mean packet size 500 bytes Negligible interrupt~0, memory access take 5 ns Per-packet processing time is 200 instructions = 50 ns Copy loop register <- memory[read_ptr] memory [write_ptr] <- register read_ptr <- read_ptr + 8 write_ptr <- write_ptr + 8 counter <- counter -1 if (counter not 0) branch to top of loop 4 instructions + 2 memory accesses = 11 ns Copying packet takes 500/8 *11 = ns Total time = ns => speed is 5.8 Gbps Added by C. Pham 19

20 Second Generation Routers CPU Route Table Memory Slow Path Drop Policy Line Card Memory Line Card Memory Line Card Memory Drop Policy Or Backpressure Port mapping intelligence in line cards-better for connection mode Fwding Cache MAC Fwding Cache MAC Fwding Cache MAC Output Link Scheduling Higher hit rate in local lookup cache 20

21 Second Generation Routers As caching became ineffective Exception Processor CPU Route Table Line Card Memory Fwding Table MAC Line Card Memory Fwding Table MAC Line Card Memory Fwding Table MAC 21

22 Second Generation Routers Queueing Structure: Combined Input and Output Queueing 1 write per cell time Rate of writes/reads 1 read per cell time determined by bus speed Bus 22

23 Third Generation Routers q Third generation switch provides parallel paths (fabric) Switched Backplane Line Card Local Memory Fwding Table MAC CPU Card Routing Table Line Card Local Memory Fwding Table MAC 23

24 Third Generation Routers Queueing Structure 1 write per cell time Rate of writes/reads 1 read per cell time determined by switch fabric speedup Switch Arbiter 24

25 Review: crossbar, general design Simplest possible spacedivision switch Crosspoints can be turned on or off, long enough to transfer a packet from an input to an output Expensive need N2 crosspoints time to set each crosspoint grows quadratically Data In configuration Data Out C. Pham, University of Pau, France

26 Switch Fabrics: ed crossbar (packets) What happens if packets at two inputs both want to go to same output? Can defer one at an input buffer Or, buffer cross-points: complex arbiter C. Pham, University of Pau, France

27 Switch fabric element Goal: towards building self-routing fabrics Can build complicated fabrics from a simple element data 10 data Routing rule: if 0, send packet to upper output, else to lower output If both packets to same output, buffer or drop C. Pham, University of Pau, France

28 Multistage crossbar In a crossbar during each switching time only one cross-point per row or column is active N/n arrays n x k k arrays N/n x N/n N/n arrayw k x n Can save crosspoints if a cross-point can attach to more than one input line This is done in a multistage crossbar C. Pham, University of Pau, France

29 Banyan element (1 possible configuration) 110 data 10 data ATM has boosted research on high-performance switches C. Pham, University of Pau, France

30 Batcher-Banyan switch a same direction than arrow if a > b, a opposite direction if a is alone C. Pham, University of Pau, France

31 management Input buffers Output buffer C. Pham, University of Pau, France

32 Still, cost of datagram packet switching A With IP datagram mode, packet lookup is performed for each packet R3 R1 R4 D B C D D R2 Destination D D Next Hop R3 R5 F E E R3 F C. Pham, University of Pau, France R5

33 Class-based lookups netid port# 23 Port 1 Class A Class B Class C Port 2 Exact match Port 3 C. Pham, University of Pau, France

34 Using longest prefix (CIDR: classless routing) Longest Prefix Match (Classless) Forwarding Destination = payload Prefix Next Hop Interface OK better / ATM 5/0/ / ATM 5/0/8 even better / Ethernet 0/1/3 best! /23 attached Serial 1/0/7 C. Pham, University of Pau, France IP Forwarding Table

35 CIDR/VLSM lookup Find the most specific route, or the longest matching prefix among all the prefixes matching the destination address of an incoming packet /22, R /24, R /22, R / / / Cost of packet lookup is further increased!!! C. Pham, University of Pau, France

36 Reliability of circuit switching SW SW Trunk lines SW SW SW SW PABX PABX SW C. Pham, University of Pau, France

37 Traditional circuit in telephony Simple, efficient, but low flexibility and wastes resources N MUX Fixed bandwitdh N De- MUX 1 sample every 125us gives a 64Kbits/s channel N Packet-switching with virtual circuit: take advantages of both worlds C. Pham, University of Pau, France

38 Virtual Circuit Connections & Virtual circuits table label R3 Label IN Link IN Label OUT Link OUT Link 1 Link Virtual Circuit: X.25 & Frame Relay. ATM: same principle but much smaller packet size A B C C. Pham, University of Pau, France R1 R2 R3 R4 R5 D E

39 Setting up a virtual circuit (1) VCI E. Lien E. VCI S. Lien S. A CR@B 0 45 A 0 67 B 2 05 C VCI E. Lien E. VCI S. Lien S A 1 34 B 2 23 C 3 05 A CR@B B 0 41 C 1 13 A 2 15 B 1 62 C 0 4 CR@B 13 VCI E. Lien E. VCI S. Lien S CR@B 5 B C VCI E. Lien E. VCI S. Lien S

40 Setting up a virtual circuit (2) VCI E. Lien E. VCI S. Lien S. A data 0 45 A 0 67 B 2 05 C VCI E. Lien E. VCI S. Lien S A 1 34 B 2 23 C 3 05 A data B 0 41 C 1 13 A 2 15 B 1 62 C 0 4 data 13 VCI E. Lien E. VCI S. Lien S data 5 B C VCI E. Lien E. VCI S. Lien S

41 Link failure with virual circuit VCI E. Lien E. VCI S. Lien S. A data 0 45 A 0 67 B 2 05 C VCI E. Lien E. VCI S. Lien S A 1 34 B 2 23 C 3 05 A data data B 0 41 C 1 13 A 2 15 B 1 62 C 0 4 VCI E. Lien E. VCI S. Lien S data 5 B C VCI E. Lien E. VCI S. Lien S

42 Using virtual circuit to decrease lookup cost Introduced by X.25, Frame Relay, ATM Use labels to forward packets/cells Label in Label out Output port C. Pham, University of Pau, France

43 VC & VP: introducing hierarchy Virtual Circuit Virtual Path Transmission Path A VPC = 1 VP or a concatenation of several VPs. A VCC = 1 VC or a concatenation of several VCs. A VP contains several VCs Avantages Simple connection setup for most used paths Easy definition of Virtual Private Networks (VPN), Simplier traffic management: traffics with different constraints can be transported in different VPs for isolation. C. Pham, University of Pau, France

44 2 level switching C. Pham, University of Pau, France

45 Advantages of VP and VC hierarchy Re-routing a VP automatically re-routes all VCs of the VP Towards Traffic Engineering!! C. Pham, University of Pau, France

46 Optics in routers Optical links Switch Core Linecards 46

47 Complex linecards Typical IP Router Linecard Lookup Tables & State Memory Optics Physical Layer Framing & Maintenance Packet Processing Mgmt & Scheduling Mgmt & Scheduling Switch Fabric & State Memory Arbitration 10Gb/s linecard: v Number of gates: 30M v Amount of memory: 2Gbits v Cost: >$20k v Power: 300W 47

48 Replacing the switch fabric with optics Typical IP Router Linecard Typical IP Router Linecard Lookup Tables & State Memory & State Memory Lookup Tables Optics Physical Layer Framing & Maintenance Packet Processing Mgmt & Scheduling Mgmt & Scheduling & State Memory 1. MEMs. electrical Switch Fabric Mgmt & Scheduling Mgmt & Scheduling Arbitration Candidate technologies & State Memory Packet Processing 2. Fast tunable lasers + passive optical couplers. 3. Diffraction waveguides. 4. Electroholographic materials. Framing & Maintenance Physical Layer Optics Typical IP Router Linecard Lookup Tables & State Memory optical Typical IP Router Linecard & State Memory Lookup Tables Optics Physical Layer Framing & Maintenance Packet Processing Mgmt & Scheduling Mgmt & Scheduling & State Memory Req/Grant Switch Fabric Arbitration Req/Grant Mgmt & Scheduling Mgmt & Scheduling & State Memory Packet Processing Framing & Maintenance Physical Layer Optics 48