UPCRC Overview. Universal Computing Research Centers launched at UC Berkeley and UIUC. Andrew A. Chien. Vice President of Research Intel Corporation

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1 UPCRC Overview Universal Computing Research Centers launched at UC Berkeley and UIUC Andrew A. Chien Vice President of Research Intel Corporation

2 Announcement Key Messages Microsoft and Intel are announcing the establishment of two Universal Parallel Computing Research Centers with the first locations at the University of Illinois at Urbana-Champaign and the University of California at Berkeley. Under this alliance, Microsoft and Intel have committed to invest a combined $20 million in the center over the next five years The center will explore the next generation of hardware and software for parallel computing and enable a revolutionary change in the way people use technology. 2

3 Multi-core is now mainstream Motivated by a need for better performance/watt 100% 75% 50% 25% 0% SINGLE-CORE* MULTI-CORE Market Market Crossover Crossover to to multi-core multi-core in in Source: Intel Q3 05 Q4 05 Q1 06 Q2 06 Q3 06 Q4 06 Over 6 MU Quad-core In 2007 Multi-core Top to Bottom 3

4 Moore s Law Motivates Multi-Core Source: Intel 45nm More, better transistors More cores benefits Continued benefits from Moore s s Law

5 A Shift to Many Cores Parallelism will enable tera-scale performance for new apps Rich Visual Computing Performance TIPS GIPS MIPS KIPS Multi- Media Text 3D & Video Kilobytes Models Single-core Megabytes Tera-scale Many cores Multi-core Gigabytes Dataset Size Turing Data into Understanding Printer Printer X42 X42 Terabytes Sensing & Perception Health 5

6 Wanted: Breakthrough Innovations in Parallelism P Programming Effort Sequential Programming Effort P Programming that doesn t increase programming complexity Productivity, Modularity, Interactions, Performance Tuning, etc. P Programming Approaches that have forward scalability Application implementation gets faster (more parallel) on succeeding generations of hardware platforms Scale data sets, scale output quality more parallelism without reprogramming or retuning P Programming implementation techniques that deliver high and robust parallel performance Enable programming at a high level Manage workload, algorithm, and data irregularlity Manage hardware differences and irregularity HW Architecture Innovations that Support Parallel Programs 6

7 Intel: Making Parallel Computing Pervasive Joint HW/SW R&D program to enable Intel products 3-7+ in future Intel Tera-scale Research Academic Research UPCRCs Academic research seeking disruptive innovations years out Software Products Enabling Parallel Computing Multi-core Education Wide array of leading multi-core SW development tools & info available today Community and Experimental Tools Multi-core Education Program Universities - 25,000+ students Goal: Double this Intel Academic Community TBB Open Sourced Threading for Multi-core SW STM-Enabled Compiler on community Whatif.intel.com Multi-core books Parallel Benchmarks at Princeton s s PARSEC site 7

8 Today: Universal Parallel Computing Research Centers Catalyze breakthrough research enabling pervasive use of parallel computing Parallel Programming Languages, Compilers, Runtime, Tools Parallel Applications For desktop, gaming, and mobile systems Parallel Architecture Support new generation of programming models and languages Parallel Sys. S/W Performance scaling, memory Utilization, & power consumption 8

9 UPCRC Partners in Research Intel & Microsoft provide funding and guidance Universities direct groundbreaking research Prof. Wen-Mei Hwu Professor David Patterson UCB UPCRC Director Prof. Marc Snir UIUC UPCRC Co-Directors 9

10 UPCRC Funding Strategy Intel + Microsoft $20 Million over 5 years Matching University Investments University of Illinois: $8 mil (committed) UC Berkeley: $7 mil (grant application) Leadership $$ Guidance Matching Fund H/W & S/W Companies Innovation Trained Researchers Academia State Govs Government Major investment in mainstream parallel programming 10

11 Future of Parallelism Computing For Software and Hardware Parallelism in all computing systems Dramatic new capabilities enabled by performance and performance / unit power Established and varied software models for portable parallelism Architecture support for Parallel Software and other capabilities 11

12 BACKGROUND 12

13 Single Core Performance is Stagnant Source: Intel Multi-core performance: P ~ Area 0.01 Time 13 Frequency (GHz) Performance Single Stream Performance P ~ Area Gap driving us to Multi-core Jan -85 Jan -86 Jan -87 Jan -88 Jan -89 Jan -90 Jan -91 Jan -92 Jan -93 Jan -94 Jan -95 Jan -96 Jan -97 Jan -98 Jan -99 Jan -00 Jan -01 Jan -02 Jan -03 Jan -04 Jan -05 Jan -06 Jan -07 Jan -08 Jan -09 Transistor Count (area) Frequency limited by leakage and power. Transistor counts continue to increase.

14 Many-core Research Questions Abound Cores How many? What size? Homogenous, Heterogeneous Programmable, Configurable, Fixed-function Chip-level Interconnect: Topology, Bandwidth Coordination Management Memory Hierarchy # of levels, sharing, inclusion Bandwidth, novel Technology Integration/Packaging I/O Bandwidth Silicon-based photonics Terabit links Source: CTWatchQuarterly, Feb 2007 Manycore Chips (circa. 2012)? 14

15 Intel s Tera-scale Research Vision Parallel Programming Tools & Techniques Virtual Environments Educational Simulation Financial Modeling Media Search & Manipulation Web Mining Bots Model-Based Applications Thread-Aware Execution Environment Stacked, Shared Memory Scalable Multi-core Architectures High Bandwidth I/O & Communications 15

16 Copyright Intel Corporation. *Other names and brands may be claimed as The property of others. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise or used for any public Purpose under any circumstance, without the express written consent and permission of Intel Corporation. 16