N E W S R E L E A S E
|
|
- Godfrey Turner
- 5 years ago
- Views:
Transcription
1 Chartered Semiconductor Manufacturing Ltd. (Regn. No.: K ) N. McCarthy Blvd., Ste. 100 Milpitas, California Tel: (1) Fax: (1) Woodlands Industrial Park D Street Two Singapore Tel: (65) Fax: (65) N E W S R E L E A S E Media Contacts: Chartered U.S.: Tiffany Sparks (1) tiffanys@charteredsemi.com Chartered Singapore: Celestine Lim (65) celestinelim@charteredsemi.com CHARTERED BEGINS PRODUCTION RAMP OF ENHANCED 65nm LOW-POWER PROCESS; IMPROVES POWER UTILIZATION BY PERCENT 65nm LPe process reduces leakage (Ioff) by 20x, extending battery life in high-volume mobile applications SINGAPORE July 13, 2009 Chartered Semiconductor Manufacturing (Nasdaq: CHRT and SGX-ST: CHARTEREDSC), one of the world s top dedicated foundries, today announced the general availability of an enhanced version of its 65-nanometer (nm) low-power (LP) process, called 65nm LPe. The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent. The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities. Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications ).
2 The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process pmosfet. Given the same Ion (ua/um), the Ioff current is reduced by a magnitude of 20X. This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as percent, depending on the application. A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic. The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process. ARM is pleased to expand our long standing relationship with Chartered by offering a full complement of physical IP optimized for Chartered 65LPe process, said Simon Segars, executive vice president and general manager PIPD division, ARM. This rich platform of IP includes enhanced memories and logic targeted at improving the performance of ARM processors. All products are supported by the most advanced power management EDA views. We believe this combination of 65LPe process and ARM physical IP is well suited to a range of mainstream applications where leakage optimization is paramount. Through the sponsorship of Chartered, the libraries are free and available today at We have worked closely with Chartered to optimize our SiWare Memory and SiWare Logic solutions to their 65nm LPe process to meet our mutual customers SoC requirements, said Brani Buric, vice president of marketing and sales at Virage Logic. With a comprehensive dashboard of options, the SiWare product line provides the flexibility needed to efficiently manage design tradeoffs to meet low power as well as performance design requirements.
3 Chartered s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors respectively. Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency. Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pmosfet hole mobility and saturation velocity without detrimentally affecting the nmosfet. Today s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don t compromise performance or functionality, said Brian Klene, vice president, product marketing at Chartered. Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based. Industry Support for Chartered 65nm LPe Process The Chartered 65nm LPe process is well-suited for the demands of power-sensitive mobile applications. With Analog Bits low-power, clocking macros, programmable interconnects and specialized memories, our customers can realize significant differentiation with high yield and reliability. We have a long heritage and well-proven track record of working closely with Chartered on each successive process generation, and we can optimize our product lines to work very efficiently with their underlying process. This helps streamline the design flow for designers and allows our technology to leverage the full potential of the advances Chartered has made in its manufacturing technology. Mahesh Tirupattur Executive VP Analog Bits, Inc.
4 Recognized worldwide as a premier IP provider, Aragio Solutions has expanded the Chartered 65nm IO offerings to the LPe process node. Using the knowledge and success of prior 65nm lowpower and generic process nodes, Aragio has been able to provide a full complement of siliconproven LPe IO libraries with excellent electrical and ESD performance, enabling highperformance operation for many industry standard interfaces - including USB 2.0, Ethernet, LVDS, Mobile DDR and DDR - as well as RF and Analog ESD protection circuitry. The diverse number of metal options made available for clients points to the team effort required between Chartered and Aragio to make this program successful. Glen Haas, Chief Technologist Aragio Solutions Cosmic Circuits, a leading provider of differentiated analog and mixed-signal IP cores, has enjoyed a history of tight partnership with Chartered, especially in the nanometer technology nodes. We are happy that our joint efforts on the 65nm LPe node have also been successful. It enables our common customers to leverage a portfolio of silicon-proven mixed-signal cores, including data-converters and power-management for low-power portable applications. This was essentially possible through the early access to Chartered s process technology, and through the R&D investments that Cosmic Circuits continually makes. Following this launch, we look forward to serve customers actively and experience all-around success. Ganapathy Subramaniam CEO Cosmic Circuits Denali and Chartered have taped out Denali s LPDDR1/DDR2 memory controller and digital PHY on the 65nm LPe process. Our customers will be attracted to the enhanced speed of the Chartered 65nm LPe process, where we ve achieved timing at 800MT/s and transfer rates up to 3.2GBytes/sec over a 32-bit DDR2 memory interface, while giving the flexibility to support lowpower LPDDR1 memories on the same interface. Marc Greenberg Director, Technical Marketing Denali Software
5 The 65nm process node is a mainstream design node for SoC developers in the consumer multimedia markets in terms of its low-power performance and production yield capabilities. We offer a broad portfolio of analog IP including audio codecs and interface IP, such as USB, HDMI, PCI Express and SATA for Chartered s 65nm LPe node to enable SoC designs to get to market faster with lower risk. John Koeter Vice President of Marketing for the Solutions Group Synopsys, Inc. About Chartered Chartered Semiconductor Manufacturing Ltd. (Nasdaq: CHRT, SGX-ST: CHARTEREDSC), one of the world s top dedicated semiconductor foundries, offers leading-edge technologies down to 40/45 nanometer (nm), enabling today s system-onchip designs. The company further serves its customers needs through a collaborative, joint development approach on a technology roadmap that extends to 22nm. Chartered s strategy is based on open and comprehensive design enablement solutions, manufacturing enhancement strategies, and a commitment to flexible sourcing. In Singapore, the company owns or has an interest in six fabrication facilities, including a 300mm fabrication facility and five 200mm facilities. Information about Chartered can be found at
Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications
Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications A Collaborative White Paper by RAMBUS and GLOBALFOUNDRIES W h i
More informationCommon Platform Ecosystem Enablement
Joe Abler Common Platform Ecosystem Enablement IBM provides a complete Foundry solution Innovative technology Leadership road map with advanced SiGe & RF offerings Leading-edge CMOS process development
More informationSoitec ultra-thin SOI substrates enabling FD-SOI technology. July, 2015
Soitec ultra-thin SOI substrates enabling FD-SOI technology July, 2015 Agenda FD-SOI: Background & Value Proposition C1- Restricted July 8, 2015 2 Today Ultra-mobile & Connected Consumer At Any Time With
More informationSynopsys Design Platform
Synopsys Design Platform Silicon Proven for FDSOI Swami Venkat, Senior Director, Marketing, Design Group September 26, 2017 2017 Synopsys, Inc. 1 Synopsys: Silicon to Software Software Application security
More informationDr. Ajoy Bose. SoC Realization Building a Bridge to New Markets and Renewed Growth. Chairman, President & CEO Atrenta Inc.
SoC Realization Building a Bridge to New Markets and Renewed Growth Dr. Ajoy Bose Chairman, President & CEO Atrenta Inc. October 20, 2011 2011 Atrenta Inc. SoCs Are Driving Electronic Product Innovation
More informationCMP Model Application in RC and Timing Extraction Flow
INVENTIVE CMP Model Application in RC and Timing Extraction Flow Hongmei Liao*, Li Song +, Nickhil Jakadtar +, Taber Smith + * Qualcomm Inc. San Diego, CA 92121 + Cadence Design Systems, Inc. San Jose,
More informationWhite Paper. The Case for Developing Custom Analog. Custom analog SoCs - real option for more product managers.
The Case for Developing Custom Analog Custom analog SoCs - real option for more product managers. White Paper The contents of this document are owned or controlled by S3 Group and are protected under applicable
More informationTechnology & Manufacturing. Laurent Bosson Executive Vice President Front End Technology & Manufacturing
Technology & Manufacturing Laurent Bosson Executive Vice President Front End Technology & Manufacturing Manufacturing and Technology Strategy LEADING EDGE TECHNOLOGY + SHAREHOLDER VALUE TIME TO MARKET
More informationDesign Solutions in Foundry Environment. by Michael Rubin Agilent Technologies
Design Solutions in Foundry Environment by Michael Rubin Agilent Technologies Presenter: Michael Rubin RFIC Engineer, R&D, Agilent Technologies former EDA Engineering Manager Agilent assignee at Chartered
More informationSoC Memory Interfaces. Today and tomorrow at TSMC 2013 TSMC, Ltd
SoC Memory Interfaces. Today and tomorrow at TSMC 2013 TSMC, Ltd 2 Agenda TSMC IP Ecosystem DDR Interfaces for SoCs Summary 3 TSMC Highlights Founded in 1987 The world's first dedicated semiconductor foundry
More informationFOR IMMEDIATE RELEASE. Toshiba Corporation Corporate Communications Office Phone:
FOR IMMEDIATE RELEASE Toshiba Corporation Corporate Communications Office Phone: +81-3-3457-2105 http://www.toshiba.co.jp/contact/media.htm SanDisk Corporation Media Contact: Ryan Donovan Phone: +1-408-801-2857
More informationTransforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry. Dr. Thomas de Paly
Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry Dr. Thomas de Paly October 06, 2009 Opportunity Meets Vision Vision To be the first truly global semiconductor foundry,
More informationDesignWare IP for IoT SoC Designs
DesignWare IP for IoT SoC Designs The Internet of Things (IoT) is connecting billions of intelligent things at our fingertips. The ability to sense countless amounts of information that communicates to
More informationKevin Donnelly, General Manager, Memory and Interface Division
Kevin Donnelly, General Manager, Memory and Interface Division Robust system solutions including memory and serial link interfaces that increase SoC and system quality. Driving Factors for Systems Today
More informationIntroducing the FX-14 ASIC Design System. Embargoed until November 10, 2015
Introducing the FX-14 ASIC Design System Embargoed until November 10, 2015 Market Forces Are Driving Need for a New Breed of Semiconductor By 2019: Bandwidth Roughly one million minutes of video will cross
More informationTechnology for Innovators TM TI WIRELESS TECHNOLOGY DELIVERING ALL THE PROMISE OF 3G
Technology for Innovators TM TI WIRELESS TECHNOLOGY DELIVERING ALL THE PROMISE OF 3G 1 BROAD PORTFOLIO OF FLEXIBLE, SCALABLE SOLUTIONS From traditional voice-centric mobile phones to the most advanced,
More informationToshiba America Electronic Components, Inc. Flash Memory
Toshiba America Electronic Components, Inc. Flash Memory Fact Sheet Company Overview Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation
More informationTechnology Platform Segmentation
HOW TECHNOLOGY R&D LEADERSHIP BRINGS A COMPETITIVE ADVANTAGE FOR MULTIMEDIA CONVERGENCE Technology Platform Segmentation HP LP 2 1 Technology Platform KPIs Performance Design simplicity Power leakage Cost
More informationTechnology & Manufacturing
Technology & Manufacturing Kevin Ritchie Senior Vice President Technology and Manufacturing Group Development & Manufacturing Strategy Process Technology Leadership Flexible Development Options Internal
More informationiphone 5 and iphone 7 (April 14 and 17, 2017) iphone 5 WiFi module iphone 7 battery application processors wafer level packaging 3D NAND
iphone 5 and iphone 7 (April 14 and 17, 2017) iphone 5 WiFi module iphone 7 battery application processors wafer level packaging 3D NAND 1 iphone 5 2 WiFi Front End in iphone 5 3 Broadcom BCM4334 inside
More informationTechnology and Manufacturing
Technology and Manufacturing Executive Vice President Field Trip 2006 - London, May 23rd Field Trip 2006 - London, May 23rd Technology Technology Development Centers and Main Programs CMOS Logic Platform
More informationTSBCD025 High Voltage 0.25 mm BCDMOS
TSBCD025 High Voltage 0.25 mm BCDMOS TSI Semiconductors' 0.25 mm process is a feature rich platform with best in class CMOS, LDMOS, and BiPolar devices. The BCD technology enables logic, Mixed-Signal,
More informationTechnology & Manufacturing. Kevin Ritchie Senior vice president, Technology & Manufacturing
Technology & Manufacturing Kevin Ritchie Senior vice president, Technology & Manufacturing 27 in review Manufacturing strategy continues to deliver financial results Accelerating analog leadership Increased
More informationtechnology Leadership
technology Leadership MARK BOHR INTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUP DIRECTOR, PROCESS ARCHITECTURE AND INTEGRATION SEPTEMBER 19, 2017 Legal Disclaimer DISCLOSURES China Tech and Manufacturing
More informationHigh Volume Manufacturing Supply Chain Ecosystem for 2.5D HBM2 ASIC SiPs
Open-Silicon.com 490 N. McCarthy Blvd, #220 Milpitas, CA 95035 408-240-5700 HQ High Volume Manufacturing Supply Chain Ecosystem for 2.5D HBM2 ASIC SiPs Open-Silicon Asim Salim VP Mfg. Operations 20+ experience
More informationMicrosemi IP Cores Accelerate the Development Cycle and Lower Development Costs
Microsemi IP Cores Accelerate the Development Cycle and Lower Development Costs October 2014 Introduction Today s FPGAs and System-on-Chip (SoC) FPGAs offer vast amounts of user configurable resources
More informationAccelerating Innovation
Accelerating Innovation In the Era of Exponentials Dr. Chi-Foon Chan President and co-chief Executive Officer, Synopsys, Inc. August 27, 2013 ASQED 1 Accelerating Technology Innovation Exciting time to
More information3D systems-on-chip. A clever partitioning of circuits to improve area, cost, power and performance. The 3D technology landscape
Edition April 2017 Semiconductor technology & processing 3D systems-on-chip A clever partitioning of circuits to improve area, cost, power and performance. In recent years, the technology of 3D integration
More informationIMPROVES. Initial Investment is Low Compared to SoC Performance and Cost Benefits
NOC INTERCONNECT IMPROVES SOC ECONO CONOMICS Initial Investment is Low Compared to SoC Performance and Cost Benefits A s systems on chip (SoCs) have interconnect, along with its configuration, verification,
More informationFinFET Technology Understanding and Productizing a New Transistor A joint whitepaper from TSMC and Synopsys
White Paper FinFET Technology Understanding and Productizing a New Transistor A joint whitepaper from TSMC and Synopsys April, 2013 Authors Andy Biddle Galaxy Platform Marketing, Synopsys Inc. Jason S.T.
More informationIO & ESD protection 1.8V & 3.3V capable general purpose digital IO pad based on 1.8V devices for TSMC 28nm CMOS technology
Data sheet IO & ESD protection 1.8V & 3.3V capable general purpose digital IO pad based on 1.8V devices for TSMC 28nm CMOS technology Sofics has verified its TakeCharge ESD protection clamps on TSMC 28nm
More informationPrinted and Flexible Devices for Smart Systems On Foils
Printed and Flexible Devices for Smart Systems On Foils M. Bedjaoui CEA/LITEN 5 OCTOBRE 2012 CEA 10 AVRIL 2012 PAGE 1 Table of content CEA/LITEN Energy storage solutions on foil Electrochromic devices
More informationDriving Leading Edge Microprocessor Technology
Driving Leading Edge Microprocessor Technology Dr. Hans Deppe Corporate Vice President & General Manager AMD in Dresden AMD Overview A leading global supplier of innovative semiconductor solutions for
More informationChapter 5: ASICs Vs. PLDs
Chapter 5: ASICs Vs. PLDs 5.1 Introduction A general definition of the term Application Specific Integrated Circuit (ASIC) is virtually every type of chip that is designed to perform a dedicated task.
More informationBaseband IC Design Kits for Rapid System Realization
Baseband IC Design Kits for Rapid System Realization Lanbing Chen Cadence Design Systems Engineering Director John Rowland Spreadtrum Communications SVP of Hardware Engineering Agenda How to Speed Up IC
More informationWill Silicon Proof Stay the Only Way to Verify Analog Circuits?
Will Silicon Proof Stay the Only Way to Verify Analog Circuits? Pierre Dautriche Jean-Paul Morin Advanced CMOS and analog. Embedded analog Embedded RF 0.5 um 0.18um 65nm 28nm FDSOI 0.25um 0.13um 45nm 1997
More informationIridium and FURUNO Announce Strategic Partnership
Iridium and FURUNO Announce Strategic Partnership Maritime Navigation and Communications Equipment Leader Will Begin Marketing Iridium(R) Mobile Satellite Communications Products and Services MCLEAN, Va.,
More information3D-IC is Now Real: Wide-IO is Driving 3D-IC TSV. Samta Bansal and Marc Greenberg, Cadence EDPS Monterey, CA April 5-6, 2012
3D-IC is Now Real: Wide-IO is Driving 3D-IC TSV Samta Bansal and Marc Greenberg, Cadence EDPS Monterey, CA April 5-6, 2012 What the fuss is all about * Source : ECN Magazine March 2011 * Source : EDN Magazine
More informationCEL combines the agility of a start-up with the technology of a semiconductor giant to deliver components that keep you competitive.
B u i l d i n g B lo c k s f o r a B u s y Wo r l d CEL combines the agility of a start-up with the technology of a semiconductor giant to deliver components that keep you competitive. Incorporated in
More informationConference paper Latch-up immune ESD Protection Clamp for High Voltage optimized on TSMC BCD technology
Conference paper Latch-up immune ESD Protection Clamp for High Voltage optimized on TSMC BCD technology TSMC Open Innovation Platform 2011 Applications like motor control, power management and conversion,
More informationSamsung emcp. WLI DDP Package. Samsung Multi-Chip Packages can help reduce the time to market for handheld devices BROCHURE
Samsung emcp Samsung Multi-Chip Packages can help reduce the time to market for handheld devices WLI DDP Package Deliver innovative portable devices more quickly. Offer higher performance for a rapidly
More informationSo you think developing an SoC needs to be complex or expensive? Think again
So you think developing an SoC needs to be complex or expensive? Think again Phil Burr Senior product marketing manager CPU Group NMI - Silicon to Systems: Easy Access ASIC 23 November 2016 Innovation
More informationF O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O N. Design Support
F O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O N www.umc.com Design Support Design Support Solutions Overview UMC's Design Support Solutions provide customers with a practical and
More informationUPCRC Overview. Universal Computing Research Centers launched at UC Berkeley and UIUC. Andrew A. Chien. Vice President of Research Intel Corporation
UPCRC Overview Universal Computing Research Centers launched at UC Berkeley and UIUC Andrew A. Chien Vice President of Research Intel Corporation Announcement Key Messages Microsoft and Intel are announcing
More information90-nm To 10-nm Physical IP For Wearable Devices & Application Processors Navraj Nandra Synopsys, Inc. All rights reserved. 1
90-nm To 10-nm Physical IP For Wearable Devices & Application Processors Navraj Nandra 2015 Synopsys, Inc. All rights reserved. 1 Process Requirements are Specific to Customer/Market Need Wearable / IoT
More informationTechTarget s Client Consulting Services: Committed to maximizing your marketing ROI
White paper TechTarget s Client Consulting Services: Committed to maximizing your marketing ROI Best practices and strategic consulting services to keep you ahead of the market Client Consulting is a global
More informationMobile, Multimedia & Communications. Tommi Uhari Executive Vice President MMC Group
Mobile, Multimedia & Communications Tommi Uhari Executive Vice President MMC Group 2007 Accomplishments Leading positions* # 1 in Analog/mixed signal # 1 in 3G RF # 3 in Wireless Focus on high-growth segments
More informationUsing IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation
Using IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation CDNLive Boston August 2013 Mark Marlett and Mahesh Tirupattur, Analog Bits Ken Willis and Kumar Keshavan, Cadence
More informationCollaborate to Innovate FinFET Design Ecosystem Challenges and Solutions
2013 TSMC, Ltd Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions 2 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges
More informationSTM32MP1 Microprocessor Continuing the STM32 Success Story. Press Presentation
STM32MP1 Microprocessor Continuing the STM32 Success Story Press Presentation What Happens when STM32 meets Linux? 2 + = Linux The STM32MP1 Microprocessor Happens! 3 Available NOW! Extending STM32 success
More informationR&D TECHNOLOGY DRIVING INNOVATION. Samsung Semiconductor, Inc. SAMSUNG SEMICONDUCTOR, INC. 1
R&D TECHNOLOGY DRIVING INNOVATION Samsung Semiconductor, Inc. SAMSUNG SEMICONDUCTOR, INC. 1 R&D & CORE COMPONENTS _ SAMSUNG is the world s largest memory chip and display maker, as well as the second largest
More informationRevolutionizing RISC-V based application design possibilities with GLOBALFOUNDRIES. Gregg Bartlett Senior Vice President, CMOS Business Unit
Revolutionizing RISC-V based application design possibilities with GLOBALFOUNDRIES Gregg Bartlett Senior Vice President, CMOS Business Unit RISC-V: Driving New Architectures and Multi-core Systems GF Enabling
More informationUnited for Excellence
United for Excellence Dear Customers, With the rising performance and shrinking feature sizes of our leading-edge production technologies, UMC's customers today enjoy unprecedented opportunities to develop
More informationThe Fujitsu ASIC Platform:
: Combining Engineering Expertise with Best-in-Class Tools and Process Technology to Deliver Cost-Efficient Custom Silicon TECHNOLOGY BACKGROUNDER Introduction Advanced ASIC (Application Specific Integrated
More informationAddressable Test Chip Technology for IC Design and Manufacturing. Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03
Addressable Test Chip Technology for IC Design and Manufacturing Dr. David Ouyang CEO, Semitronix Corporation Professor, Zhejiang University 2014/03 IC Design & Manufacturing Trends Both logic and memory
More informationAll Programmable: from Silicon to System
All Programmable: from Silicon to System Ivo Bolsens, Senior Vice President & CTO Page 1 Moore s Law: The Technology Pipeline Page 2 Industry Debates Variability Page 3 Industry Debates on Cost Page 4
More informationEXTREMELY LOW-POWER AI HARDWARE ENABLED BY CRYSTALLINE OXIDE SEMICONDUCTORS
Semiconductor Energy Laboratory: White Paper EXTREMELY LOW-POWER AI HARDWARE ENABLED BY CRYSTALLINE OXIDE SEMICONDUCTORS Semiconductor Energy Laboratory (SEL): Extremely low-power AI chips can be built
More informationVeloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics
Veloce2 the Enterprise Verification Platform Simon Chen Emulation Business Development Director Mentor Graphics Agenda Emulation Use Modes Veloce Overview ARM case study Conclusion 2 Veloce Emulation Use
More informationLP-DDR. How Much Power Will a Low-Power SDRAM Save you? Marc Greenberg Director, Technical Marketing Denali Software, Inc.
LP-DDR How Much Power Will a Low-Power SDRAM Save you? Marc Greenberg Director, Technical Marketing Denali Software, Inc. 1 Introduction There are two types of DRAM chips commonly used in embedded systems.
More informationCADENCE DESIGN SYSTEMS, INC. Second Quarter 2018 Financial Results Conference Call
Page 1 CADENCE DESIGN SYSTEMS, INC. Second Quarter 2018 Financial Results Conference Call Prepared Remarks of Lip-Bu Tan, Chief Executive Officer and John Wall, Senior Vice President and Chief Financial
More informationLow-Power Technology for Image-Processing LSIs
Low- Technology for Image-Processing LSIs Yoshimi Asada The conventional LSI design assumed power would be supplied uniformly to all parts of an LSI. For a design with multiple supply voltages and a power
More informationLayout Analysis I/O. Analysis from an HD Video/Audio SoC
Sample Report Analysis from an HD Video/Audio SoC For any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500,
More informationAdvanced Heterogeneous Solutions for System Integration
Advanced Heterogeneous Solutions for System Integration Kees Joosse Director Sales, Israel TSMC High-Growth Applications Drive Product and Technology Smartphone Cloud Data Center IoT CAGR 12 17 20% 24%
More informationSample Table of Contents
Sample Table of Contents from System-on-Chip (SoC) For any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500,
More informationCutting Power Consumption in HDD Electronics. Duncan Furness Senior Product Manager
Cutting Power Consumption in HDD Electronics Duncan Furness Senior Product Manager Situation Overview The industry continues to drive to lower power solutions Driven by: Need for higher reliability Extended
More informationA 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias. David Kidd August 26, 2013
A 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias David Kidd August 26, 2013 1 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved. Agenda DDC transistor and PowerShrink platform
More informationPARTNERING FOR SUCCESS PARTNER NETWORK
PARTNERING FOR SUCCESS PARTNER NETWORK PointClickCare Partner Network 204 PointClickCare aims to align with companies that share a similar passion for improving the lives of seniors and who have complementary
More informationInternational Journal of Scientific & Engineering Research, Volume 5, Issue 2, February ISSN
International Journal of Scientific & Engineering Research, Volume 5, Issue 2, February-2014 938 LOW POWER SRAM ARCHITECTURE AT DEEP SUBMICRON CMOS TECHNOLOGY T.SANKARARAO STUDENT OF GITAS, S.SEKHAR DILEEP
More informationIntroducing the 22FDX. 22nm FD-SOI Platform. from GLOBALFOUNDRIES
Introducing the 22FDX 22nm FD-SOI Platform from GLOBALFOUNDRIES March 2016 Introduction Selecting a next generation technology platform for your new product is a critical decision. Product requirements
More informationSmart Data Center Solutions
Smart Data Center Solutions New Data Center Challenges Require New Solutions Data Center Architecture. Inside and Out. Data centers are mission-critical facilities. A silo-based approach to designing,
More informationeasic Technology & Nextreme Architecture
easic Technology & Nextreme Architecture Tomer Kabakov Director of Sales tomer@easic.com Tel: 054-4304032 1 easic at a Glance Fabless Semiconductor Company Provider of Structured ASIC Products Founded
More informationSilicon Labs Corporate Overview
Silicon Labs Corporate Overview APRIL 2018 The leader in silicon, software and solutions for a smarter, more connected world. A World-Class Design Culture In 1996, a visionary group of engineers pioneered
More informationSilicon Labs Corporate Overview
Silicon Labs Corporate Overview MARCH 2018 The leader in silicon, software and solutions for a smarter, more connected world. A World-Class Design Culture In 1996, a visionary group of engineers pioneered
More informationAn Executive View of Trends and Technologies in Electronics
An Executive View of Trends and Technologies in Electronics All rights reserved. Safe Harbor Statement and Regulation G Safe Harbor Statement The following discussion contains forward looking statements,
More informationJames Lin Vice President, Technology Infrastructure Group National Semiconductor Corporation CODES + ISSS 2003 October 3rd, 2003
Challenges for SoC Design in Very Deep Submicron Technologies James Lin Vice President, Technology Infrastructure Group National Semiconductor Corporation CODES + ISSS 2003 October 3rd, 2003 1 Contents
More informationSupporting Advanced-Node FinFET SoCs with 16Gbps Multi-Protocol SerDes PHY IP
Supporting Advanced-Node FinFET SoCs with 16Gbps Multi-Protocol IP By William Chen and Osman Javed, Cadence Design Systems Applications such as the Internet of Things, cloud computing, and high-definition
More informationTIRIAS RESEARCH. Lowering Barriers to Entry for ASICs. Why ASICs? Silicon Business Models
Technology industry Reporting Insights Advisory Services Whitepaper by TIRIAS Research June 20, 2017 There has never been a better time to build your own custom application specific integrated circuit
More informationMoore s Law: Alive and Well. Mark Bohr Intel Senior Fellow
Moore s Law: Alive and Well Mark Bohr Intel Senior Fellow Intel Scaling Trend 10 10000 1 1000 Micron 0.1 100 nm 0.01 22 nm 14 nm 10 nm 10 0.001 1 1970 1980 1990 2000 2010 2020 2030 Intel Scaling Trend
More informationEnabling Electronic Devices, Materials, and Processes with Physically Flexible ICs. Rich Chaney
Enabling Electronic Devices, Materials, and Processes with Physically Flexible ICs Rich Chaney Image from performancemanagementcompany.com Image from: theapplecollection.com Traditional Crunchy (rigid)
More informationStacked Silicon Interconnect Technology (SSIT)
Stacked Silicon Interconnect Technology (SSIT) Suresh Ramalingam Xilinx Inc. MEPTEC, January 12, 2011 Agenda Background and Motivation Stacked Silicon Interconnect Technology Summary Background and Motivation
More informationNXP Smart Washing Machine Solution
NXP Smart Washing Machine Solution 恩智浦智能洗衣机方案 Mike Mui Senior Sales Director, Global Appliance Segment NXP Semiconductors July, 2012 Content NXP & Major Home Appliances Home Automation Market Generic Smart
More informationLow Power SRAM Techniques for Handheld Products
Low Power SRAM Techniques for Handheld Products Rabiul Islam 5 S. Mopac, Suite 4 Austin, TX78746 5-4-45 rabiul.islam@intel.com Adam Brand Mission College Blvd Santa Clara, CA955 48-765-546 adam.d.brand@intel.com
More informationConference paper ESD Design Challenges in nano-cmos SoC Design
Conference paper ESD Design Challenges in nano-cmos SoC Design SoC conference 2008 The Silicon Controlled Rectifier ( SCR ) is widely used for ESD protection due to its superior performance and clamping
More informationCluster-based approach eases clock tree synthesis
Page 1 of 5 EE Times: Design News Cluster-based approach eases clock tree synthesis Udhaya Kumar (11/14/2005 9:00 AM EST) URL: http://www.eetimes.com/showarticle.jhtml?articleid=173601961 Clock network
More informationFreescale i.mx Applications Processors based on ARM Technology Connected Multimedia
Freescale i.mx Applications Processors based on ARM Technology Connected Multimedia 2010 ARM Technology Symposiums Vivek Tyagi- Country Sales Manager, Freescale India Freescale, the Freescale logo, CodeWarrior,
More informationEKOHEAT Induction Heating Systems
EKOHEAT Induction Heating Systems EKOHEAT with VPA Technology TM Unique Versatility and Exceptional Performance Through a First-of-its-Kind in Product Design Architecture. The introduction of our next
More informationUnited for Excellence
United for Excellence Dear Customers, With the rising performance and shrinking feature sizes of our leading-edge production technologies, UMC's customers today enjoy unprecedented opportunities to develop
More informationOn-chip ESD protection for Internet of Things ON-CHIP PROTECTION
ON-CHIP PROTECTION for electrostatic discharge (ESD) and electrical overstress (EOS) On-chip ESD protection for Internet of Things Cisco predicts that more than 50 Billion devices will be connected to
More information54 th DAC EXHIBITOR PROSPECTUS
54 th DAC EXHIBITOR PROSPECTUS Austin Convention Center Austin, Texas Exhibition: June 19-21, 2017 Conference: June 18-22, 2017 DAC.com sponsored by: in technical cooperation with: NETWORK ENGAGE AND EDUCATE
More informationSoCtronics Corporate Overview Industry s 1st Design FoundryTM
SoCtronics Corporate Overview Industry s 1st Design FoundryTM Headquarters Hyderabad, India Design Center Santa Clara, California Company Profile One-stop SoC design service company Operating since 2003
More informationBOEING OVERVIEW. Connect Protect Explore Inspire. Copyright 2018 Boeing. All rights reserved.
BOEING OVERVIEW Connect Protect Explore Inspire HISTORY The First 100 Years Founded in 1916 in the Puget Sound region of Washington state Became a LEADING PRODUCER of military and commercial aircraft Completed
More informationReduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
More informationTOWER SEMICONDUCTOR COMPLETES MERGER WITH JAZZ TECHNOLOGIES
NEWS ANNOUNCEMENT FOR IMMEDIATE RELEASE TOWER SEMICONDUCTOR COMPLETES MERGER WITH JAZZ TECHNOLOGIES Merger Creates: Leading specialty foundry with increased capacity and scale offering a comprehensive
More informationEmbedded Hardware and Software
Embedded Hardware and Software Saved by a Common Language? Nithya A. Ruff, Director, Product Marketing 10/11/2012, Toronto Synopsys 2012 1 Synopsys Industry Leadership $1,800 $1,600 $1,400 $1,200 $1,000
More informationMEDIA RELEASE FOR IMMEDIATE RELEASE Singapore, 6 January 2010 Total: 8 pages (including Notes to the Editor)
MEDIA RELEASE FOR IMMEDIATE RELEASE Singapore, 6 January 2010 Total: 8 pages (including Notes to the Editor) A*STAR s Exploit Technologies and Institute for Infocomm Research launch world s first adaptive
More informationRTL LEVEL POWER OPTIMIZATION OF ETHERNET MEDIA ACCESS CONTROLLER
RTL LEVEL POWER OPTIMIZATION OF ETHERNET MEDIA ACCESS CONTROLLER V. Baskar 1 and K.V. Karthikeyan 2 1 VLSI Design, Sathyabama University, Chennai, India 2 Department of Electronics and Communication Engineering,
More informationF O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O N. 28 Nanometer.
F O U N D R Y L E A D E R S H I P F O R T H E S o C G E N E R A T I O N 28 28 Nanometer www.umc.com 28 Nanometer UMC's 28nm process technology is developed for applications that require the highest performance
More informationMixed-Signal. From ICs to Systems. Mixed-Signal solutions from Aeroflex Colorado Springs. Standard products. Custom ASICs. Mixed-Signal modules
A passion for performance. Mixed-Signal solutions from Aeroflex Colorado Springs Standard products Custom ASICs Mixed-Signal modules Circuit card assemblies Mixed-Signal From ICs to Systems RadHard ASICs
More informationZatara Series ARM ASSP High-Performance 32-bit Solution for Secure Transactions
1 ARM-BASED ASSP FOR SECURE TRANSACTIONS ZATARA SERIES 32-BIT ARM ASSP PB022106-1008 ZATARA SERIES ADVANTAGE SINGLE-CHIP SOLUTION BEST FEATURE SET IN POS PCIPED PRE-CERTIFIED EMV L1 CERTIFIED TOTAL SOLUTION
More informationIf you can't read the mail, please visit here»
If you can't read the mail, please visit here» About Fujitsu Semiconductor Limited Asia With the development of the Chinese semiconductor industry, it has become a key concern in the industry as to how
More information