Computer Architecture Homework Set # 1 COVER SHEET Please turn in with your own solution

Transcription

1 CSCE 614 (Fall 2017) Computer Architecture Homework Set # 1 COVER SHEET Please turn in with your own solution Eun Jung Kim Write your answers on the sheets provided. Submit with the COVER SHEET. If you need additional sheets for any of the problems, use the Additional Work Sheet page (as many copies as you require). Name : ID Number: Print your name clearly. No late homework will be accepted. You are expected to write up your solutions on your own, without referring to other students works or to solutions you may find on the web. This homework is due at the beginning of class on Thursday, September 21 st, 2017.

2 1. A certain benchmark contains 195,700 floating-point operations. The benchmark was run on an embedded processor after compilation. There are two systems to compare. One is based on a RISC processor that includes floating-point function units. The other is a embedded processor without floating-point units. The compiler allows floating-point instructions to be calculated with the hardware units or using software routines, depending on compiler flag. The benchmark took 1.08 seconds on the RISC processor and 13.5 seconds using software on its embedded version. Assume that the CPI using the RISC processor was measured to be 10, while the CPI of the embedded version of the processor was measured to be 6. Also assume that both the RISC and the embedded processors have the same clock cycle time. (a) What are the total numbers of instructions executed for the RISC processor and the embedded processor, respectively? (b) What are the MIPS ratings for the RISC processor and the embedded processor, respectively? (c) On the average, how many integer instructions does it take to perform a floating-point operation in software?

3 2. Assume that we make two enhancement modes to a computer, A and B. Mode A provides a speedup of 10 and mode B provides a speedup of 100. While using the enhancements, 50% of the time is spent in enhancement A (only A is applied), 25% is spent in enhancement B (only B is applied), and 10% of the time is spent in BOTH enhancements A and B (both A and B are applied, gaining a speedup of 1000 for that part of the code). (a) What is the speedup obtained from A used alone, B used alone, and both used together? (b) What percentage of the original execution time has been converted to mode A only? Mode B only? And both modes A and B together? 3. With a MIPS pipeline architecture, we can have four different branch alternatives as follows. Assume we have a 500MHz machine for which the following measurements have been made and the CPI of instruction except branch is 1. What are the MIPS rates for each scheme? Assume 4% unconditional branch, 6% conditional branch- untaken, 10% conditional branchtaken. Scheduling Penalty Stall pipeline 4 Predict taken 1 Predict not taken 2 Delayed branch 0.5 Table 1. Performance penalty

4 4. The following table presents the power consumption of several computer system components. We will explore how the hard drive affects power consumption for the system. Component type Product Performance Power Processor Sun Niagara 8-core 1.2 GHz 72-79W peak Intel Pentium 4 2 GHz W DRAM Kingston X64C3AD2 1 GB 184-pin 3.7W Kingston D2N3 1 GB 240-pin 2.3W Hard drive DiamondMax rpm 7.0W read/seek, 2.9W idle DiamondMax Plus rpm 7.9W read/seek, 4.0W idle Table 2. Power consumption of computer system components (a) Assuming the maximum load for each component, and a power supply efficiency of 80%, what wattage must the servers power supply deliver to a system with an Intel Pentium 4 chip, 2 GB 240-pin Kingston DRAM, and one 7200 rpm hard drive? (b) How much power will the 7200 rpm disk drive consume if it is idle roughly 60% of the time? (c) Given that the time to read data off a 7200 rpm disk drive will be roughly 75% of a 5400 rpm disk, at what idle time of the 7200 rpm disk will the power consumption be equal, on average, for the two disks?

5 5. The main reliability measure is MTTF. We will now look at different systems and how design decisions affect their reliability. (a) We have a single processor with an FIT of 200. What is the MTTF for this system? (b) If it takes three days to get the system running again, what is the availability of the system? 6. Imagine that the government, to cut costs, is going to build a supercomputer out of the cheap processor system in Problem 5 rather than a special purpose reliable system. What is the MTTF for a system with 150 processors? Assume that if one fails, they all fail.

6 7. Consider executing the following code on the pipelined datapath of Figure 1 shown below. add $2, $1, $3 lw $4, 100($2) sub $6, $4, $3 Figure 1: Pipelined Datapath How many cycles will it take to execute this code, considering all the dependencies?

7 8. Given the full single-cycle datapath below, label the datapath and control signals for the instruction lw $1, addr($2). Add brief text if necessary to clarify what activity is occurring in each part of the datapath and what the control signals are doing.