Computer Architecture

Transcription

1 Computer Architecture Mehran Rezaei

2 Welcome Office Hours: TBA Office: Eng-Building, Last Floor, Room 344 Tel: Course Web Site: eng.ui.ac.ir/~m.rezaei/architecture/index.html 2

3 Text book Computer Organization & Design: The Hardware/Software Interface David A. Patterson and John E. Hennessy 5 th Edition, Morgan Kaufmann, / 3

4 Overview Intro to Computer Architecture Administrative Matters Course Style, Philosophy and Structure High Level, Assembly, and Machine Language Anatomy of computer system Computer Architecture realistic view 4

5 What is Computer Architecture Computer Architecture =? 5

6 What is Computer Architecture Computer Architecture = Instruction Set Architecture + Machine Organization 6

7 Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, SOFTWARE -- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Set -- Instruction Formats -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions Slide from Dave Patterson

8 The Instruction Set: a Critical Interface software instruction set hardware 8 Slide from Dave Patterson

9 Example ISAs (Instruction Set Architectures) Alpha (v1, v3,, ev8) HP PA-RISC (v1.1, v2.0) Sun Sparc (v8, v9) SGI MIPS(MIPS I,, IV, V) Intel (4004,, 8086, 80486, Pentium, MMX, PII,, PIV, Itanium, Xeon) 9

10 MIPS R3000 Instruction Set Architecture Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management Special 3 Instruction Formats: all 32 bits wide Registers R0 - R31 PC HI LO OP OP OP rs rt rd sa funct rs rt immediate jump target 10

11 Organization Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALU, Shifters, Logic Units,...) Ways in which these components are interconnected Information flows between components Data path Logic and means by which such information flow is controlled. Control unit Choreography of FUs to realize the ISA 11

12 What is Computer Architecture? Application Operating System Compiler Instr. Set Proc. Firmware I/O system Instruction Set Architecture Datapath & Control Digital Design Circuit Design Layout Coordination of many levels of abstraction Under a rapidly changing set of forces Design, Measurement, and Evaluation Slide from Dave Patterson 12

13 Course Style (overview handout) Grade breakdown Exams: 60% Projects 30% Homework Assignments: 10% No late homework Passing Grade Projects + Homework : necessary requirements Reasonable grades on exams (50% above) 13

14 Academic Honesty vs. Cheating Don t cheat If you submit something, it should be your own work Scholarly work Give credit to whom you get the idea from Plagiarizing is forbidden What happens if you cheat I will inform Department Provost I will give you an F What I am trying to say is Do not cheat 14

15 Course Materials (Systematically) Instruction Set Architecture CPU design, single cycle and pipelined CPU Memory Systems Measuring the performance of computer system 15

16 Where are we? Intro to Computer Architecture Administrative Matters Course Style, Philosophy and Structure High Level, Assembly, Machine Language Anatomy of computer system Computer Architecture realistic view 16

17 High Level, Assembly, Machine language, and control signals High Level Language Program Compiler Assembly Language Program Assembler Machine Language Program temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) Machine Interpretation Control Signal Specification 17 ALUOP[0:3] <= InstReg[9:11] & MASK Slide from Dave Patterson

18 Levels of Organization (computer Anatomy) SPARCstation 20 Workstation Design Target: 25% of cost on Processor 25% of cost on Memory (minimum memory size) Rest on I/O devices, power supplies, box Computer Processor Control Datapath Memory Devices Input Output 18 Slide from Dave Patterson

19 Another view CPU Cache DRAM Secondary Storage Hard disk Controller Video Monitor Video Controller Keyboard Keyboard Controller I/O Bus Network NIC I/O Expansion BIU Memory Controller Bridge System Bus 19

20 Example Organization TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 SuperSPARC MBus Module Floating-point Unit Integer Unit L2 $ CC MBus DRAM Controller Inst Cache Ref MMU Bus Interface Data Cache Store Buffer L64852 SBus SBus DMA SBus Cards MBus control M-S Adapter SCSI Ethernet STDIO serial kbd mouse audio RTC Boot PROM Floppy 20

21 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Result Store Deposit results in storage for later use Next Instruction Determine successor instruction 21

22 DLQ Computer Architecture is? 22

23 (final thoughts) Forces on Computer Architecture Technology Programming Languages Applications Computer Architecture Operating Systems History 23

24 Why Technology Matters

25 Log2 of Number of Components per Integrated Function A Prediction by Gordon Moore year Courtesy of the graph Cramming more components onto integrated circuits, Electronics, 38(8), April

26 The Growth in CPU Speed (lately) Chip's nam e EV EV EV EV EV8 Introduced X X Technology m m m m 0.35 m m 0.18 m m m m Transistors 1.68 M 9 M 15 M 152 M 250 M Frequency MHz MHz GHz GHz GHz Architecture 2-Way In-Order 4-Way In-Order 4-Way Out-Of-Order 4-Way Out-Of-Order 8-Way Out-Of-Order System on a Chip 4-Way SMT, SoC Sources: J. S. Emer. Simultaneous Multithreading: Multiplying Alpha's Performance, 12 th Microprocessor Forum, October R. E. Kessler. The Alpha Microprocessor, IEEE Micro, 19(2), pp , March/April V. A. Klauser. Trends in High Performance Microprocessor Design, Telematik, 7(1), pp , April

27 Pace In Memory Speed Row Access Strobe (RAS) 27 Column Access Strobe (CAS)/ Year of Slowest Fastest data transfer Cycle Introduction Chip Size DRAM (ns) DRAM (ns) time (ns) time (ns) K bit K bit M bit M bit M bit M bit M bit M bit M bit Courtesy of the table:j. L. Hennessy and D. A. Patterson. L. Hennessy and D. A. Patterson. ``Computer Architecture: A Quantitative Approach'', Morgan Kaufmann Publishers, Third Edition 2003.

28 Performance CPU-Memory Speed Gap Memory CPU Ever-increasing CPU-Mem S-Gap Year Courtesy of the Graph:J. L. Hennessy and D. A. Patterson. ``Computer Architecture A Quantitative Approach'', Morgan Kaufmann Publishers, Third Edition

29 DLQ 5 Stages of Instruction Execution? 5 main Components of any computer system? 29