APEX Devices APEX 20KC. High-Density Embedded Programmable Logic Devices for System-Level Integration. Featuring. All-Layer Copper.
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1 APEX Devices High-Density Embedded Programmable Logic Devices for System-Level Integration APEX 0KC Featuring All-Layer Copper Interconnect July 00
2 APEX programmable logic devices provide the flexibility and high density needed for system-on-a-programmable-chip (SOPC) applications. Their MultiCore architectures combine the benefits of look-up table (LUT) logic with embedded memory, saving board space and simplifying complex system design. APEX devices also offer True-LVDS dedicated circuitry for 80-Mbps data transfer rates. APEX 0KC devices, manufactured using all-layer copper interconnect technology, feature increased performance to address the high-bandwidth needs of communications applications.
3 APEX: A Revolutionary Embedded Architecture Figure. Improved Performance with APEX 0KC Devices The Altera APEX device family offers complete system-level integration on a single device. With the innovative MultiCore architecture, APEX FPGAs combine and enhance the strengths of previous programmable logic device (PLD) architectures and deliver the ultimate in design flexibility and efficiency for high-performance, SOPC applications (Figure 1). The new APEX 0KC devices are manufactured on a 0.15 µm all-layer copper interconnect technology to address the high-density, high-performance needs of communication applications. Performance 0 FLEX 10KE Aluminum 0.5-µm 6-layer metal APEX 0K Aluminum 0.-µm 6-layer metal APEX 0KE Aluminum 0.18-µm 8-layer metal Process and Metal Layers APEX 0KC All-Layer Copper 0.15-µm 8-layer metal With densities ranging from 30,000 to over 1.5 million gates (113,000 to over. million maximum system gates), APEX devices feature performance enhancements such as copper interconnect technology and multiple phase-locked loops (PLLs). With the APEX True-LVDS circuitry, this family can achieve data transfer rates up to 80 Mbps and is designed to be 6-bit, 66-MHz PCI and PCI-X compliant. The.5-V APEX 0K devices are fabricated on an advanced 0.-µm, six-layer-metal SRAM process. The 1.8-V APEX 0KE devices, which are a functional superset of the APEX 0K devices, utilize a 0.18-µm, eight-layer-metal process. The 1.8-V APEX 0KC devices are fabricated on a 0.15-µm all-layer copper eight-layer-metal process for improved performance (Figure ). Tables 1 to (pages to 5) provide details of the APEX devices features. Figure 1. APEX Device Features MultiCore Architecture LUT Memory Embedded System Block (ESB) ESB Dual-Port RAM ROM CAM Breakthrough MultiCore Architecture The innovative APEX MultiCore architecture contains two types of PLD structures: the look-up table (LUT) logic of FLEX 10K and FLEX 6000 devices and the enhanced embedded memory blocks of FLEX 10KE devices. Both structures are combined into a single integrated architecture, eliminating the need for multiple devices, saving board space, and simplifying the implementation of complex designs. The MultiCore architecture introduces a new level of hierarchy called the MegaLAB structure. Each MegaLAB structure contains 16 logic array blocks (LABs) that consist of 10 logic elements (LEs), each of which are used to implement LUT logic and an advanced embedded structure called embedded system blocks (ESBs). The MegaLAB local interconnect ties the 16 LABs and the ESBs together without using valuable global routing resources. The MegaLAB structures are connected by the FastTrack interconnect continuous routing structure for fast, predictable delays. I/O Features LVDS SSTL-/-3 GTL+ HSTL CTT LVPECL AGP MultiVolt I/O Clock Management Up to PLLs ClockShift Circuitry ClockBoost Circuitry ClockLock Circuitry Altera Corporation 3
4 Table 1. APEX Device Highlights Feature 80-Mbps data rates All-layer-copper interconnect MultiCore architecture Embedded system block (ESB) PCI compliance Support for emerging I/O standards SignalTap II logic analysis Density up to 1.5 million gates (. million system gates) 1.8-V and.5-v operation Up to four phase-locked loops (PLLs) MultiVolt I/O operation FineLine BGA packaging Vertical migration Benefit High-speed I/O interface to provide a true system-level programmable solution Improves performance by 5% to 35% over aluminum-based devices Integrates LUT logic and memory into a single architecture Implements dual-port RAM, first-in first-out (FIFO) buffers, ROM, and content-addressible memory CAM Meets all specifications for 6-bit, 66-MHz PCI compliance and PCI-X support Supports LVDS, LVTTL, LVCMOS, GTL+, CTT, AGP, HSTL, LVPECL, and SSTL-/-3 I/O standards Improves verification of chip functionality Addresses system-level density needs Reduces power consumption Supports ClockLock, ClockBoost, and ClockShift circuitry, 1x to 160x clock multiplication, and 1 to 56 clock division with an extended frequency range Ideal for mixed-voltage systems Area-optimized, better thermal characteristics, high-pin-count BGA offerings, and packaging migration flexibility Addresses changing density without the need to re-spin the board Table. APEX 0KC Device Features (1.8 V) Device Maximum system gates Logic elements (LEs) Maximum RAM bits Phase-locked loops (PLLs) Speed grades 1 EP0K00C 56,000 8,30 106,96-7, -8, -9 EP0K00C 1,05,000 16,60 1,99-7, -8, -9 EP0K600C 1,537,000,30 311,96-7, -8, -9 EP0K1000C 1,77,000 38,00 37,680-7, -8, -9 Notes: 1-7 is the fastest speed grade in the APEX 0KC family. Table 3. APEX 0KE Device Features (1.8 V) Device EP0K30E EP0K60E EP0K100E EP0K160E EP0K00E EP0K300E EP0K00E EP0K600E EP0K1000E EP0K1500E Maximum system gates Logic elements (LEs) Maximum RAM bits Phase-locked loops (PLLs) 113,000 1,00,576 16,000,560 3,768 63,000,160 53,8 0,000 6,00 81,90 56,000 8,30 106,96 78,000 11,50 17,56 1,05,000 16,60 1,99 1,537,000,30 311,96 1,77,000 38,00 37,680,39,000 51,80,368 Speed grades 1-1, -, -3-1, -, -3-1, -, -3-1, -, -3-1, -, -3-1, -, -3-1, -, -3-1, -, -3-1, -, -3-1, -, -3 Maximum user I/O pins Package Maximum User I/O Pins 1-Pin TQFP 1-Pin FineLine BGA 3 08-Pin PQFP Pin PQFP Pin FineLine BGA Pin BGA 8-Pin FineLine BGA Pin BGA 67-Pin FineLine BGA 1,00-Pin FineLine BGA F Notes: 1-1 is the fastest speed grade in the APEX 0K and APEX 0KE families TQFP: thin quad flat pack 3 BGA: ball-grid array PQFP: plastic quad flat pack Altera Corporation
5 Table. APEX 0K Device Features (.5 V) Device Maximum system gates Logic elements (LEs) Maximum RAM bits Phase-locked loops (PLLs) Speed grade Maximum user I/O pins Package 1-Pin TQFP 1-Pin FineLine BGA 08-Pin PQFP 0-Pin PQFP 3-Pin FineLine BGA 356-Pin BGA 8-Pin FineLine BGA 65-Pin BGA 67-Pin FineLine BGA EP0K100 EP0K00 63,000 56,000,160 8,30 53,8 106, , -, -3-1, -, EP0K00 1,05,000 16,60 1,99 1-1, -, Maximum User I/O Pins Table 5. CAM Applications Address translation Packet header identification Cache tagging Pattern recognition IP filtering Switch address mapping MAC address look-up VPI/VCI translation in ATM switches Embedded System Block Configuration Embedded system blocks are the heart of the MultiCore architecture. The,08 programmable bits of each APEX ESB can be configured as dual-port RAM, ROM, or content-addressable memory (CAM). Embedded Dual-Port RAM APEX ESBs support dual-port RAM with independent read/write ports, synchronous or asynchronous RAM operation, and high-speed first-in first-out (FIFO) performance in a wide range of RAM widths and depths (18 16, 56 8, 51, 1,0, and,08 1). APEX ESBs also support 5-MHz cache RAM performance and ROM performance over 30 MHz. Multiple ESBs can be combined to build wider and deeper memories. High-Performance CAM Within APEX 0KE and APEX 0KC devices, ESBs can be configured as CAM, a parallel processing memory that facilitates fast address search functions. CAM operates like reverse RAM: while RAM receives an address input and supplies data output, CAM receives data input and supplies the address that contains the input data. CAM is commonly used in data communication applications (Table 5). Because the APEX 0KE and APEX 0KC CAM functions as a high-speed parallel comparator, it opens up many new applications for FPGA designs. APEX CAM supports single match, multiple match, fast multiple match, and ternary CAM. Each ESB can be configured as a 3-word 3-bit CAM, and ESBs can be cascaded to build larger CAMs. The integrated CAM in APEX 0KE and APEX 0KC devices offers considerable gains in system performance and configuration flexibility relative to discrete CAM solutions. High-Bandwidth, Low-Voltage I/O Standards The demand for higher system performance and lower supply voltages is growing. APEX 0KE and APEX 0KC devices support multiple I/O interfacing standards, including LVTTL, LVCMOS, GTL+, SSTL-3/, HSTL, AGP, CTT, LVPECL, and LVDS with performance up to 80 Mbps. All APEX devices support the Altera MultiVolt I/O interface, which is ideal for mixed-voltage systems. Enhanced Phase-Locked Loops To increase system-clock rates, APEX 0KE and APEX 0KC devices feature up to four PLLs with enhanced ClockLock, ClockBoost, and ClockShift circuitry. The ClockLock circuitry uses a synchronizing PLL with an extended frequency range that reduces clock delay and skew within the device. The ClockBoost circuitry provides a clock multiplier that allows the designer to distribute a low-speed clock and to multiply that clock on the device. It also allows for resourcesharing within the device and enhances device area efficiency. The ClockShift circuitry provides a programmable clock delay and phase-shift capability. High-Bandwidth True-LVDS Support The APEX 0KE and APEX 0KC I/O interface meets 80-Mbps data transfer rate specifications and has demonstrated data transfer rates up to 1 gigabits per seconds (Gbps) under laboratory conditions (Figure 3, page 6). With dedicated built-in True-LVDS circuitry, the APEX 0KE and APEX 0KC LVDS supports programmable bandwidths up to 6 Gbps. APEX devices offer the highest performance, highest bandwidth SOPC solution for high-speed data transmission designs. Altera Corporation 5
6 Figure 3. APEX 0KE LVDS Running at 1 Gbps Data Transfer Rate* Figure. Aluminum vs. Copper Delays Relative Interconnect Delays µm, Aluminum 0.15-µm, Copper Interconnect Material *Data taken under laboratory conditions. Greater Performance with All-Layer- Copper Interconnect APEX 0KC devices offer improved internal and I/O performance to address the high-density, highperformance needs of communication applications. With internal performance improvements of 5% to 35% and I/O transmission speeds up to 80 Mbps, these devices are ideal for applications such as OC-19 and SONET SDH protocol, as well as WAN and gigabit Ethernet applications. APEX 0KC devices build on the state-of-the-art features offered in the industry-leading APEX 0KE devices. Combined with the revolutionary MultiCore architecture, a wide density range, and advanced FineLine BGA package offering up to four PLLs and multiple user-selectable I/Os standards, the APEX 0KC devices provide even greater system-level integration. In the APEX 0KC devices, copper technology replaces aluminum for routing structure performance enhancements. Copper has low resistivity and better electro-migration characteristics, making it one of the best-known electrical conductors. Interconnect delays are 70% lower than aluminum delays, which translates to significant core performance improvements as shown in Figure. Copper is also more scalable than aluminum, resulting in smaller die size, enhanced internal performance, and speed. The four APEX 0KC devices range in density from 00,000 to 1 million system gates (56,000 to 1.8 million maximum system gates) with embedded memory ranging from 106,69 to 37,680 RAM bits. Three new speed grades (-7, -8, -9) represent the faster performance of these devices. Intellectual Property & Quartus II Design Software Simplify Design The Quartus II design software provides the most comprehensive environment available for SOPC design. This is because the Quartus II software contains a suite of programmable logic design and verification tools including an integrated embedded software development environment and integration to third-party EDA software. The Quartus II software allows designers to implement advanced device features such as CAM, PLL, and LVDS, or to integrate intellectual property (IP) megafunctions easily. Table 6 shows the highlights of the Quartus II design software version.1. 6 Altera Corporation
7 Table 6. Quartus II Software Version.1 Highlights Feature LogicLock Design Methodology Benefit Uses block-based design and optimization capabilities to shorten design and verification cycles and enable team-based design. PowerFit Place-and-Route Timing Closure Flow SignalProbe In-System Verification SignalTap II Embedded Logic Analyzer NativeLink Integration SOPC Builder Integration Improves productivity by intelligently optimizing designs based on user s timing specifications and delivering the fastest compile times in the industry. Includes timing closure floorplan editor to display physical timing estimates between nodes in real time, ability to make powerful path based assignments on critical paths to remove performance bottlenecks easily, netlist optimization features, and incremental, block-based placement. Allows incremental routing of internal nodes to unused or reserved pins for analysis with an external scope or logic analyzer. Enables designers to capture internal signal values in-system and running at system speeds without external probes and without changing user design files. Seamless integration of Quartus II software with third-party EDA synthesis and verification software. Integrates SOPC Builder automated system definition and integration tool. Contact Altera Today The APEX device family provides a new level of capability and offers a platform for SOPC applications. The revolutionary MultiCore architecture brings together the power of FPGA logic and embedded memory for system-level integration. Call Altera today to learn more about this multi-million-gate programmable logic family or visit the Altera web site at Altera Corporation 7
8 The Programmable Solutions Company Altera Offices Altera Corporation Altera European Headquarters Altera Japan Ltd. Altera International Ltd. 101 Innovation Drive Holmers Farm Way Shinjuku i-land Tower 3F 10 Tower 6 San Jose, CA 9513 High Wycombe 5-1, Nishi-Shinjuku, 6-Chome The Gateway, Harbour City USA Buckinghamshire Shinjuku-ku, Tokyo Canton Road Telephone: (08) HP1 XF Japan Tsimshatsui Kowloon United Kingdom Telephone: (81) Hong Kong Telephone: () Telephone: (85) Copyright 00 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. GB-APEX0K-5.0
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