CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING Top 10 Supercomputers in the World as of November 2013*

Transcription

1 CS2214 COMPUTER ARCHITECTURE & ORGANIZATION SPRING 2014 COMPUTERS : PRESENT, PAST & FUTURE Top 10 Supercomputers in the World as of November 2013* No Site Computer Cores Rmax + (TFLOPS) Rpeak (TFLOPS) Power (KWatts) 1 National University of Defense Technology Tianhe-2, NUDT DOE/SC/Oak Ridge National Laboratory Titan, Cray DOE/NNSA/LLNL Sequoia, IBM RIKEN AICS Center K Computer, Fujitsu DOE/SC/Argonne National Laboratory Mira, IBM Swiss National Supercomputing Center Piz Daint, IBM Texas Advanced Computing Center Stampede, Dell Forschungszentrum Juelich JUQEEN, IBM DOE/NNSA/LLNL Vulcan, IBM Leibniz Rechenzentrum, Germany SuperMUC, IBM * From the TOP500 list (of supercomputers in the world) ( + Numbers indicate the performance when Linpack is run on the computers IBM Roadrunner IBM Cell processor with nine cores IBM BlueGene/L The CPU board of the IBM Roadrunner The IBM Roadrunner at LANL IBM computation chip with two PPCs The IBM BlueGene/L at LLNL A portion of the IBM BlueGene/L NYU School of Engineering Page 1 of 10 Handout No : 20 May 5, 2014

2 Sixtieth Birthday of Eniac, 2006 UPenn Library/Exhibitions Eniac which stands for Electronic Numerical Integrator and Computer is considered to be the first electronic computer. It performed 5000 additions or 360 multiplications per second. ENIAC consumed 174 KW and weighted 30 tons with a size of 30 feet x 50 feet as seen in the picture above. Below is an excerpt about the dedication of the ENIAC from Introduction to the ENIAC, Arthur W. Burks and Edward S. Davidson, Proceedings of the IEEE, Vol. 87, NO. 6, June 1999, pp : On February 15, 1946, the vacuum-tube ENIAC was publicly dedicated at the University of Pennsylvania s Moore School of Electrical Engineering. In its demonstration at that time, the digital ENIAC solved the trajectory of an artillery shell in only 25 seconds, whereas the shell itself took 30 seconds to reach its target. This marked the first time that a complicated nonlinear real-time process had been calculated in less than real time. Moreover, the electronic portion of the calculation took up only 5 seconds the other 20 were consumed by the IBM punched-card I/O of data. The Army officers and their scientific advisors to this Army-sponsored project felt that their money (ultimately $ ) was well spent. The ENIAC, operating reliably at pulses per second, was 5000 times as fast as a human computer using a desk calculator and 60 times as fast as the most powerful (electrically driven) mechanical computer, the analog differential analyzer, of which only two were available to the Army. The ENIAC was physically about 20 times as large as the largest radio transmitters, and designing, building, and testing it was a tremendous and revolutionary undertaking. The ENIAC processor circuits have been implemented on a chip with a die size of 7.5 mm x 5.3mm as shown on the right. The die developed at the same school has 174,569 transistors. Picture from : Jan Van der Spiegel University of Pennsylvania, Moore School of Electrical Engineering NYU School of Engineering Page 2 of 10 CS2214 Handout No : 20 May 5, 2014

3 SIAM News November 1986 NYU School of Engineering Page 3 of 10 CS2214 Handout No : 20 May 5, 2014

4 The New York Times Tuesday, March 15, 1988 NYU School of Engineering Page 4 of 10 CS2214 Handout No : 20 May 5, 2014

5 NYU School of Engineering Page 5 of 10 CS2214 Handout No : 20 May 5, 2014

6 IEEE Computer, November 1994 NYU School of Engineering Page 6 of 10 CS2214 Handout No : 20 May 5, 2014

7 IEEE Computer, November 1994 NYU School of Engineering Page 7 of 10 CS2214 Handout No : 20 May 5, 2014

8 Next 8-10 Years Moore s law is expected to hold : Every two years the number of transistors on a chip doubles. Doubling is possible by shrinking the size of transistors. More transistors on the chip means more functionality. Moore s law has improved the speed of microprocessors considerably. In general, the speed of a microprocessor for an application is increased by Reducing the number of operations it performs for the application Better algorithms, high-level language programs, compilers, instruction sets needed Performing more operations in parallel Multiple hardware units (cores) performing multiple operations in parallel are needed Performing each operation faster which means the clock frequency is higher Smaller transistors are needed since they are faster : Moore s law The speed of microprocessors has doubled every two years until 2005 mostly by increasing the clock frequency. But, increasing the clock frequency increases the power consumption hence the heat generated by the chip. In late 2004, it was realized increasing the clock frequency could not continue at its rate unless expensive cooling techniques were used. Designers were forced to switch to the second technique above to increase the microprocessor speed : performing more operations in parallel by using multiple CPUs (cores) : Multi-core computing, i.e. parallel Intel Phi microprocessor 64 cores (2012) processing, has become the main stream. It is expected that the number of cores will double every two years (see figure below). But, shrinking transistor size will lead to a new problem : Alpha and neutron particles from the sky can hit a transistor and change its value, causing soft errors hence program crashes. Another problem is the increasing speed gap between processors and memory chips. Because of Moore s law, the density of memory chips has doubled every two years. But, while the memory speed improves 10% a year, the microprocessor speedis improved more than that, forcing the processor to wait for the slow memory for a long time and severely lowering the computer speed. This problem is called the memory wall problem and is expected to worsen with multi-core chips since there are more processors trying to access the memory. The hardest multi-core problem to solve is developing parallel software that can run on two cores to large numbers of cores efficiently. 40 years of efforts on this problem have not been successful! NYU School of Engineering Page 8 of 10 CS2214 Handout No : 20 May 5, 2014

9 Next 8-10 Years Moore s law and advances in computer architecture and microarchitecture can help reconfigurable computing become main stream. Such a chip has reconfigurable hardware and processor cores. These chips are known as Fiel Programmable Gate Array chips, FPGA chips. One would write a C program for an application. The C program is converted to a code that runs on the cores and to another code to reconfigure the hardware. The memory is distributed across the chip reducing the memory delay. Such a chip offers better speed/cost/flexibility than highspeed multi-core microprocessors for certain applications. Already, there are reconfigurable chips with four processor cores, a reconfigurable area and distributed memory. We expect the number of cores on reconfigurable chips to increase as well. 6.8 Billion transistors Xilinx Virtex T FPGA chip, 28 nm World s 2 nd densest chip The first multi-dimensional chip 2.5-dimensional NVIDIA TESLA KEPLER K20 GPU chip, 28 nm Make sure to handle errors due to Alpha particles, neutrons Defective transistors Make sure to handle Power Wall Memory Wall Parallel programming Wall 7.1 Billion transistors World s densest chip IBM Deep Blue 1997 Electronic with chips 30 cores special chips IBM Watson 2011 Electronic with chips 2880 cores & 0.08 PFLOPS + 16 TB RAM Thinking? A PC in 2020? Electronic with chips Same raw processing power as human brain 20 PFLOPS Peta (10 15 ) - 33 Exa (10 18 ) Bytes NYU School of Engineering Page 9 of 10 CS2214 Handout No : 20 May 5, 2014

10 Longer Term Prospects Semiconductor substances, such as silicon and germanium, will continue to be used for chips in the long run. In addition, transistor sizes will be at the nano scale. However, power consumption, wiring, memory wall, soft errors, hard errors (defects on the chip) and parallel programming will be major problems to solve. New devices may be introduced on to chips, such as carbon nano tubes for wiring and cooling. Other new interconnects besides nano tubes are silicon nano wires, optical connections and plasmonics. New components such as spin-electron, phase change, optical and molecular transistors can be introduced. Sematech, a consortium of semiconductor manufacturers around the world, has a number of predictions for the year 2020 (from its 2008 Update of International Roadmap for Semiconductors, ITRS, study) : On-chip clock speed : 5.3 GHz. The number of transistors on a high-speed microprocessor chip : 35 billion. Largest mass-produced DRAM memory size : 32 Gbits. Process length : 11.9 nm. Eventually, nanotechnology will be present with characteristics that include : Structures with less than 10 nm features. Materials manipulated on an atomic scale. Organic (biological) and inorganic materials. Self-assembly of devices and wires on chips (as opposed to lithograph we have today). DNA self-assembly of components? First nano-level circuits may be hybrid circuits called CMOL combining CMOS and molecular circuits. We might also have the following systems : plastic computers, quantum computers, biologically inspired computational structures. Nano systems will find extensive usage first in medicine and the health sector. A prediction by an artificial intelligence expert at CMU : Hans Moravec, 1998 NYU School of Engineering Page 10 of 10 CS2214 Handout No : 20 May 5, 2014