EE241 - Spring 2000 Advanced Digital Integrated Circuits. Practical Information

Transcription

1 EE24 - Spring 2000 Advanced Digital Integrated Circuits Tu-Th 2:00 3:30pm 203 McLaughlin Practical Information Instructor: Borivoje Nikolic 570 Cory Hall, , bora@eecs.berkeley.edu Office hours: TuTh 3:30-5:00pm TA: TBA Admin: Alev Burton Cory Hall Class Web page

2 Class Organization +/- 5 assignments term-long design project» Phase : Proposal (by week 3)» Phase 2: Study (report by week 7)» Phase 3: Design (presentation and report by final week) Take-home Final Class Material No textbook Must be familiar with Digital Integrated Circuits - A Design Perspective, by J. M. Rabaey Other reference books:» High-Speed CMOS Design Styles, by K. Bernstein, et al.» Digital Systems Engineering by W. Dally» High-Performance System Design: Circuits and Logic, by V.G. Oklobdžija» Low-Power CMOS Design, by Chandrakasan and Brodersen 2

3 Class Material List of background material available on web-site Selected papers will be made available on web-site» Protected area Papers on Class-notes on web-site Sources IEEE Journal of Solid-State Circuits (JSSC) IEEE International Solid-State Circuits Conference (ISSCC) Symposium on VLSI Circuits (VLSI) Other conferences and journals 3

4 Class Topics This course aims to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, optimization, and layout of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing. SPECIAL FOCUS in SPRING 2000:» high-performance low -power logic (as needed for digital radio)» interconnect» timing» arithmetic circuits» memory Class Topics Fundamentals - Technology and modeling - Design Tolerances Limits of scaling ( week) Design for deep-submicron devices - HIGH SPEED (2 weeks)» transistor sizing, buffer design, bootstrapping, reduced swing Design techniques for LOW POWER (2 weeks)» analysis of power consumption sources» power minimization at the technology, circuit, and architecture level Arithmetic circuits adders, multipliers (2 weeks) Impact of interconnect (2 weeks) Timing (2 weeks)» Clock skew, Clocking strategies, Self-timed design, arbiters / phase-locked loops Memory design (2 week) Design of array structures ( week)» FPGAs and reconfigurable logic Design for test ( week) 4

5 Project Topics High-performance low-power logic (radio) Low voltage design Interconnect in deep-submicron Arithmetic circuits High-speed communication Timing of gigascale circuits Reconfigurable logic Reliability of deep-submicron circuits Embedded DRAM and/or flash Other important circuit topics Moore s Law In 965, Gordon Moore noted that the number of transistors on a chip doubled every 8 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 8 months 5

6 Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 9, 965. Transistor Count,000,000 K Billion Transistors 0,000,000,000 0 i386 i486pentium Pentium III Pentium II Pentium Pro 8086 Source: Intel Projected 6

7 Processor Frequency Trend,000 Intel IBM Power PC DEC Gate delays/clock Processor freq scales by 2X per generation 0,000 Mhz S 264A A Pentium(R) 264 II 266 MPC Pentium Pro 60, 603 (R) Pentium(R) ➊ Frequency doubles each generation ➋ Number of gates/clock reduce by 25% Gate Delays/ Clock V.De, S. Borkar ISLPED 99 Technology Scaling Goals of scaling the dimensions by 30%:» Reduce gate delay by 30% (increase operating frequency by 43%)» Double transistor density» Reduce energy per transition by 65% (50% power 43% increase in frequency Technology generation spans 2-3 years, but µp speed doubles every generation (not increased only by 43%) S. Borkar, IEEE Micro, July

8 Total Transistor Width 0 Transistor Size (meters) Total Transistor Pentium Pro Pentium II (R) (R) Pentium MMX Pentium II (R) Pentium (R) (TM) Pentium MMX (TM) Pentium (R) Pentium Pro (R) Pentium II (R) Pentium (R) Pentium MMX(TM) Pentium II (R) Average Transistor Pentium (R) Pentium MMX (TM) Process Technology Generation Source: Intel Transistors scale by ~ 30% per generation Technology Evolution (997 data) National Technology Roadmap for Semiconductors Year of Introduction Channel length [nm] Supply [V] Metal layers Max frequency [MHz],Local Max mp power [W]

9 Technology Roadmap Moore s Law Logic Density A. Masaki, 992. IEEE Circuits & Devices 9

10 Moore s Law - Logic Density 00 Logic Transistors/mm 2 Logic Density 0.5m 386.0m i Pentium Pro (R) Pentium (R) 0.8m 0.6m 0.35m 0.25m 2x trend Pentium II (R) 0.8m 0.3m Source: Intel hrinks and compactions meet density goals ew micro-architectures drop density Interconnect Scaling Trends Interconnect Stack.0m 0.8m 0.6m 0.35m 0.25m M5 ILD4 M4 ILD3 M3 ILD2 M2 ILD M ILD0 Poly Field oxide Gate oxide Minimum Widths (Relative).0m 0.8m 0.6m 0.35m 0.25m M5 M4 M3 M2 M Poly 4.0 Minimum Spacing (Relative) 3.5 Minimum Pitch (Relative) M5 M4 M3 M2 M Poly M5 M4 M3 M2 M Poly 0.0.0m 0.8m 0.6m 0.35m 0.25m 0.0.0m 0.8m 0.6m 0.35m 0.25m

11 Interconnect Distribution Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II Source: Intel No of nets (Log Scale) 0,000,000 0,000 Length (u) Interconnect distribution does not change significantly Processor Power Max Power (Watts) Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX.5m m 0.8m 0.6m 0.35m 0.25m 0.8m 0.3m ➊ Lead processor power increases every generation ➋ Compactions provide higher performance at lower power? Source: Intel

12 If We Sustain Die Size Trend Die size (mils),000,000 Die size grows by 25% to satisfy the trend Pentium Pentium Pro (R) 620(R) A di/dt in AU.E+08.E+07.E+06.E+05.E+04.E+03.E+02.E+0.E+00 Pentium Pro (R) Pentium (R) di/dt noise increases.5m 0.8m 0.35m 0.8m 0.m,000,000 Due to 30% Vdd scaling,000,000 Power (Watts) 0 0-2,000W Pentium Pro (R) Pentium (R) Icc (amps) 0 Pentium Pro (R) Pentium (R) 0-3,000amps Power Density Power density will increase Surpassed hot-plate power density in 0.6m Junction Temp <= 0 C is necessary Performance (higher freq) Exponential growth in leakage Exponential impact on reliability Low cost and more efficient heat spreading techniques are needed Watts/cm

13 Productivity Trends,000,000,000,000,000,000 Complexity Logic Transistor per Chip (M) 0,000 0,000, Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 2%/Yr. compound Productivity growth rate 0,000,000,000,000,000,000 0,000,000, Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Feature Size Pessimistic scenario(very much so) Mainstream scenario Optimistic scenario(?) J. Meindl, Apr Proceedings IEEE 3

14 Chip Dimension 960:.2 mm 980: 6.5-7mm 2000: 25-30mm Driven by economy Packing Efficiency 3D Packing Unused silicon area 4

15 N=D 2 PE/F Integration Density Trends in Power Dissipation 5

16 Energy Chip Performance Index 6