What is this class all about?
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1 -Fall 2004 Digital Integrated Circuits Instructor: Borivoje Nikolić TuTh 3: Cory EECS141 1 What is this class all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Combinational and sequential circuits. Timing and clocking. Arithmetic, interconnect, and memories. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability Practical design using state-of-the-art tools EECS
2 Practical Information Instructor Prof. Borivoje Nikolic 570 Cory Hall, , Office hours: Mo 10:30am-12pm, Th 5:00-6:00pm TAs: Zhengya Zhang, Office hours: W 2-3pm, 353 Cory Bill Tsang, ctsang@eecs Office hours: M 4-5pm, 353 Cory TBA Office hours: TBA Web page: EECS141 3 Discussions and Labs Discussion sessions M 3-4pm, Zhengya Zhang, 293 Cory W 3-4pm, Zhengya Zhang, 293 Cory Same material in both sessions! Labs (353 Cory) M 1-4pm, Bill Tsang W 11am-2pm, TBA F 2-5pm, Bill Tsang Please choose one lab session and stick with it! EECS
3 Your EECS141 Week M OH (Bora) 570 Cory Lab (Bill) 353 Cory DISC* (Zhengya) 293 Cory OH (Bill) 353 Cory T Lec (Bora) 521 Cory TA mtg W Lab (TBA) 353 Cory OH DISC* (Zhengya) (Zhengya) 353 Cory 293 Cory Problem Sets Due R Lec (Bora) 521 Cory OH (Bora) 570 Cory F Lab (Bill) 353 Cory EECS141 * Discussion sections will cover identical material 5 Class Organization 10 Assignments One design project with three phases Labs: 5 software, 1 hardware 2 midterms, 1 final Midterm 1: Thursday, March 2, evening Midterm 2: Thursday, April 6, evening Final: Wednesday, May 19, 12:30-3:30pm EECS
4 Some Important Announcements Please don t bring food/drinks to 353 Cory Please use the newsgroup for asking questions (ucb.class.ee141) Project is done in pairs Homework is done individually Don t even think about cheating! EECS141 7 Grading Policy Homeworks: 10% Labs: 10% Projects: 20% Midterms: 30% Final: 30% EECS
5 Class Material Textbook: Digital Integrated Circuits A Design Perspective, 2 nd ed, by J. Rabaey, A. Chandrakasan, B. Nikolic Class notes: Web page Lab Reader: Available on the web page! Check web page for the availability of tools EECS141 9 The Web Site Class and lecture notes Assignments and solutions Lab and project information Exams Many other goodies The sole source of information Print only what you need: Save a tree! EECS
6 Software Cadence Industry standard Online tutorials We discontinued the use of MicroMagic in this class HSPICE and IRSIM for simulation EECS Getting Started Assignment 1: Getting SPICE to work see web-page Due next Thursday, January 26, 5pm NO discussion sessions or labs this week. First discussion sessions in Week 2 First Software lab in Week 3 EECS
7 Digital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures EECS Introduction Why is designing digital ICs different today than it was before? Will it change in future? EECS
8 The First Computer The Babbage Difference Engine 25,000 parts cost: 17,470 EECS ENIAC - The First Electronic Computer (1946) EECS
9 The Transistor Revolution First transistor Bell Labs, 1948 EECS The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola 1966 EECS
10 Intel 4004 Microprocessor Intel, ,300 transistors (12mm 2 ) 740 KHz operation (10μm PMOS technology) EECS Intel Pentium 4 Microprocessor Intel, ,000,000 transistors (112mm 2 ) 3.8 GHz operation (90nm CMOS technology) EECS
11 Moore s s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months EECS Moore s s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION EECS141 Electronics, April 19,
12 Evolution in Complexity EECS Transistor Counts Transistor Counts in Intel's Microprocessors 1000 Itanium II Transistors [in millions] DX DX Pentium Pro Pentium Pentium II 486DX4 Pentium 4 Pentium MMX Itanium Pentium III Doubles every 2 years EECS141 12
13 Frequency Frequency Trends in Intel's Microprocessors Pentium 4 Frequency [MHz] DX 386DX Pentium II Pentium Pro Pentium 486DX4 Pentium III Pentium MMX Itanium II Itanium Has been doubling every 2 years, but is now slowing down EECS141 Power [W] Power Dissipation Power Trends in Intel's Microprocessors Has been > doubling every 2 years 486DX 386DX Pentium Pro Pentium Itanium Pentium III Pentium II Itanium II Has to stay ~constant Pentium EECS141 13
14 Power is a Major Problem Power (Watts) Pentium proc 18KW 5KW 1.5KW 500W Year Power delivery and dissipation will be prohibitive EECS141 Courtesy, Intel 27 Power Density Power Density (W/cm2) Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp S. Borkar EECS
15 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) M 86M 162M 260M 435M Power Management Analog Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) EECS Productivity Trends 10,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo Source: Sematech Complexity outpaces design productivity EECS141 Courtesy, ITRS Roadmap 30 15
16 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction EECS Challenges in Digital Design DSM Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! EECS
17 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE D n+ EECS This Class Introduces basic metrics for design of integrated circuits how to measure delay, power, etc. Groups layout rectangles into transistors and wires Transistors and wires into gates Gates into functions (Functional blocks into systems) e.g. EECS150 Need to verify that the assumptions are valid EECS
18 Next Lecture Introduces basic metrics for design of integrated circuits how to measure delay, power, cost, etc. Brief intro to IC manufacturing and design EECS
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