Computer Performance. Relative Performance. Ways to measure Performance. Computer Architecture ELEC /1/17. Dr. Hayden Kwok-Hay So

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1 Computer Architecture ELEC344 Computer Performance How do you measure performance of a computer? 2 nd Semester, Dr. Hayden Kwok-Hay So How do you make a computer fast? Department of Electrical and Electronic Engineering 2nd sem. '8-9 ENGG344 - HS 2 Ways to measure Performance Execution Time Time to finish a task Throughput Number of tasks finish per unit time n Execution time (response time) Throughput n We will focus on execution time in this course Relative Performance n Define performance of a computer as Performance = ExecutionTime n Computer B is n times faster than Computer A if: n = Performance B Performance A = ExecutionTime A ExecutionTime B 2nd sem. '8-9 ENGG344 - HS 3 2nd sem. '8-9 ENGG344 - HS 4

2 Quick Check n Computer A finishes a task in 5s, Computer B finishes the same task in 4s. Which one is faster, by how much? Performance B Performance A = ExecutionTime A ExecutionTime B = 5 4 =.25 Computer B is.25 times faster than Computer A 2nd sem. '8-9 ENGG344 - HS 5 Ways to Measure Execution Time n Wall Clock Time (Elapse Time) The total time a user experiences that a computer takes to finish a task Includes OS overhead, I/O, idle time, time shared with other users n CPU Time The time spent on a user task in the CPU User CPU + OS CPU time Does not include I/O, time spent by other users, etc n Focus on CPU Time in this course $ time shasum afile 32ecc0e9eec9d5dc775752efeac280cecebdc afile real user sys 0m20.77s 0m2.835s 0m.786s 2nd sem. '8-9 ENGG344 - HS 6 How can we determine CPU time needed to execute a program? CPUTime = The Iron Law # of instruction program # of cycle instruction time cycle CPU Time Step CPUTime = CycleCount CycleTime = CycleCount ClockFrequency n Most modern CPUs are synchronous digital systems n The time needs to finish executing a task is determined by the number of cycles needed for that ask, multiply by the cycle time. Digital system design review 2nd sem. '8-9 ENGG344 - HS 7 2nd sem. '8-9 ENGG344 - HS 8 2

3 input Synchronous Sequential Circuits n A synchronous sequential circuit contains exactly clock signal n All state elements are connected to the same clock signal è the state of the entire circuit is updated at the same time n Common form of synchronous sequential circuits: Comb Logic Comb Logic Comb Logic Comb Logic output Clock Signal n A clock signal is particularly important signal in a synchronous sequential circuit It controls the action of all DFFs n A clock signal toggles between 0 and periodically n The frequency of the toggling determines the maximum speed of the circuit E.g.: in the accumulator example earlier, the output S cannot change faster than the clock frequency X x0 x x2 S 0 x0 x0 + x x0 + x + x2 clock period = clock frequency clock period e.g. Intel CPU runs at 3 GHz, Mobile phone processors at GHz Lab FPGA board at 50 MHz 2nd sem. '8-9 ENGG344 - HS 9 2nd sem. '8-9 ENGG344 - HS 0 Timing in Synchronous Circuits a b c d n In a synchronous sequential circuit, signal changes occur only during clock edge n All signals are therefore synchronized to change values right after a clock edge n In the above example, need to make sure correct value of y available BEFORE next clock edge Avoid glitches y Timing in Synchronous Circuits n In general, the propagation delay through the combinational logic between any two registers must be shorter than the clock period n The longest such path is called the critical path of the circuit n The critical path determines the maximum clock speed a b x y From glitch example Comb Logic Stable before clock edge 2nd sem. '8-9 ENGG344 - HS 2nd sem. '8-9 ENGG344 - HS 2 3

4 CPU Time Step Summary CPUTime = CycleCount CycleTime = n To improve performance:. Increase clock frequency 2. Reduce cycle count CycleCount ClockFrequency n Increase clock freq è shorter critical path è less work accomplished in cycle è more cycles needed Engineers need tradeoff between the two CPU Time Step 2 Cycle Per Instruction (CPI) CycleCount = InstructionCount CyclePerInstruction n Program A has 2000 instructions, each instruction takes 2 cycles to finish. How many cycles does it take to complete Program A? n Program B has 3000 instructions of them takes 2 cycles and 000 of them takes cycle. How many cycles does the program take to finish? How many cycle does it take to finish a program? 2nd sem. '8-9 ENGG344 - HS 3 2nd sem. '8-9 ENGG344 - HS 4 Average CPI n In general, different machine instructions may take different amount of time to complete. n Assuming n classes of instructions, then total clock cycle: ClockCycle = i= n Weighted average CPI: n CycleCount CPI = InstructionCount = CPI i InstructionCount i n i= CPI i InstructionCount i InstructionCount CPI Example () Class C C2 C3 Cycles 4 8 Compiler J n The ISA of computer A includes 3 classes of instructions that take different number of cycles to complete. A program P is compiled using compiler J, resulting in the utilization above. n What is the average CPI of the compiled program? 2nd sem. '8-9 ENGG344 - HS 5 2nd sem. '8-9 ENGG344 - HS 6 4

5 CPI Example (2) Class C C2 C3 Cycles 4 8 Compiler J Compiler K n A newer compiler K was developed to compile same program P, resulting in the utilization above. n What is the average CPI of the compiled program using compiler K? Ans: 2.3 Which compiler was better? 2nd sem. '8-9 ENGG344 - HS 7 CPI Example (3) Class C C2 C3 #instr #cycle CPI Cycles 4 8 Compiler J Compiler K n Observation: Compiler J results in higher CPI Compiler K uses more instructions n But most importantly: Compiler J uses fewer cycles è shorter run time è better 2nd sem. '8-9 ENGG344 - HS 8 Number of Instructions How many instructions are there in the following code? If CPI =, how many cycles does it take to complete? a = 0 b = a + c = a + b b = c + b # of instr: 4 # of cycles: 4 Number of Instructions How many instructions are there in the following code? If CPI =, how many cycles does it take to complete? i = 0 loop: a = a + i = i + if i < 0 goto loop # of STATIC instructions: 4 # of DYNAMIC instructions: + 3 * 0 = 3 # of cycles: 3 2nd sem. '8-9 ENGG344 - HS 9 2nd sem. '8-9 ENGG344 - HS 20 5

6 Number of Instructions How many instructions are there in the following code? To compute: r = a b r = 0 for (i=b; i>0; i=i-) r = r + a # of DYNAMIC instructions: 3b # of cycles: 3b r = a * b # of instructions: # of cycles: (?) Dynamic # of instructions can be data dependent. Instruction Count & CPI n The number of instructions in a program depends on Nature of application Compiler techniques Type of available instruction of an ISA n Average cycles per instruction depends on CPU microarchitecture ISA (CISC vs RISC) The current running state of CPU n Different instructions may have different CPI Average CPI affected by instruction mix 2nd sem. '8-9 ENGG344 - HS 2 2nd sem. '8-9 ENGG344 - HS 22 Combining All The Iron Law CPUTime = # of instruction program # of cycle instruction time cycle CISC vs RISC n CISC: Complex Instruction Set Computer RISC: Reduced Instruction Set Computer n CISC and RISC are two different computer design strategies: CISC RISC Algorithm Language Compiler ISA Language Compiler ISA Microarchitecture ISA Hardware design VAX x86 PA-RISC Alpha SPARC MIPS ARM RISC-V 2nd sem. '8-9 ENGG344 - HS 23 2nd sem. '8-9 ENGG344 - HS 24 6

7 CISC n ISA includes complex instructions E.g. VAX has a POLY instruction that evaluate polynomial in hardware n Includes complex addressing mode Mem-reg; mem-mem; indirect; relative; double-indirect.. n Hardware implement complex instructions using multiple clock cycles microcode n One promise of CISC ISA is that it allows shorter compiled code and make compiler easier. Still relevant today in embedded systems n Drawback: Less attractive as compiler techniques improve Complex hardware è slow RISC n ISA specifies simple instructions Mostly register-register transfer Simple addressing mode n Simpler hardware design Allows hardware optimization Faster hardware overall Allows easy pipelining n Simple ISA allows compiler optimization n Generated code length is generally longer n Most (if not all) ISA after the 80s are RISC 2nd sem. '8-9 ENGG344 - HS 25 2nd sem. '8-9 ENGG344 - HS 26 RISC vs CISC Iron Law CPUTime = Microarchitecture CPI Cycle Time CISC > short RISC single cycle unpipelined # of instruction program long RISC pipelined short # of cycle instruction time cycle Amdahl s Law Review n Describes the overall speedup of a system due to speed improvement that applies to a portion of the system. n Let P be the portion of the system that can be sped up by a factor of S, 0 P n Amdahl s Law stays that the overall speedup is: ( P)+ P S n E.g.: P = 50%, S=00 è speedup =.98x 2nd sem. '8-9 ENGG344 - HS 27 2nd sem. '8-9 ENGG344 - HS 28 7

8 Amdahl s Law Example n Q: a new implementation of C3 reduces its execution length by half to 4 cycles, how much improvement in performance can be achieved? P = Class C C2 C3 Cycles 4 8 # instr # cycles = 0.4 S = 2 speedup = ( 0.4)+ 0.4 / 2 =.25 2nd sem. '8-9 ENGG344 - HS 29 Amdahl s Law Example n Q2: Which instruction class, when its cycle count is reduced by half, will result in most performance improvement? Largest CPI? Most used? Most cycles used? Class C C2 C3 Cycles 4 8 # instr # cycles nd sem. '8-9 ENGG344 - HS 30 Amdahl s Law Implications n In most applications, only portion of the computation can be sped up improved hardware designs parallelization Can we get to a speedup of 0 with P=0.9? n Amdahl s Law è max speedup is limited by P If only small portion of program can be sped up, then it doesn t matter how large S is 2nd sem. '8-9 ENGG344 - HS 3 Benchmark Programs n A benchmark suite is a set of programs used to compare processor performance n Need to be representative of typical workload n Kernel vs whole application Recall Amdahl s Law n Avoid over optimization for specific benchmark n SPEC benchmark Several benchmark suites commonly used in computer architecture research E.g. SPEC CPU2006 2nd sem. '8-9 ENGG344 - HS 32 8

9 SPEC CPU Benchmark n Programs used to measure performance Supposedly typical of actual workload n Standard Performance Evaluation Corp (SPEC) Develops benchmarks for CPU, I/O, Web, n SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point) CINT2006 for Intel Core i7 920 n n ÕExecution timeratio i i= ENGG344 2nd sem. '8-9 - HS 33 ENGG344 2nd sem. '8-9 - HS 34 Matrix-Matrix Multiplication a 0,0! a 0,N " # " a N,0! a N,N! N = " a i,k b k, j " k=0! b 0,0! b 0,N " # " b N,0! b N,N 2nd sem. '8-9 ENGG344 - HS 35 r[i][j] = 0 for (k=0; k<n; k++) r[i][j] += a[i][k] * b[k][j] Matrix-Matrix Multiplication! n = " a i,k b k, j " k=0! for(i=0; i<n; i++) for(j=0; j<n; j++) r[i][j] = 0 for (k=0; k<n; k++) r[i][j] += a[i][k] * b[k][j] Total number of instructions: N 3 [, +, assignment] n If all instructions have CPI=, then time to complete is ~N 3 cycles. n What are the factors that will make this run faster/slower? 2nd sem. '8-9 ENGG344 - HS 36 9

10 And in conclusion n The study of computer architecture allows us to construct better computer systems Performance, power n Computer architecture is a study that crosses software and hardware n We will use RISC-V as main ISA for class work, but design principles applicable to other computer designs n The Iron Law determines performance of a CPU n ISA, microarchitecture, compilers, and hardware technology all play a role in determining CPU performance Acknowledgements n These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) n MIT material derived from course n UCB material derived from course CS52, CS252 2nd sem. '8-9 ENGG344 - HS 42 2nd sem. '8-9 ENGG344 - HS 43 0