ECE331: Hardware Organization and Design

Transcription

1 ECE331: Hardware Organization and Design Lecture 19: Verilog and Processor Performance Adapted from Computer Organization and Design, Patterson & Hennessy, UCB

2 Verilog Basics Hardware description language Verilog: verification and logic Main language for describing Ics IEEE 1364 C-Like (mostly) Case sensitive Hierarchic Modeling Bottom-up (Essentially) ECE331: Processor Performance 2

3 Verilog Basics - Module Defines a functional module Interface with IC How could it be connected with other ICs module modulename(list of connections); endmodule ECE331: Processor Performance 3

4 Verilog Basics - Connections Defines connections for module module modulename(clk,rst,dout); input clk; input rst; output [7:0] dout; endmodule module modulename( clk, //clock rst, // reset dout //output data ); input clk; input rst; output [7:0] dout; endmodule ECE331: Processor Performance 4

5 Verilog Basics - Wires something which connects two points module modulename( clk, // clock rst, // reset dout // output data ); input clk; input rst; output [7:0] dout; wire clk; wire rst; endmodule ECE331: Processor Performance 5

6 Verilog Basics - Registers Sequential element module modulename(clk,rst,dout); input clk; input rst; output [7:0] dout; wire clk; wire rst; reg [7:0] dout; endmodule ECE331: Processor Performance 6

7 Verilog Basics Constants Syntax: <size> <radix><value> 8-bit Binary 8 b à b à b1010_1010 à bit Hex 8 h AA à h 1F à Can also use decimal ECE331: Processor Performance 7

8 Verilog Basics Behavior Always (posedge clk) begin: <name> //block name //code end (a or b or c) begin: <name> //block name //code end posedge / negedge à rising or falling edges of the clock or à list all inputs that would activate block (*) à combinational circuit Initial (good for simulation) initial begin A < 8 b #5 B < 3 // 5 cycles after end ECE331: Processor Performance 8

9 Verilog Basics Assignments Nonblocking (<) vs Blocking () module block_nonblock(); reg a, b, c, d, e, f ; // Blocking assignments initial begin a #10 1'b1;// assigns 1 to a at time 10 b #20 1'b0;// assigns 0 to b at time 30 c #40 1'b1;// 1 to c at time 70 end // Nonblocking assignments initial begin d < #10 1'b1;// assigns 1 to d at time 10 e < #20 1'b0;// assigns 0 to e at time 20 f < #40 1'b1;// assigns 1 to f at time 40 end endmodule ECE331: Processor Performance 9

10 Verilog Basics Behavior - Decision ECE331: Processor Performance 10

11 Verilog Basics Behavior - Loops ECE331: Processor Performance 11

12 Back to our schedule - Overview Need to define processor performance in a formal way Generally involves cycles per instruction In the best case (for what we ve seen so far), the processor would finish one instruction every cycle Unfortunately, there are problems Hazards Slow memory Other bottlenecks ECE331: Processor Performance 12

13 Understanding Performance Algorithm Determines number of operations executed Programming language, compiler, architecture Determine number of machine instructions executed per operation Processor and memory system Determine how fast instructions are executed I/O system (including OS) Determines how fast I/O operations are executed ECE331: Processor Performance 13

14 Response Time and Throughput Response time How long it takes to do a task Throughput Total work done per unit time e.g., tasks/transactions/ per hour How are response time and throughput affected by Replacing the processor with a faster version? Adding more processors? We ll focus on response time for now ECE331: Processor Performance 14

15 Relative Performance Define Performance 1/Execution Time X is n times faster than Y Performance Performance X Y Execution time Y Execution time X n Example: time taken to run a program 10s on A, 15s on B Execution Time B / Execution Time A 15s / 10s 1.5 So A is 1.5 times faster than B ECE331: Processor Performance 15

16 Measuring Execution Time Elapsed time Total response time, including all aspects Processing, I/O, OS overhead, idle time Determines system performance CPU time Time spent processing a given job Discounts I/O time, other jobs shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance ECE331: Processor Performance 16

17 CPU Clocking Operation of digital hardware governed by a constant-rate clock Clock (cycles) Data transfer and computation Update state Clock period Clock period: duration of a clock cycle e.g., 250ps 0.25ns s Clock frequency (rate): cycles per second e.g., 4.0GHz 4000MHz Hz ECE331: Processor Performance 17

18 CPU Time CPU Time CPU Clock Cycles Clock Cycle Time CPU Clock Cycles Clock Rate Performance improved by Reducing number of clock cycles Increasing clock rate Hardware designer must often trade off clock rate against cycle count ECE331: Processor Performance 18

19 CPU Time Example Computer A: 2GHz clock, 10s CPU time to complete a process Designing Computer B Aim for 6s CPU time to complete the process Can do faster clock, but causes 1.2 clock cycles to complete the same process (e.g. because of architecture causes more stalls in the pipeline) How fast must Computer B clock be? Clock Rate B Clock Cycles CPU Time B B 1.2 Clock Cycles 6s A Clock Cycles A CPU Time A Clock Rate A 10s 2GHz Clock Rate B s s 9 4GHz ECE331: Processor Performance 19

20 Instruction Count and CPI Clock Cycles Instruction Count Cycles per Instruction CPU Time Instruction Count CPI Clock Cycle Time Instruction Count Clock Rate CPI Instruction Count for a program Determined by program, ISA (instruction set architecture) and compiler Average cycles per instruction (CPI) Determined by CPU hardware If different instructions have different CPI Average CPI affected by instruction mix Dimensional analysis: Rate: Units of Hz, or (1/sec) Cycle time: Units of seconds ECE331: Processor Performance 20

21 CPI Example Computer A: Cycle Time 250ps, CPI 2.0 Computer B: Cycle Time 500ps, CPI 1.2 Same ISA Which is faster, and by how much? CPU Time A CPU Time B CPU Time B CPU Time A Instruction Count CPI A I ps I 500ps Instruction Count CPI Cycle Time B B I ps I 600ps I 600ps I 500ps 1.2 Cycle Time A A is faster by this much performance ECE331: Processor Performance 21

22 CPI in More Detail If different instruction classes take different numbers of cycles Clock Cycles n i 1 (CPIi Instruction Count i) Summation is over class types Weighted average CPI CPI Clock Cycles Instruction Count n i 1 CPI i Instruction Count i Instruction Count Relative frequency (fraction) for specific instruction classes compared to the whole ECE331: Processor Performance 22

23 CPI Example Alternative compiled code sequences using instructions in classes A, B, C For example: A unconflicted instruction, B jump instruction, C- beq instruction Class A B C Total IC CPI for class IC in sequence IC in sequence IC à instruction count Sequence 1: IC 5 Clock Cycles Avg. CPI 10/5 2.0 Sequence 2: IC 6 Clock Cycles Avg. CPI 9/6 1.5 ECE331: Processor Performance 23

24 Performance Summary The BIG Picture Instructions Clock cycles CPU Time Program Instruction Seconds Clock cycle The CPU time result is in units of Seconds / Program Performance depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, T c ECE331: Processor Performance 24

25 Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn t account for Differences in ISAs between computers Differences in complexity between instructions MIPS Instruction count Execution time 10 6 Instruction count Instruction count CPI 10 Clock rate 6 Clock rate 6 CPI 10 CPI varies between programs on a given CPU ECE331: Processor Performance 25

26 Summary Important to understand how performance is measured in computers Optimizing just one piece of the computer doesn t always help Identify bottleneck Cycles per instruction can be less that one if parallel processing is used Hazards limit CPI in some cases ECE331: Processor Performance 26