CS305, Computer Architecture, End Sem, Sat 21/11/09, 2:30 05:30pm, Max marks: 45

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1 CS305, Computer Architecture, End Sem, Sat 21/11/09, 2:30 05:30pm, Max marks: 45 Declaration (write by hand and sign): I hereby declare that I hold copying as an act as shameful as stealing, or bribery, or other such acts where one seeks to attain what one does not truly deserve, directly or indirectly denying those adopting honest means. Instructions: Line num. Signature: Write the answers in the space provided; (amount of space indicates length of answer expected). Write neatly and clearly with an ink or ball-point pen (use pencil only for drawings). Your own hand-written notes are allowed. No printed matter or xerox copies are allowed. Some questions have choices, applicable only for students, not for exam-takers. Students should clearly indicate the choice they are attempting, and should not attempt all possible choices. 1. MIPS Coding [3 + 2 = 5 marks] a) Consider the following recursive algorithm for computing x n. fastpow(x, n) = 1 if n=0 x * square(fastpower(x, n/2)) if n is odd square(fastpower(x, n/2)) if n is even Complete the MIPS code below; you must be consistent with the comments/labels given. Label (if any) Code Comments 1 fastpow: # 3 instrns for stack manipln [1 mark] 2 # 3 # 4 # 2 lines: base case in recrsn [0.5 marks] 5 # 6 # 2 instrns for recursive call [0.5 marks] 7 # 8 L1: mul $v0, $v0, $v0 # Use value frm recursive call [0.5 marks] beqz $t0, return # jump past 'odd' case 12 odd: 13 return: # 3 instrns before/for return [0.5 marks] Page 1 of 12

2 b) For the call fastpow(3, 11), draw the stack at the point when it is at its maximum size. Indicate the stack frames for each of the recursive calls at this stage. For each entry in the stack, indicate which register is stored there, and its value (absolute or symbolic, as appropriate). 2. Single-cycle MIPS implementation [5 marks] Choice for students: Answer either a or b, but not both. Indicate a or b clearly. Exam-takers have to answer b (choice a is not available). For either a or b, use the following single-cycle datapath as starting point, which implements MIPS instruction subset: {add, sub, and, or, lw, sw, beq} Page 2 of 12

3 a) Adding support for 'jal'. [ = 5 marks] i. What is the (32-bit) format of the 'jal' instruction? Draw it and explain briefly. ii. Given the above datapath, add support for the 'jal' (jump and link) instruction. Recall that the jal instruction is used for function calls. Indicate only the changes to the above datapath. In your solution, you have to use three 2-to-1 muxes. Also indicate any additional required control line(s). Assume that the control unit outputs an additional control line called 'jal_instr', which indicates whether the current instruction is 'jal'. iii. Complete the following table of control line outputs for the 'jal' instruction. Be sure to follow the mux convention shown in the earlier datapath figure. State any additional assumption as necessary. Ctrl line Value RegDst RegWr PCSrc ALUSrc ALUOp Branch MemRd MemWr Mem2Reg jal_instr b) Adding support for a new instruction 'jm'. [ = 5 marks] We want to add support for a new 'jump memory' instruction. For example: jm 200($s0) will jump to the PC value as given in the memory location whose address is 200+$s0. i. Draw a reasonably designed (32-bit) format of the 'jm' instruction, assuming that it uses the maximum possible number of bits for the offset. Explain briefly. Page 3 of 12

4 ii. Given the original datapath, add support for the 'jm' instruction. Indicate only the changes to the above datapath. In your solution, you have to use two 2-to-1 muxes. Also indicate any additional required control line(s). Assume that the control unit outputs an additional control line called 'jm_instr', which indicates whether the current instruction is 'jm'. iii. Complete the following table of control line outputs for the 'jm' instruction. Be sure to follow the mux convention shown in the earlier datapath figure. State any additional assumption as necessary. Ctrl line Value RegDst RegWr PCSrc ALUSrc ALUO p Branch MemRd MemWr Mem2Reg jm_instr 3. Multicycle MIPS implementation [ = 5 marks] In this question, we want to add support for a new instruction add_mem, whose operands are all in memory: add_mem ($s0), ($s1), ($s2) adds the contents of the locations ($s1) and ($s2) and stores them in ($s0). a) Give a reasonable (32-bit) format for the add_mem instruction. Draw and explain briefly. b) Suggest a reasonable multi-cycle implementation for this instruction, by filling out the following table. Your implementation should use six stages, and should be as close to the original multi-cycle implementation as possible (for simplicity). Stage # Description of operation(s) Page 4 of 12

5 c) In the six-stages, indicate the following (subset of) control lines by filling out the table below. (All of these are control lines from the original datapath). Ctrl line PCWrite IorD (0=I, 1=D) MemRd MemWr IRWrite RegWrite Stg1 val Stg2 val Stg3 val Stg4 val Stg5 val Stg6 val 4. Pipelined MIPS [ = 8 marks] In this question, you are given the following pipelined MIPS datapath to begin with. You are to add support for implementing the 'jal' instruction. Assume that the 'jal' instruction completes in just 2 cycles. Page 5 of 12

6 a) Show only the changes to the pipelined datapath to add support for 'jal'. b) If you have only 1-bit muxes (two inputs, one ctrl input, one output), how many of these units will be needed for the above addition of 'jal' support? How many different control lines are required? c) If in a program, a 'jal' instruction is labeled instruction number 'I', which instructions can have a WAW hazard with the 'jal' instruction? Answer precisely, with a brief explanation. d) Suppose that we want to implement the logic for WAW hazard detection and prevention using stalls. Write the micro-code for this (in the form of pseudocode). Ignore any other hazards. Page 6 of 12

7 e) A more efficient way of avoiding WAW hazards is to ignore the write caused by the earlier instruction in the WAW pair. Now rewrite the above microcode logic for hazard detection and handling, to use such an efficient method. 5. Bus transactions OR Hamming codes [2 + 3 = 5 marks] Choice for students: Answer either a or b, but not both. Indicate a or b clearly. Exam-takers have to answer a (choice b is not available). a) Bus transactions [2 + 3 = 5 marks] i. Consider the CPU writing a word of data to memory. Draw a diagram of the write data transaction on bus, with 'data-request', 'ack', and 'data-ready' control lines. Assume that there is a 32-bit bus-line for data as well as address. Show the various dependancies using arrows clearly. Page 7 of 12

8 ii. Using the same lines as above, draw the diagram for a 2-word read transaction. Show with neat arrows, the various dependencies/steps in the time-line diagram. The memory is inter-leaved, and hence, the address of the second word is assumed to be 1 word greater than the address of the first word requested. b) Hamming codes [2 + 3 = 5 marks] i. Mention one advantage of Hamming codes over 2D parity. Mention one advantage of 2D parity over Hamming codes. ii. Prove that Hamming codes use the minimum required bits for 1-bit error correction. Page 8 of 12

9 6. Paged page tables [Q7.43, 4 marks] Page tables require fairly large amounts of memory, even if most of the entries are invalid. One solution is to use a hierarchy of page tables. The virtual page number, can be broken up into two pieces, a page table number and a page table offset. The page table number can be used to index a first-level page table that provides a physical address for a second-level page table, assuming it resides in memory (if not, a first-level page fault will occur and the page table itself will need to be brought in from disk). The page table offset is used to index into the second-level page table to retrieve the physical page number. One obvious way to arrange such a scheme is to have the second-level page tables occupy exactly one page of memory. Assuming a 32-bit virtual address space with 4 KB pages and 4 bytes per page table entry, how many bytes will each program need to use to store the first-level page table (which must always be in memory)? Draw a figure to show the various bit fields in the virtual address, how they are used to access the first and second level page tables, and how we finally arrive at the physical address. 7. Non-restartable instruction [2 marks] In the context of page-faults, a restartable instruction is one which can be restarted after handling a page-fault which was caused during the instruction's execution. In the MIPS subset we have seen, all instructions are restartable. The Intel IA32 architecture has a single instruction which can perform string copy (strictly speaking, it is memcpy). Prove that this instruction is non-restartable. Hint: think of some special cases in the specification of the origin and destination strings. Page 9 of 12

10 8. Building a cache starting with SRAM chips [Q7.23, 4 marks] You have been given 18 32K x 16-bit SRAMs to build an instruction cache for a processor with a 32-bit address. What is the largest size (i.e., the largest size of the data storage area in bytes) direct-mapped instruction cache that you can build with one-word (64-bit) blocks? Show the breakdown of the address into its cache access components and describe how the various SRAM chips will be used. (Hint: You may not need all of them.) Page 10 of 12

11 9. Short-answer questions [1 x 7 = 7 marks] Students can answer any 7 of the following 14 questions. Be sure to strike out questions which you are not attempting. Exam-takers have to attempt only the first seven questions. a) State two advantages of using tri-state in buses. b) What are the four components of a hard-disk sector read time? c) What are the three central ideas in Computer Science systems? d) A web browser (e.g. firefox) caches the pages the user accesses. This cache is (fill-in this blank w.r.t. associativity) since (state the reason). e) When the hazard detection unit in the ID stage determines the need to stall, it stalls by preventing a write to and to. f) Increasing the number of pipeline stages is good because: Increasing the number of pipeline stages is bad because: g) If 0.25 is the fraction of memory instructions, then Amdahl's law states that the maximum possible speedup due to faster ALU is (give the equation and the answer): Page 11 of 12

12 h) The number of bus-lines for bus arbitration for n devices is (state in O() notation): For daisy chaining: For polling: For independent requesting: i) A cache has k-blocks. If it is then it does not have any misses. j) Stage < (less than) or > (greater than) relationships: Hit-time(L1) Hit-time(L2) Miss-penalty(L1) Miss-penalty(L2) Global-miss-rate(L1) Global-miss-rate(L2) k) The benefit of having the hazard detection unit in the ID stage of the MIPS pipeline is: l) The MIPS ISA has a total of 64 registers (32 int and 32 FP). But the instruction format has only 5 bits for specifying a register. This works because: m) The difference between 'lb' and 'lbu' instructions is: n) Name any two methods to deal with the problem of page tables themselves occupying a lot of memory. Your method should not impose any limits on the number of pages used by a program. Page 12 of 12