EE457. Note: Parts of the solutions are extracted from the solutions manual accompanying the text book.

Transcription

1 EE457 Instructor: G. Puvvada ======================================================================= Homework 5b, Solution ======================================================================= Note: Parts of the solutions are extracted from the solutions manual accompanying the text book. Part I (2nd Edition) addi: No change to datapath is needed. The existing datapath is sufficient. The execution steps for addi would be Instruction fetch (Unchanged) Instruction decode and register fetch (Unchanged) Execution: ALUOut = A + sign-extend ( IR[ 15-0 ] ); Instruction completion: Reg[ IR[ ] ] = ALUOut The first three steps are identical to those performed for memory access instructions, so we can use them (we must add Op = 'addi' to the transition from state 1 to state 2). The fourth step is different and it is not like any existing step; thus we must add a new state to our finite state machine (i.e. state 10). The changed state diagram is on the next page. 1/11

2 Op = addi or 10 Op = addi RegDst = 0 RegWrite = 1 MemtoReg = (3rd Edition) jal: The existing datapath is insufficient. We already have a way to change the PC based on the specified address (using the datapath for jump instruction), but we'll need a new way to put PC+4 into register $ra(31), and this will require changing the datapath. We'll need to expand the two multiplexors controlled by RegDst and MemtoReg. The execution steps would be Instruction fetch (Unchanged) Instruction decode and register fetch (Unchanged) jal: Reg[31] = PC; PC = PC[ ] ( IR[ 25-0 ] << 2 ); Note that in this case we are writing the PC after it has already been incremented by 4 ( in the instruction fetch step) into register $ra ( thus the datapath requires that PC be an input to the MemtoReg multiplexor and 31 needs to be an input to the RegDst multiplexor). We need to modify existing states to show proper values of RegDst and Memtoreg and add a new state that performs the jal instruction ( and then returns to state 0). 2/11

3 The above textbook solution is proposing to change the two 2-to-1 muxes previously controlled by RegDst and MemtoReg to two 3-to muxes to be controlled by new 2-bit control signals RegDst[1:0] and MemtoReg[1:0]. Instead of changing each of these 2-to-1 muxes to a 3-to-1 mux, we felt that it would be easier for students to understand the datapath if we cascaded another 2-to-1 mux (controlled by jal) after the existing 2-to-1 mux. This design is shown on the next page. The corresponding revised state diagram is shown here. (Op = jal ) 10 PCWrite = 1 PCSource=10 RegWrite=1 MemtoReg=X RegDst=X jal =1 jal =0 Note Note jal =0 Note 3/11

4 jal /11

5 5.43. (3rd Edition) wai: There are a variety of implementation options. In state 0 the PC is incremented by 4, so we must subtract 4 from the PC and put this value in a register. This requires two new states (10 and 11). There would be an arrow from state 1 to state 10 labeled Op = 'wai', and there should be unconditional arrows from state 10 to state 11 and from state 11 to state 0. State 10 accomplishes ALUOut = PC - 4 (ALUSrcA = 0, ALUSrcB = 01, and ALUOp = 01) and state 11 accomplishes Reg[IR[20-16]] = ALUout (RegDst = 0, MemtoReg = 0, and RegWrite = 1). An alternative solution relies on the format assumption that '-1' is put in the 16-bit immediate value, and the calculation of the branch address actually computes the PC. This clever solution reduces the number of needed states by 1. First Solution (Op= wai ) 10 ALUSrcA=0 ALUSrcB=01 ALUop = RegDst = 0 MemtoReg=0 regwrite = 1 5/11

6 5.44. (3rd Edition) jm: The existing datapath is insufficient. The jump memory instruction behaves much like a load word until the memory is read. We will add a new input to the multiplexor controlled by PCSource to take the memory contents to the PC. Two methods are covered here. 1. Not so efficient method: The data coming out of memory is deposited first into the MDR in state 3. We need to copy MDR into the PC in a new state coming off of state 3 that checks for Op = "jump memory" (and modify the transition to state 4 to ensure Op = 'lw'). The new state has PCWrite = 1, PCSource = 11. The transitions from (a) state 1 to state 2 and (b) state 2 to state 3 need to also include Op = 'jm'. 2. A more efficient method: Since PC is a stand-alone register and can be written at the end of a clock/state, the new state can be a branch-off from state 2 and can include reading of the memory as well as transferring the contents to the PC directly without having to go through MDR. This save one clock in executing the jm instruction. Method 1 state diagram or (Op = jm ) or (Op = jm ) (Op = jm ) PCwrite =1 \ PCSource=11 (Op = lw ) 6/11

7 Method 1 DPU Method 2 DPU 7/11

8 Method 2 state diagram or (Op = jm ) (Op = jm ) MemRead IorD =1 PCwrite =1 PCSource=11 8/11

9 ee457_homework_5b_sol.fm 10/10/ (3rd Edition) add3: The existing datapath is insufficient. The instruction will require using the ALU twice. A multiplexor should be added to permit the ALU to use the previous result produced by the ALU (stored in ALUOut) as an input for the second addition. Note that changes will also be needed for register read. The instruction can be implemented in 5 cycles by reading the third register source during the cycle in which the first addition is taking place. Clearly a multiplexor and a new control signal will be needed for the inputs to one of the register read ports. Please notice how cleverly the add3 control signal is used in the 6 states below. Note: add3 = X if it is not mentioned in a particular state. add3 = 0 (Op= add3 ) 10 add3 = 1 add3 = 1 add3 = 1 ALUSrcA=1 ALUSrcB=00 ALUop = 00 add3 = 1 11 ALUSrcA=1 ALUSrcB=00 ALUop = 00 add3 = 0 9/11

10 Please note the two new multiplexers under the control of the new control signal add3. ee457_homework_5b_sol.fm 10/10/05 10/11

11 5.45. (3rd Edition) add3: The existing datapath is insufficient. The instruction will require using the ALU twice. A multiplexor should be added to permit the ALU to use the previous result produced by the ALU (stored in ALUOut) as an input for the second addition. Note that changes will also be needed for register read. The instruction can be implemented in 5 cycles by reading the third register source during the cycle in which the first addition is taking place. Clearly a multiplexor and a new control signal will be needed for the inputs to one of the register read ports. Please notice how cleverly the add3 control signal is used in the 5 states below. Note: ADD3 = X if it is not mentioned in a particular state. ADD3 = 1 MUX#1 (Op= add3 ) 10 ALUSrcA=1 ALUSrcB=00 ALUop = 00 ADD3 = X MUX#1 11 ALUSrcA=1 ALUSrcB=00 ALUop = 00 ADD3 = 1 you need (rt) as mem data In state 1, ADD3=1 makes sure that the 5-bit Rs address is conveyed to the register file read address 1input. In states 6, 8, 10, ADD3=0 makes sure that the content of (rt) in the B register is conveyed to the ALU. In state 10, while (rt) is used in the ALU, the same ADD3=0 arranges the 3rd read register ID (Instr [4:0]) to be conveyed to the read address 1 input. In the state 11, ADD3 = 1 causes the previous partial sumto be returned to the B-leg of the ALU while the contents of the 3rd source reg. in the A register are simultaneously conveyed to the A-leg of the ALU. The ADD3 can be X in state 2 as B-leg of the ALU gets sign-extended offset and A-leg gets (rs) from A. In the next clock in state 5, we need (rt) for conveying it as write data for the memory for the sw instruction. ADD3 value interferes in no way with this aspect. 9/11

12 Please note the two new multiplexers under the control of the new control signal ADD3. MUX #2 MUX #1 10/11

13 A better (simpler and cleaner) design Mr. Aaron Black of Fall 2016 EE457 class, says, he understands the corrected solution in the previous pages but he does not like it! He does not like it because he has a simpler and cleaner solution! I agreed with him after going through his solution. I want all students to go through it in the next two pages. Basically the previous solution affects operation in two separate clocks: the clock to fetch the data from a register and the clock to utilize the data. Aaron has avoided this and made it easy to understand and easy to implement it! He deposited the result of the first partial sum (rs + rt) in the B register instead of the ALUOut Register by intercepting the input of register B with a 32-bit mux (Mux #2) under the control of ADD3. So ADD3 is arranging $R3 content in the A register and partial Sum in the B register, both in the same clock!

14 A Simpler and Cleaner Design by Mr. Aaron Black of Fall 2016 EE457 class Mux#1 can be moved to the Rt ID path and Mux#2 can be moved to the Rs content path and the state diagram on the next page does not have to be changed! ADD3 1 Mux#1 1 Mux#2

15 A Simpler and Cleaner Design by Mr. Aaron Black of Fall 2016 EE457 class Except in the three states, 1, 2, and 10, ADD3 can be a don t care in other states. ALUSrcA = 1 ALUSrcB = 00 ALUOp = 00 ADD3 = 1 10 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 00 11

16 ee457_mt_fall2012.fm 2 ( 72 points) 50 min. "add3" instruction in HW#5b and Multicycle CPU design from the 1st and 2nd editions: 2.1 Reproduced below (and on next page) are state diagram and the datapath of the 2nd edition design as modified in HW#5b to support an "add3" instruction. Note: ADD3 = X if it is not mentioned in a particular state. ADD3 = 1 MUX#1 (Op= add3 ) 10 ALUSrcA=1 ALUSrcB=00 ALUop = 00 ADD3 = X MUX#1 11 ALUSrcA=1 ALUSrcB=00 ALUop = 00 ADD3 = 1 you need (rt) as mem data Your junior engineer, Miss Bruin, made a mistake in the datapath layout and made the tapping for the Write data for Memory from the downstream of MUX #2 as shown on the next page. You are the project manager and you need to make one of the following choices. (A) It does not matter if the tapping is upstream or downstream. (B) It matters and there is no fix for this error and hence Miss Bruin has to redo the layout. (C) It matters, but Miss Trojan can fix it in the above state diagram for the control unit. Your choice is:. Explain your choice if it (A) or (B). Carry-out the revision to the state diagram if your choice is (C). November 1, :03 pm EE457 Midterm Exam - Fall 2012 Page - 7 / 13 C Copyright 2012 Gandhi Puvvada

17 ee457_mt_fall2012.fm Our s Miss Bruin s MUX #2 MUX #2 MUX #1 MUX #1 November 1, :10 pm EE457 Midterm Exam - Fall 2012 Page - 8 / 13 C Copyright 2012 Gandhi Puvvada

18 ee457_mt_fall2012.fm Let us go back to our datapath. Someone modified our state diagram for "add3" as shown below and called his instruction "add4_sw" for "add4_storeword". Reverse engineer and find out what does this "add4_sw"actually does. Note: ADD3 = X if it is not mentioned in a particular state. ADD3 = 1 MUX#1 (Op= add4_sw ) 10 ALUSrcA=1 ALUSrcB=00 ALUop = 00 ADD3 = X MUX#1 11 ALUSrcA=1 ALUSrcB=00 ALUop = 00 ADD3 = 1 you need (rt) as mem data MUX#1 ALUSrcA=1 ALUSrcB=01 ALUop = 01 Note! ADD3 = Reproduced on the next two pages are the 1st edition state diagram and the datapath. The datapath was modified partially by a senior EE560 Trojan to support the "add3" instruction. Since there isn t any ALU_out register, he has used the Target register to hold the intermediate sum. He has added the A and B registers at the output of the Register file like in the 2nd edition. Notice that the two new muxes have separate controls: ADD3R to control register ID selection and ADD3A to select the ALU input selection. The datapath modification is complete. You need to complete the state diagram. Write ADD3R and ADD3A values for the 0 to 9 states and also complete states 10, 11, and 12. November 1, :03 pm EE457 Midterm Exam - Fall 2012 Page - 9 / 13 C Copyright 2012 Gandhi Puvvada

19 ee457_mt_fall2012.fm 1st edition state diagram to be modified by you. Fill-in values 0 or 1 or X (prefer X whenever possible). (Op= add3 ) 10 ALUSelA= ALUSelB= ALUop = TargetWrite = 1 11 ALUSelA= ALUSelB= ALUop = 12 ALUSelA= ALUSelB= ALUop = MemtoReg = 0 RegWrite November 1, :03 pm EE457 Midterm Exam - Fall 2012 Page - 10 / 13 C Copyright 2012 Gandhi Puvvada

20 ee457_mt_fall2012.fm Datapath modification to support "add3" is completed already. November 1, :03 pm EE457 Midterm Exam - Fall 2012 Page - 11 / 13 C Copyright 2012 Gandhi Puvvada

21 Part II (3rd Edition) stuck-at-0 fault: If RegDst = 0, all R-format instructions will be unable to write into the proper register (rd). If MemtoReg = 0, load (lw) will not work. If IorD = 0 load (lw) and store (sw) will not work. Further sw will write into (and corrupt) code area. If ALUSrcA = 0, none of the instructions needing rs register will work properly because we are now conveying (PC) in place of (rs) (3rd Edition) stuck-at-1 fault If RegDst = 1, load instructions will not work. If MemtoReg = 1, all R-format instructions will not work. If IorD = 1, no instruction will work because the PC will never be used to get an instruction. If ALUSrcA = 1, the program counter will not be properly incremented by 4 and essentially all instructions will not work. 11/11