Laboratory Exercise 6
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1 Laboratory Exercie 6 Adder, Subtractor, and Multiplier The purpoe of thi exercie i to examine arithmetic circuit that add, ubtract, and multiply number. Each circuit will be decribed in VHL and implemented on an Intel FPGA E1-Lite, E-CV, E1-SoC, or E2-115 board. Part I Conider again the four-bit ripple-carry adder circuit ued in lab exercie 2; it diagram i reproduced in Figure 1. c 3 c 2 c 1 c in carry a) Four-bit ripple-carry adder circuit Figure 1: A four-bit ripple carry adder. A Thi circuit can be implemented uing a ign in VHL. For example, the following code fragment add n-bit number A and B to produce output um and carry: LIBAY ieee; Clock USE ieee.td_logic_1164.all; USE ieee.td_logic_arith.all; USE ieee.td_logic_igned.all;... overflow c in SIGNAL um : ST_LOGIC_VECTO(n-1 OWNTO );... um <= A B; Ue thi contruct to implement a circuit hown in Figure 2. Thi circuit, which i often called an accumulator, i ued to add the value of an input A to itelf repeatedly. The circuit include a carry out from the adder, a well a Overflow S an overflow output ignal. If the input A i conidered a -complement number, then overflow hould be et to 1 in the cae where the output um produced doe not repreent a correct 2 -complement reult. b) Eight-bit regitered adder circuit Perform the following tep: 1. Create a new uartu project. Write VHL code that decribe the circuit in Figure Connect input A to witche SW 7, ue KEY a an active-low aynchronou reet, and ue KEY 1 a a manual clock input. The um from the adder hould be diplayed on the red light LE 7, the regitered carry ignal hould be diplayed on LE, and the regitered overflow ignal hould be diplayed on LE 9. Show the regitered value of A and S a hexadecimal number on the 7-egment diplay HEX3 2 and HEX1. 1
2 c 3 c 2 c 1 c in 3. Make the neceary pin aignment needed to implement the circuit on your E-erie board, and compile carry the circuit. 4. Ue timing imulation to verify the correct operation of the circuit. Once the imulation work properly, download the circuit onto your E-erie board and tet it by uing different value of A. Be ure to check that the overflow output work correctly. a) Four-bit ripple-carry adder circuit A Clock Logic circuit overflow carry S Figure 2: An eight-bit accumulator circuit. Part II Extend the circuit from Part I to be able to both add and ubtract number. To do o, introduce an add_ub input to your circuit. When add_ub i 1, your circuit hould ubtract A from S, and when add_ub i your circuit hould add A to S a in Part I. Part III Figure 3a give an example of paper-and-pencil multiplication P = A B, where A = 11 and B = x x p 7 p 6 p 5 x p 4 p 3 p 2 p 1 p a) ecimal b) Binary c) Implementation Figure 3: Multiplication of binary number. 2
3 We compute P = A B a an addition of ummand. The firt ummand i equal to A time the one digit of B. The econd ummand i A time the ten digit of B, hifted one poition to the left. We add the two ummand to form the product P = 132. Part b of the figure how the ame example uing four-bit binary number. To compute P = A B, we firt form ummand by multiplying A by each digit of B. Since each digit of B i either 1 or, the ummand are either hifted verion of A or. Figure 3c how how each ummand can be formed by uing the Boolean AN operation of A with the appropriate bit of B. A four-bit circuit that implement P = A B i illutrated in Figure 4. Becaue of it regular tructure, thi type of multiplier circuit i called an array multiplier. The haded area correpond to the haded column in Figure 3c. In each row of the multiplier AN gate are ued to produce the ummand, and full adder module are ued to generate the required um. b p 7 p 6 p 5 p 4 p 3 p 2 p 1 p Figure 4: An array multiplier circuit. Perform the following tep to implement the array multiplier circuit: 1. Create a new uartu project. 2. Generate the required VHL file. Ue witche SW 7 4 to repreent the number A and witche SW 3 to repreent B. The hexadecimal value of A and B are to be diplayed on the 7-egment diplay HEX2 and 3
4 HEX, repectively. The reult P = A B i to be diplayed on HEX Make the neceary pin aignment needed to implement the circuit on your E-erie board, and compile the circuit. 4. Ue imulation to verify your deign. 5. ownload your circuit onto your E-erie board and tet it functionality. Part IV In Part III, an array multiplier wa implemented uing full adder module. At a higher level, a row of full adder function a an n-bit adder and the array multiplier circuit can be repreented a hown in Figure 5. c o n-bit Adder c i c o n-bit Adder c i b3 c o n-bit Adder c i p 7 p 6 p 5 p 4 p 3 p 2 p 1 p Figure 5: An array multiplier implemented uing n-bit adder. Each n-bit adder add a hifted verion of A for a given row and the partial product of the row above. Abtracting the multiplier circuit a a equence of addition allow u to build larger multiplier. The multiplier hould conit 4
5 of n-bit adder arranged in a tructure hown in Figure 5. Ue thi approach to implement an x multiplier circuit with regitered input and output, a hown in Figure 6. ata input Clock EA E E EB A B Multiplier 16 Figure 6: A regitered multiplier circuit. P Perform the following tep: 1. Create a new uartu project and write the required VHL file. 2. Ue witche SW 7 to provide the data input to the circuit. Ue SW 9 a the enable ignal EA for regiter A, and ue SW a the enable for regiter B. When SW 9 = 1 diplay the content of regiter A on the red light LE, and diplay the content of regiter B on thee light when SW = 1. Ue KEY a a ynchronou reet input, and ue KEY 1 a a manual clock ignal. Show the product P = A B a a hexadecimal number on the 7-egment diplay HEX Make the neceary pin aignment needed to implement the circuit on your E-erie board, and compile the circuit. 4. Tet the functionality of your deign by inputting variou data value and oberving the generated product. Part V Part IV howed how to implement multiplication A B a a equence of addition, by accumulating the hifted verion of A one row at a time. Another way to implement thi circuit i to perform addition uing an adder tree. An adder tree i a method of adding everal number together in a parallel fahion. Thi idea i illutrated in Figure 7. In the figure, number A, B, C,, E, F, G, and H are added together in parallel. The addition A B happen imultaneouly with C, E F and G H. The reult of thee operation are then added in parallel again, until the final um P i computed. 5
6 A B C E F G H P Figure 7: An example of adding number uing an adder tree. In thi part you are to implement an x multiplier circuit by uing the adder-tree approach. Input A and B, a well a the output P hould be regitered a in Part IV. 6
7 Copyright c Intel Corporation. All right reerved. Intel, The Programmable Solution Company, the tylized Intel logo, pecific device deignation, and all other word and logo that are identified a trademark and/or ervice mark are, unle noted otherwie, the trademark and ervice mark of Intel Corporation in the U.S. and other countrie. All other product or ervice name are the property of their repective holder. Intel product are protected under numerou U.S. and foreign patent and pending application, mak work right, and copyright. Intel warrant performance of it emiconductor product to current pecification in accordance with Intel tandard warranty, but reerve the right to make change to any product and ervice at any time without notice. Intel aume no reponibility or liability ariing out of the application or ue of any information, product, or ervice decribed herein except a exprely agreed to in writing by Intel Corporation. Intel cutomer are advied to obtain the latet verion of device pecification before relying on any publihed information and before placing order for product or ervice. Thi document i being provided on an a-i bai and a an accommodation and therefore all warrantie, repreentation or guarantee of any kind (whether expre, implied or tatutory) including, without limitation, warrantie of merchantability, non-infringement, or fitne for a particular purpoe, are pecifically diclaimed. 7
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