DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 4

Transcription

1 DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 4 Integer DATA TYPE STRUCTURAL DESCRIPTION Hierarchical deign: port-map, for-generate, ifgenerate. Eample: Adder, comparator, multiplier, Look-up Table, Barrel hifter Intructor: Daniel Llamocca

2 INTEGER Data Tpe A ignal of tpe integer repreent a binar number. But we do not pecif the number of bit for the ignal, onl the range of decimal value (thi can be ver convenient). Eample: 7-egment decoder. The BCD input i an integer from 0 to 9, requiring 4 bit (computed b the ntheizer). Drawback: the datatpe integer doe not allow acce to the individual bit (unlike td_logic_vector ) librar ieee; ue ieee.td_logic_1164.all; entit eveneg i port ( bcd: in integer range 0 to 9; -- bcd: 0000 to > 4 bit required eveneg: out td_logic_vector (6 downto 0); EN: in td_logic_vector (3 downto 0)); end eveneg; architecture truct of eveneg i ignal led: td_logic_vector (6 downto 0); begin -- a b c d e f g -- led6 led5 led4 led3 led2 led1 led0 with bcd elect led <= " " when 0, " " when 1, " " when 2, " " when 3, " " when 4, " " when 5, " " when 6, " " when 7, " " when 8, " " when 9; -- Ne3: LED are active low. -- Each 7-eg dipla ha an active-low enable EN <= "0111"; eveneg <= not(led); end truct; Intructor: Daniel Llamocca

3 STRUCTURAL DESCRIPTION It i the generalization of the Concurrent Decription. The circuit are decribed via interconnection of it ubcircuit. Thi ubcircuit can be decribed in concurrent code and/or equential code. Eample: Multipleor 2-to-1. a b 0 1 f b f a Thi cae i trivial, ince the interconnection i realied via logic operator, but neverthele it i an eample of tructural decription. Intructor: Daniel Llamocca

4 STRUCTURAL DESCRIPTION Eample: 4-to-16 decoder We can decribe thi decoder in an tructured wa baed on 2-to-4 decoder. However, we can alo decribe the 4-to-16 decoder uing the withelect tatement. w0 w1 w2 w3 E w0 w1 E w0 w1 E w0 w1 E w0 w1 E w w1 E Intructor: Daniel Llamocca

5 CONTROLLER ALU STRUCTURAL DESCRIPTION Eample: DLX Proceor S1 In thi tpe of tem, it i bet to decribe each component firt, then aemble them to make the large tem. S2 A B REGISTER FILE C X1 We do not need to ee uch large tem to realie the importance of the Structural Decription. X2 TEMP IAR PC IR MAR MDR Intructor: Daniel Llamocca

6 STRUCTURAL DESCRIPTION Man tem can be decribed entirel in one ingle block: we can ue the behavioral decription, and/or concurrent tatement (with-elect, when-ele). However, it i adviable not to abue of thi technique ince it make: i) the code le readable, ii) the circuit verification proce more cumberome, and iii) circuit improvement le evident. The tructural decription allow for a hierarchical deign: we can ee the entire circuit a the piece it i made of, then identif critical point and/or propoe improvement on each piece. It i alwa convenient to have baic building block from which we can build more comple circuit. Thi alo allow building block (or ub-tem) to be re-ued in a different circuit. Intructor: Daniel Llamocca

7 STRUCTURAL DESCRIPTION Eample: 4-bit add/ub for number in 2 complement The circuit can be decribed in one ingle block. However, it i bet to decribe the Full Adder a a block in a eparate file (full_add.vhd), then ue a man full adder to build the 4-bit adder. The place where we ue and connect a man full adder a deired, and poibl add etra circuitr i called the top file (m_addub.vhd). Thi create a hierarch of file in the VHDL project: c i FA c i 0 m_addub.vhd full_add.vhd add/ub add =0 ub = 1 overflow c 4 FA c 3 FA c 2 FA c 1 FA c Intructor: Daniel Llamocca

8 4-bit 2 complement Adder Full Adder: VHDL Decription (fulladd.vhd): librar ieee; ue ieee.td_logic_1164.all; entit fulladd i port ( cin,, : in td_logic;, cout: out td_logic); end fulladd; FA architecture truct of fulladd i begin <= or or cin; cout <= ( and ) or ( and cin) or ( and cin); end truct; Intructor: Daniel Llamocca

9 4-bit 2 complement Adder Top file (m_addub.vhd): We need 4 full adder block and etra logic circuitr. In order to ue the file fulladd.vhd into the top file, we need to declare it in the top file: librar ieee; ue ieee.td_logic_1164.all; entit m_addub i port ( addub: in td_logic;,: in td_logic_vector(3 downto 0); : out td_logic_vector(3 downto 0); cout, overflow: out td_logic); end m_addub; architecture truct of m_addub i component fulladd port ( cin,, : in td_logic;, cout: out td_logic); end component; ignal c: out td_logic_vector(4 downto 0); ignal t: out td_logic_vector(3 downto 0); begin -- continued on net page We cop what i in the entit of full_add.vhd Intructor: Daniel Llamocca

10 4-bit 2 complement Adder Here, we: Inert the required etra circuitr (or gate and I/O connection). Intantiate the full adder and interconnect them (uing the port map tatement) -- continuation from previou page c(0) <= addub; cout <= c(4); overflow <= c(4) or c(3); t(0) <= (0) or addub; t(1) <= (1) or addub; t(2) <= (2) or addub; t(3) <= (3) or addub; f0: fulladd port map(cin=>c(0),=>(0),=>t(0),=>(0),cout=>c(1)); f1: fulladd port map(cin=>c(1),=>(1),=>t(1),=>(1),cout=>c(2)); f2: fulladd port map(cin=>c(2),=>(2),=>t(2),=>(2),cout=>c(3)); f3: fulladd port map(cin=>c(3),=>(3),=>t(3),=>(3),cout=>c(4)); end truct; Intructor: Daniel Llamocca

11 4-bit 2 complement Adder Ue of port map tatement: port map (ignal in full adder => ignal in top file,...) Intantiating and connecting the firt full adder: f0: fulladd port map(cin=>c(0),=>(0),=>t(0),=>(0),cout=>c(1)); add/ub t 3 t 2 t 1 t 0 overf low c 4 c 3 c 2 c 1 c Intructor: Daniel Llamocca

12 4-bit 2 complement Adder Ue of port map tatement: port map (ignal in full adder => ignal in top file,...) Intantiating and connecting the econd full adder: f1: fulladd port map(cin=>c(1),=>(1),=>t(1),=>(1),cout=>c(2)); add/ub t 3 t 2 t 1 t 0 overf low c 4 c 3 c 2 c 1 c Intructor: Daniel Llamocca

13 4-bit 2 complement Adder Ue of port map tatement: port map (ignal in full adder => ignal in top file,...) Intantiating and connecting the third full adder: f2: fulladd port map(cin=>c(2),=>(2),=>t(2),=>(2),cout=>c(3)); add/ub t 3 t 2 t 1 t 0 overf low c 4 c 3 c 2 c 1 c Intructor: Daniel Llamocca

14 4-bit 2 complement Adder Ue of port map tatement: port map (ignal in full adder => ignal in top file,...) Intantiating and connecting the fourth full adder: f3: fulladd port map(cin=>c(3),=>(3),=>t(3),=>(3),cout=>c(4)); add/ub t 3 t 2 t 1 t 0 overf low c 4 c 3 c 2 c 1 c Intructor: Daniel Llamocca

15 STRUCTURAL DESCRIPTION In the 4-bit adder eample, if we wanted to ue a 8 bit, we would need to intantiate 8 full adder and write 8 port map tatement. For-generate: Intantiating component can be a repetitive tak, thu the for-generate tatement i of great help here: t(0) <= (0) or addub; t(1) <= (1) or addub; t(2) <= (2) or addub; t(3) <= (3) or addub; f0: fulladd port map(cin=>c(0),=>(0),=>t(0),=>(0),cout=>c(1)); f1: fulladd port map(cin=>c(1),=>(1),=>t(1),=>(1),cout=>c(2)); f2: fulladd port map(cin=>c(2),=>(2),=>t(2),=>(2),cout=>c(3)); f3: fulladd port map(cin=>c(3),=>(3),=>t(3),=>(3),cout=>c(4)); -- continuation from previou page c(0) <= addub; cout <= c(4); overflow <= c(4) or c(3); gi: for i in 0 to 3 generate t(i) <= (i) or addub; fi: fulladd port map(cin=>c(i),=>(i),=>t(i),=>(i),cout=>c(i+1)); end generate; end truct; Intructor: Daniel Llamocca