VLSI Design 9. Datapath Design

Transcription

1 VLSI Deign 9. Datapath Deign 9. Datapath Deign Lat module: Adder circuit Simple adder Fat addition Thi module omparator Shifter Multi-input Adder Multiplier omparator detector: A = 1 detector: A = Equality comparator: A = Magnitude comparator: A < D. Z. Pan 9. Datapath Deign 1 D. Z. Pan 9. Datapath Deign 2 1 & Detector 1 detector: N-input AND gate detector: NOT 1 detector (N-input NOR) A 7 A 6 A 5 A 4 A A 7 A 6 A 5 A 4 allone A allone allzero Equality omparator heck if each bit i equal (XNOR, or equality gate ) 1 detect on bitwie equality [3] A[3] [2] A[2] [1] A[1] [] A[] A = A D. Z. Pan 9. Datapath Deign 3 D. Z. Pan 9. Datapath Deign 4 Magnitude omparator ompute -A and look at ign -A = ~A 1 For unigned number, carry out i ign bit 3 A N A Signed v. Unigned For igned number, comparion i harder : carry out Z: zero (all bit of A- are ) N: negative (MS of reult) V: overflow (input had different ign, output ign ) 2 1 Z A = A D. Z. Pan 9. Datapath Deign 5 D. Z. Pan 9. Datapath Deign 6 D. Z. Pan 1

2 VLSI Deign 9. Datapath Deign Shifter Logical Shift: Shift number left or right and fill with 111 LSR 1 = LSL1 = 11 Arithmetic Shift: Shift number left or right. Rt hift ign extend 111 ASR1 = ASL1 = 11 arrel Shift (Rotate): Shift number left or right and fill with lot bit 111 ROR1 = ROL1 = 111 Funnel Shifter A funnel hifter can do all ix type of hift Select N-bit field Y from 2N-bit input Shift by k bit ( k < N) 2N-1 N-1 offet N-1 Y offet D. Z. Pan 9. Datapath Deign 7 D. Z. Pan 9. Datapath Deign 8 Funnel Shifter Operation Simplified Funnel Shifter Optimize down to 2N-1 bit input omputing N-k require an adder D. Z. Pan 9. Datapath Deign 9 D. Z. Pan 9. Datapath Deign 1 Funnel Shifter Deign 1 N N-input multiplexer Ue 1-of-N hot elect ignal for hift amount nmos pa tranitor deign (V t drop!) left k[1:] Inverter & Decoder Y 3 Log N tage of 2-input MUXe No elect decoding needed Funnel Shifter Deign 2 left Z Z 1 Z 2 k 1 k Y Y 1 Y 2 Y 2 Z 3 Y 3 Z 6 Y 1 Z 4 Z 5 Y Z 5 Z 4 Z 3 Z 2 Z 1 Z Z 6 D. Z. Pan 9. Datapath Deign 11 D. Z. Pan 9. Datapath Deign 12 D. Z. Pan 2

3 VLSI Deign 9. Datapath Deign Multi-input Adder Suppoe we want to add k N-bit word Ex: = 1111 Straightforward olution: k-1 N-input PA Large and low arry Save Addition Full adder um 3 input, produce 2 output arry output ha twice weight of um output N full adder in parallel: carry ave adder Produce N um and N carry out X 4 Y 4 Z 4 X 3 Y 3 Z 3 X 2 Y 2 Z 2 X 1 Y 1 Z S 4 3 S 3 2 S 2 X N...1 Y N...1 Z N S 1 n-bit SA 1111 N...1 S N...1 D. Z. Pan 9. Datapath Deign 13 D. Z. Pan 9. Datapath Deign 14 SA Application Ue k-2 tage of SA Keep reult in carry-ave redundant form Final PA compute actual reult _ 4-bit SA bit SA 11_ _ 11_ _ 11_ X Y Z S X Y Z S A S D. Z. Pan 9. Datapath Deign 15 Example: Multiplication 11 : : : 6 1 multiplicand multiplier partial product product M x N-bit multiplication Produce N M-bit partial product Sum thee to produce MN-bit product D. Z. Pan 9. Datapath Deign 16 General Form Multiplicand: Y = (y M-1, y M-2,, y 1, y ) Multiplier: X = (x N-1, x N-2,, x 1, x ) Dot Diagram Each dot repreent a bit Product: P = y x = x y M 1 N 1 N 1M 1 j i i j j2 i2 i j2 j= i= i= j= y 5 y 4 y 3 y 2 y 1 y x 5 x 4 x 3 x 2 x 1 x multiplicand multiplier partial product x y 5 x y 4 x y 3 x y 2 x y 1 x y x multiplier x x 1 y 5 x 1 y 4 x 1 y 3 x 1 y 2 x 1 y 1 x 1 y x 2 y 5 x 2 y 4 x 2 y 3 x 2 y 2 x 2 y 1 x 2 y x 3 y 5 x 3 y 4 x 3 y 3 x 3 y 2 x 3 y 1 x 3 y x 4 y 5 x 4 y 4 x 4 y 3 x 4 y 2 x 4 y 1 x 4 y partial product x 15 p 11 x 5 y 5 x 5 y 4 x 5 y 3 x 5 y 2 x 5 y 1 x 5 y p 1 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p product D. Z. Pan 9. Datapath Deign 17 D. Z. Pan 9. Datapath Deign 18 D. Z. Pan 3

4 VLSI Deign 9. Datapath Deign Array Multiplier Rectangular Array x y 3 y 2 y 1 y Squah array to fit rectangular floorplan y 3 y 2 y 1 y x 1 SA Array x x 2 x 1 p x 3 x 2 p 1 PA p 7 p 6 p 5 p 4 p 3 p 2 p 1 p x 3 p 2 Sin A in A critical path A A p 3 out Sin = out in out in = out in p 7 p 6 p 5 p 4 D. Z. Pan 9. Datapath Deign 19 D. Z. Pan 9. Datapath Deign 2 Fewer Partial Product Array multiplier require N partial product If we looked at group of r bit, we could form N/r partial product. Fater and maller? alled radix-2 r encoding Ex: r = 2: look at pair of bit Form partial product of, Y, 2Y, 3Y Firt three are eay, but 3Y require adder ooth Encoding Intead of 3Y, try Y, then increment next partial product to add 4Y Similarly, for 2Y, try 2Y 4Y in next partial product D. Z. Pan 9. Datapath Deign 21 D. Z. Pan 9. Datapath Deign 22 ooth Hardware ooth encoder generate control line for each PP ooth elector chooe PP bit Sign Extenion Partial product can be negative Require ign extenion, which i cumberome High fanout on mot ignificant bit y j y j-1 X i 2X i M i ooth Encoder x 2i-1 x 2i x 2i1 PP PP 1 PP 2 PP 3 PP 4 x -1 x multiplier x PP 5 PP 6 ooth Selector PP ij PP 7 x 15 PP 8 x 16 x 17 D. Z. Pan 9. Datapath Deign 23 D. Z. Pan 9. Datapath Deign 24 D. Z. Pan 4

5 VLSI Deign 9. Datapath Deign Simplified Sign Extenion Sign bit are either all or all 1 Note that all i all 1 1 in proper column Ue thi to reduce loading on MS Even Simpler Sign Extenion No need to add all the 1 in hardware Precompute the anwer! PP PP 1 PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP PP PP 1 PP 2 PP 3 PP 4 PP 5 PP 6 PP 7 PP 8 D. Z. Pan 9. Datapath Deign 25 D. Z. Pan 9. Datapath Deign 26 Advanced Multiplication Signed v. unigned input Higher radix ooth encoding Array v. tree SA network Serial Multiplication D. Z. Pan 9. Datapath Deign 27 Serial Multiplication Lower area at expene of peed ignal proceing on bit tream Delay for n n multiply 2n bit product with 2n bit delay Additional n-bit delay to hift n bit Total delay of 3n bit Pipelined multiplier: poible to produce a new 2n bit product every 2n bit time after initial n bit delay Only interet in high-order bit: n bit delay for n bit product D. Z. Pan 9. Datapath Deign 28 Serial Multiplier Architecture Diviion Area for tructure increae linearly with number of bit, n Pipeline multiplier accumulate partial product um tarting with the leat ignificant partial product (reult i n-bit number which i truncated to n-1 bit before the next partial product) D. Z. Pan 9. Datapath Deign 29 To divide A by Shift P and A one bit left Subtract from P, put the reult back If reult i negative, additional tep, et low order bit of A to, otherwie to 1 retoring or non-retoring diviion to fix negative reult D. Z. Pan 9. Datapath Deign 3 D. Z. Pan 5

6 VLSI Deign 9. Datapath Deign SRT Diviion Divide A by (n-bit)(view number a fraction between ½ and 1) 1. If ha k leading when expreed uing n bit, hift all regiter by k bit 2. For i = to (n-1) 1. If top 3 bit of P equal, et q i =, hift (P,A) one bit left 2. If top 3 bit of P not all equal, and P negative, et q i =-1, (written a, hift (P,A) one bit left and add 3. Otherwie, et q i = 1, hift (P,A) one bit left, ubtract 3. If the final remainder i negative, correct by adding, correct quotient by ubtracting 1; finally, hift remainder k bit right 4. Radix-4 SRT algorithm ued in Pentium chip D. Z. Pan 9. Datapath Deign 31 Floating Point (IEEE ) Special value NaN,, - Round to nearet by default, but three other rounding mode Halfway reult founded to nearet even floating point number Denormal number to repreent reult of computation < 1. 2 Emin Sophiticated facilitie for handling exception D. Z. Pan 9. Datapath Deign 32 Iterative Diviion Newton iteration: finding the of a function tarting from a gue for the, approximate function by it tangent at the gue, form new gue baed on where tangent ha a Goldchmidt method To compute a/b, iteratively, multiply both numerator and denominator by r with r.b = 1 Set x = a, y = b and write b = 1 - δ where δ < 1 If we pick r = 1 δ, then y 1 = r y = 1 - δ 2 Next, pick r 1 = 1 δ 2, etc., and y i 1 Ued in the TI 8847 chip D. Z. Pan 9. Datapath Deign 33 D. Z. Pan 6