Laboratory Exercise 2

Transcription

1 Laoratory Exercie Numer and Diplay Thi i an exercie in deigning cominational circuit that can perform inary-to-decimal numer converion and inary-coded-decimal (BCD) addition. Part I We wih to diplay on the 7-egment diplay HEX and HEX the value et y the witche SW 7. Let the value denoted y SW 7 and SW e diplayed on HEX and HEX, repectively. Your circuit hould e ale to diplay the digit from to 9, and hould treat the valuation to a don t-care.. Create a new project which will e ued to implement the deired circuit on your Altera DE-erie oard. The intent of thi exercie i to manually derive the logic function needed for the 7-egment diplay. Therefore, you hould ue only imple Verilog aign tatement in your code and pecify each logic function a a Boolean expreion.. Write a Verilog file that provide the neceary functionality. Include thi file in your project and aign the pin on the FPGA to connect to the witche and 7-egment diplay. Make ure to include the neceary pin aignment.. Compile the project and download the compiled circuit into the FPGA chip.. Tet the functionality of your deign y toggling the witche and oerving the diplay. Part II You are to deign a circuit that convert a four-it inary numer V = v v v v into it two-digit decimal equivalent D = d d. Tale how the required output value. A partial deign of thi circuit i given in Figure. It include a comparator that check when the value of V i greater than 9, and ue the output of thi comparator in the control of the 7-egment diplay. You are to complete the deign of thi circuit. v v v v d d Tale : Binary-to-decimal converion value. The output z for the comparator circuit can e pecified uing a ingle Boolean expreion, with the four input V. Deign thi Boolean expreion y making a truth tale that how the valuation of the input V for which z ha to e.

2 d Comparator > 9 z 7 6 d V 7 6 Circuit A A Figure : Partial deign of the inary-to-decimal converion circuit. Notice that the circuit in Figure include a -it wide -to- multiplexer (a imilar multiplexer wa decried a part of Laoratory Exercie ). The purpoe of thi multiplexer i to drive digit d with the value of V when z =, and the value of A when z =. To deign circuit A conider the following. For the input value V 9, the circuit A doe not matter, ecaue the multiplexer in Figure jut elect V in thee cae. But for the input value V > 9, the multiplexer will elect A. Thu, A ha to provide output value that properly implement Tale when V > 9. You need to deign circuit A o that the input V = give an output A =, the input V = give the output A =,..., and the input V = give the output A =. Deign circuit A y making a truth tale with the input V and the output A. Perform the following tep:. Write Verilog code to implement your deign. The code hould have the -it input SW, which hould e ued to provide the inary numer V, and the two 7-it output HEX and HEX, to how the value of decimal digit d and d. The intent of thi exercie i to ue imple Verilog aign tatement to pecify the required logic function uing Boolean expreion. Your Verilog code hould not include any if-ele, cae, or imilar tatement.. Make a Quartu II project for your Verilog module.. Compile the circuit and ue functional imulation to verify the correct operation of your comparator, multiplexer, and circuit A.. Download the circuit into an FPGA oard. Tet the circuit y trying all poile value of V and oerving the output diplay. Part III Figure a how a circuit for a full adder, which ha the input a,, and c i, and produce the output and. Part and f the figure how a circuit ymol and truth tale for the full adder, which produce the two-it inary um = a + + c i. Figure d how how four intance of thi full adder module can e ued to deign a circuit that add two four-it numer. Thi type of circuit i uually called a ripple-carry adder, ecaue of

3 the way that the carry ignal are paed from one full adder to the next. Write Verilog code that implement thi circuit, a decried elow. c i a c i a a) Full adder circuit ) Full adder ymol ac i a c a c a c a c in ut c) Full adder truth tale d) Four-it ripple-carry adder circuit Figure : A ripple-carry adder circuit.. Create a new Quartu II project for the adder circuit. Write a Verilog module for the full adder ucircuit and write a top-level Verilog module that intantiate four intance of thi full adder.. Ue witche SW 7 and SW to repreent the input A and B, repectively. Ue SW 8 for the carry-in c in of the adder. Connect the output of the adder, ut and S, to the red light LEDR.. Include the neceary pin aignment for your DE-erie oard, compile the circuit, and download it into the FPGA chip.. Tet your circuit y trying different value for numer A, B, and c in. Part IV In part II we dicued the converion of inary numer into decimal digit. For thi part you are to deign a circuit that ha two decimal digit, X and Y, a input. Each decimal digit i repreented a a -it numer. In technical literature thi i referred to a the inary coded decimal (BCD) repreentation. You are to deign a circuit that add the two BCD digit. The input to your circuit are the numer X and Y, plu a carry-in, c in. When thee input are added, the reult will e a -it inary numer. But thi reult i to e diplayed on 7-egment diplay a a two-digit BCD um S S. For a um equal to zero you would diplay S S =, for a um of one S S =, for nine S S = 9, for ten S S =, and o on. Note that the input X and Y are aumed to e decimal digit, which mean that the larget um that need to e handled y thi circuit i S S = = 9. Perform the tep given elow.. Create a new Quartu II project for your BCD adder. You hould ue the four-it adder circuit from part III to produce a four-it um and carry-out for the operation X + Y.

4 A good way to work out the deign of your circuit i to firt make it handle only um (X + Y ). With thee value, your circuit from Part II can e ued to convert the -it um into the two decimal digit S S. Then, once thi i working, modify your deign to handle value of < (X + Y ) 9. One way to do thi i to till ue your circuit from Part II, ut to modify it output efore attaching them to the 7-egment diplay to make the neceary adjutment when the um from the adder exceed. Write your Verilog code uing imple aign tatement to pecify the required logic function do not ue other type of Verilog tatement uch a if-ele or cae tatement for thi part of the exercie.. Ue witche SW 7 and SW for the input X and Y, repectively, and ue SW 8 for the carry-in. Connect the four-it um and carry-out produced y the operation X + Y to the red light LEDR. Diplay the BCD value of X and Y on the 7-egment diplay HEX and HEX, and diplay the reult S S on HEX and HEX.. Since your circuit handle only BCD digit, check for the cae when the input X or Y i greater than nine. If thi occur, indicate an error y turning on the red light LEDR 9.. Include the neceary pin aignment for your DE-erie oard, compile the circuit, and download it into the FPGA chip.. Tet your circuit y trying different value for numer X, Y, and c in. Part V In part IV you created Verilog code for a BCD adder. A different approach for decriing the adder in Verilog code i to pecify an algorithm like the one repreented y the following peudo-code: T = A + B + c if (T > 9) then Z = ; c = ; ele 6 Z = ; 7 c = ; 8 end if 9 S = T Z S = c It i reaonaly traightforward to ee what circuit could e ued to implement thi peudo-code. Line and 9 repreent adder, line -8 correpond to multiplexer, and teting for the condition T > 9 require comparator. You are to write Verilog code that correpond to thi peudo-code. Note that you can perform addition operation in your Verilog code intead of the utraction hown in line 9. The intent of thi part of the exercie i to examine the effect of relying more on the Verilog compiler to deign the circuit y uing if-ele tatement along with the Verilog > and + operator. Perform the following tep:. Create a new Quartu II project for your Verilog code. Ue witche SW 7 and SW for the input A and B, repectively, and ue SW 8 for the carry-in. The value of A hould e diplayed on the 7-egment diplay HEX, while B hould e on HEX. Diplay the BCD um, S S, on HEX and HEX.. Ue the Quartu II RTL Viewer tool to examine the circuit produced y compiling your Verilog code. Compare the circuit to the one you deigned in Part IV.. Download your circuit onto your DE-erie oard and tet it y trying different value for numer A and B.

5 Part VI Deign a cominational circuit that convert a 6-it inary numer into a -digit decimal numer repreented in the BCD form. Ue witche SW to input the inary numer and 7-egment diplay HEX and HEX to diplay the decimal numer. Implement your circuit on a DE-erie oard and demontrate it functionality. Copyright c Altera Corporation.