Pipeline Implementation. Pipeline Implementation. Pipeline Implementation. Pipeline Implementation. Unpipelined Implementation

Transcription

1 ssume branch target is calculated in E stage Consider only EQZ branches IF stage em[] N + ID stage s[rs] s[rt] sign-ed immediate field of E stage emory reference + ister-register func ister-immediate op ranch N + ( <<2) (==0) 2 E stage For all instructions N emory reference LD em[] em[] ranch If (cond) W stage ister-register /ister-immediate s[rd] s[rt] LD 3 npipelined Implementation IF IF/ID ID ID/E E E/E E E/ W W N N I opcode D LD I D LD opcode 5 6

2 IF stage IF/ID. em[] if((e/e.opcode ==branch) & E/E.cond) then IF/ID.N E/E. else IF/ID.N + ID stage ID/E. s[if/id.[rs]];id/e. s[if/id.[rt]] ID/E.N IF/ID.N; ID/E. IF/ID. ID/E. sign-(if/id.[ediate]) 7 E stage For all instructions E/E. ID/E. emory reference E/E. ID/E. + ID/E. E/E. ID/E. ister-register /ister-immediate E/E. ID/E. func ID/E. or E/E. ID/E. op ID/E. ranch E/E. ID/E.N + (ID/E.<<2) E/E. (ID/E.==0) 8 E stage For all instructions E/W. E/E. instruction E/W. E/E. emory reference E/W.LD em[e/e.] or em[e/e.] E/E. W stage ister-register /ister-immediate s[e/w.[rd]] E/W. or s[e/w.[rt]] E/W. s[e/w.[rt]] E/W.LD 9 0 Pipeline Control IF IF/ID ID ID/E E E/E E E/ W I N ID/E.opcode W E/E. D LD E/W.opcode Handling Hazards There are no structural hazards in our pipeline ll data hazards can be detected (and some solved by forwarding) during ID phase RW(Read after Write) instruction j reads the operand before instruction i writes it WW(Write after Write) instruction j writes the operand before instruction i writes it WR(Write after Read) instruction j writes the operand before instruction i reads it RR(Read after Read) is not a hazard 2 2

3 Hazards No dependence Dependence requiring stall Dependence overcome by forwarding Dependence with accesses in order LD R, 5(R2) DDD R5, R6, R7 DS R8, R6, R7 LD R, 5(R2) DDD R5, R, R7 DS R8, R6, R7 LD R, 5(R2) DDD R5, R6, R7 DS R8, R, R7 LD R, 5(R2) DDD R5, R6, R7 DS R8, R6, R7 OR R9, R, R7 3 Compare IF/ID.[rs] (or IF/ID.[rt]) with ID/E.[rt] Compare IF/ID.[rs] (or IF/ID.[rt]) with E/W.[rt] Hazards that Require Stalls ister-register, store, imm, branch IF/ID.[rs] = = ID/E.[rt] IF/ID.[rt] = = ID/E.[rt] IF/ID.[rt] = = ID/E.[rt] Data Hazards with Forwarding ister-register ister-immediate DDD R, R2, R3 DDD R5, R, R7 DS R8, R6, R7 E/E.[rd/rt] == ID/E.[rs] Top op E/E. ottom op E/E. ister-register DDD R, R2, R3 E/W.[rd /rt] == ID/E.[rs] ister-immediate DDD R5, R3, R7 Top op E/W. DS R8, R, R7 ottom op E/W. LD R, 5(R2) E/W.[rt] == ID/E.[rs] DDD R5, R6, R7 Top op E/W.LD DS R8, R, R7 ottom op E/W.LD Data Hazards with Forwarding IF IF/ID ID ID/E E E/E E W I N LD D LD 5 6 Control Hazards If we only consider EQZ and NEZ (EQ and NE with R0) we can move comparison to the end of ID stage To take advantage of that branch target needs to be computed early We need additional adder Only clock cycle branch penalty followed by a branch on the result will incur stall 7 Control Hazards IF IF/ID ID ID/E E E/E E W I N 8 LD D LD 3

4 Control Hazards IF stage IF/ID. em[] if((if/id.opcode ==branch) & (s[if/id ] op 0)) then IF/ID.N IF/ID.N+ (IF/ID. 6 ) 6 ## IF/ID ##00 else IF/ID.N + 9 Dealing with Exceptions Problem arises when instruction i+k raises an exception, while instruction i is being executed Types of Exceptions: I/O request OS system call Tracing instruction execution rithmetic overflow Page fault emory protection violation etc. 20 Requirements. Synchronous vs. asynchronous 2. ser requested vs. coerced 3. ser maskable vs. nonmaskable. Within vs. between instructions 5. Resume vs. terminate Difficult task is implementing exceptions within instructions that must resume after exception 2 Stopping and Restarting Execution Saving the pipeline state: Force a trap instruction in the pipeline on next IF ntil trap is taken turn off all writes for the faulting instruction and other instructions that follow in the pipeline When trap becomes active it saves of the faulting instruction, it will be used for return. If there are branches in pipeline, we should save s for branch_delay+ instructions. If the pipeline can be stopped so that instructions before faulting instruction are completed, and the others can be restarted it is said to have precise exceptions 22 Exception Handling in IPS Instruction j can cause exception before instruction i does However we must handle exceptions the way we would have handled them without pipelining first i and then j ssociate a status vector with the instruction Turn off all writes if bit in status vector is set When the instruction is in W the status vector is checked and handled 23 Instruction Set Complications Problem arises when an instruction can alter state early in the pipeline: pon exception this state change must be undone Instructions that update memory are forced to work on registers, thus the state of partially completed instructions is in registers and can be saved and restored If instruction set has very long instructions, pipelining is done at microinstruction level SL2 R2, R3 2

5 Extending IPS for FP Pipelining FP operations are long and cannot be completed in 5 cycles (E lasts more than cycle) Simply imagine that E stage is duplicated for FP There are multiple FP functional units Instruction i IF ID E E W FP Instruction i+ IF ID E E E E E W Instruction i+2 IF ID E E W Extending IPS for FP Pipelining E Integer E IF ID FP/Int ult E W E FP dder E FP/Int Div Extending IPS for FP Pipelining It would be beneficial to pipeline E stage for FP We define: Latency number of cycles between the instruction that produces result and instruction that uses the result Initiation interval number of cycles that must elapse before issuing two operations of a given type Functional unit Latency Initiation interval Integer Data memory FP add FP/Int multiply FP/Int divide Extending IPS for FP Pipelining E IF ID E W 2 3 DIV 28 Hazards ecause DIV unit is not pipelined structural hazards can occur ecause instructions have varying running times number of register writes in a cycle can be > Instructions don t reach W in order, so WW hazards are possible Instructions can raise exceptions out of order Stalls for RW hazards will be longer due to long latency 29 RW Hazards L.D IF ID E W DD.D IF ID 2 3 E W L.D IF ID E E W S.D IF ID E E W 30 5

6 WW Hazards Write Port Structural Hazards L.D F,0(R2) L.D F0, F, F6 DD.D F2, F0, F8 S.D F2, 0(R2) IF ID E E W IF ID stall E W IF stall ID stall stallstallstall stall stall 2 3 E W IF stall stall stallstall stall stall ID E stall stall stall E W lthough it seems useless sequence of instructions (STORE overwrites F2 immediately after DD writes it) we must detect WW hazard and make sure the later value appears in register One approach (shown) is to delay issue of later instruction nother approach is to stamp the result of DD and don t write it into memory 3 L.D DD.D L.D IF ID 2 3 IF ID E E W IF ID E E W IF ID 2 3 E W E W IF ID E E W IF ID E E W IF ID E E W Detect write port hazard in ID stage, use shift register that indicates when already issued instructions will use write port, shift reservation register one bit at each clock cycle lternative stall before E or W Detecting and Handling Hazards Since FP and integer operations use different registers we need only consider moves and loads/stores Pipeline checks in ID for: Structural hazards DIV unit and write port RW hazards wait until source registers are not listed as pending destinations WW hazards determine if any instruction in E stage has the same destination register, if so stall the current instruction 33 aintaining Precise Exception Out-of-order completion DIV.D F0, F2, F DD.D F0, F0, F8 S.D F2, F2, F Different approaches to handle this: uffer results of the operation until all previous operations have completed History file keeps track of original values of registers Future file keeps track of new values, registers are updated when all previous instructions have completed Proceed only if sure that no previous instructions 3 will cause exceptions Homework Due Tuesday, October 2 by the end of the class Submit either in class (paper) or by (PS or PDF only) or bring the paper copy to my office Do exercises. (assume branch target and condition are calculated in ID stage),.5,.6 and