M25P Mbit (Multilevel), low-voltage, Serial Flash memory with 50-MHz SPI bus interface Feature summary

Transcription

1 128 Mbit (Multilevel), low-voltage, erial Flash memory with 50-MHz PI bus interface Feature summary 128 Mbit of Flash memory 2.7 to 3.6 V single supply voltage PI bus compatible erial interface 50 MHz clock rate (maximum) V PP = 9 V for fast Program/Erase mode (optional) Page Program (up to 256 Bytes): in 2.5 ms (typical) in 1.2 ms (typical with V PP = 9 V) ector Erase (2 Mbit) Bulk Erase (128 Mbit) Electronic signature JEE standard two-byte signature (2018h) More than Erase/Program cycles per sector More than 20-year data retention Packages EOPAK (RoH compliant) VFPN8 (ME) 8x6mm (MLP8) O16 (MF) 300 mils width ecember 2007 Rev 3 1/45 1

2 ontents ontents 1 ummary description ignal description erial data output (Q) erial data input () erial clock () hip elect () Hold (HOL) Write Protect/Enhanced Program supply voltage (W/V PP ) V supply voltage V ground PI modes Operating features Page programming ector Erase and Bulk Erase Polling during a write, program or erase cycle Fast Program/Erase mode Active power and standby power modes tatus Register Protection modes Hold condition Memory organization Instructions Write Enable (WREN) Write isable (WRI) Read Identification (RI) Read tatus Register (RR) WIP bit /45

3 ontents WEL bit BP2, BP1, BP0 bits RW bit Write tatus Register (WRR) Read ata Bytes (REA) Read ata Bytes at Higher peed (FAT_REA) Page Program (PP) ector Erase (E) Bulk Erase (BE) Power-up and power-down Initial delivery state Maximum rating and A parameters Package mechanical Part numbering Revision history /45

4 List of tables List of tables Table 1. ignal names Table 2. Protected area sizes Table 3. Memory organization Table 4. Instruction set Table 5. Read Identification (RI) data-out sequence Table 6. tatus Register format Table 7. Protection modes Table 8. Power-Up Timing and VWI Threshold Table 9. Absolute maximum ratings Table 10. Operating conditions Table 11. A measurement conditions Table 12. apacitance Table 13. characteristics Table 14. A characteristics Table 15. VFPN8 (MLP8), 8-lead Very thin ual Flat Package No lead, 8 6mm, package mechanical data Table 16. O16 wide 16 lead Plastic mall Outline, 300 mils body width Table 17. Ordering information scheme Table 18. ocument revision history /45

5 List of figures List of figures Figure 1. Logic diagram Figure 2. VFPN connections Figure 3. O connections Figure 4. Bus master and memory devices on the PI bus Figure 5. PI modes supported Figure 6. Hold condition activation Figure 7. Block diagram Figure 8. Write Enable (WREN) instruction sequence Figure 9. Write isable (WRI) instruction sequence Figure 10. Read Identification (RI) instruction sequence and data-out sequence Figure 11. Read tatus Register (RR) instruction sequence and data-out sequence Figure 12. Write tatus Register (WRR) instruction sequence Figure 13. Read ata Bytes (REA) instruction sequence and data-out sequence Figure 14. Read ata Bytes at Higher peed (FAT_REA) instruction and data-out sequence Figure 15. Page Program (PP) instruction sequence Figure 16. ector Erase (E) instruction sequence Figure 17. Bulk Erase (BE) instruction sequence Figure 18. Power-up timing Figure 19. A measurement I/O waveform Figure 20. erial input timing Figure 21. Write Protect setup and hold timing during WRR when RW = Figure 22. Hold timing Figure 23. Output timing Figure 24. V PPH timing Figure 25. VFPN8 (MLP8), 8-lead Very thin ual Flat Package No lead, 8x6mm, package outline. 41 Figure 26. O16 wide 16 lead Plastic mall Outline, 300 mils body width /45

6 ummary description 1 ummary description The is a 128 Mbit (16 Mbit 8), multilevel erial Flash memory, with advanced write protection mechanisms, accessed by a high speed PI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 64 sectors, each containing 1024 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of pages, or bytes. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment. The device enters this mode whenever the V PPH voltage is applied to the Write Protect/Enhanced Program upply Voltage pin (W/V PP ). The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the ector Erase instruction. In order to meet environmental requirements, Numonyx offers these devices in EOPAK packages. EOPAK packages are Lead-free and RoH compliant. Figure 1. Logic diagram V Q W/V PP HOL V AI11313b Table 1. Q W/V PP HOL V V ignal names erial lock erial ata Input erial ata Output hip elect Write Protect/Enhanced Program supply voltage Hold upply Voltage Ground 6/45

7 ummary description Figure 2. VFPN connections Q W/V PP V V HOL AI11314b 1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to V, and must not be allowed to be connected to any other voltage or signal line on the PB. 2. ee Package mechanical section for package dimensions, and how to identify pin-1. Figure 3. O connections HOL V U U U U Q U U U U V W/V PP AI11315b 1. U = on t Use 2. ee Package mechanical section for package dimensions, and how to identify pin-1. 7/45

8 ignal description 2 ignal description 2.1 erial data output (Q) This output signal is used to transfer data serially out of the device. ata is shifted out on the falling edge of erial lock (). 2.2 erial data input () This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of erial lock (). 2.3 erial clock () This input signal provides the timing of the serial interface. Instructions, addresses, or data present at erial ata Input () are latched on the rising edge of erial lock (). ata on erial ata Output (Q) changes after the falling edge of erial lock (). 2.4 hip elect () When this input signal is High, the device is deselected and erial ata Output (Q) is at high impedance. Unless an internal Program, Erase or Write tatus Register cycle is in progress, the device will be in the tandby Power mode. riving hip elect () Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on hip elect () is required prior to the start of any instruction. 2.5 Hold (HOL) The Hold (HOL) signal is used to pause any serial communications with the device without deselecting the device. uring the Hold condition, the erial ata Output (Q) is high impedance, and erial ata Input () and erial lock () are on t are. To start the Hold condition, the device must be selected, with hip elect () driven Low. 8/45

9 ignal description 2.6 Write Protect/Enhanced Program supply voltage (W/V PP ) W/V PP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If the W/V PP input is kept in a low voltage range (0V to V ) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the tatus Register). If V PP is in the range of V PPH it acts as an additional power supply pin. In this case V PP must be stable until the Program/Erase algorithm is completed. 2.7 V supply voltage V is the supply voltage. 2.8 V ground V is the reference for the V supply voltage. 9/45

10 PI modes 3 PI modes These devices can be driven by a microcontroller with its PI peripheral running in either of the two following modes: POL=0, PHA=0 POL=1, PHA=1 For these two modes, input data is latched in on the rising edge of erial lock (), and output data is available from the falling edge of erial lock (). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in tand-by mode and not transferring data: remains at 0 for (POL=0, PHA=0) remains at 1 for (POL=1, PHA=1) Figure 4. Bus master and memory devices on the PI bus V V R (2) PI Interface with (POL, PHA) = (0, 0) or (1, 1) O I K Q V Q V Q V PI bus master V V V R (2) PI memory R (2) PI memory R (2) device device PI memory device W/V PP HOL W/V PP HOL W/V PP HOL AI The Write Protect (W/V PP ) and Hold (HOL) signals should be driven, High or Low as appropriate. 2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the line in the highimpedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (e.g.: when the Bus Master is reset), the clock line () must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, is pulled High while is pulled Low (thus ensuring that and do not become High at the same time, and so, that the t HH requirement is met). 10/45

11 PI modes Figure 5. PI modes supported POL PHA MB Q MB AI01438B 11/45

12 Operating features 4 Operating features 4.1 Page programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t PP ). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see ection 6.8: Page Program (PP) and Table 14: A characteristics). 4.2 ector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the ector Erase (E) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration t E or t BE ). The Erase instruction must be preceded by a Write Enable (WREN) instruction. 4.3 Polling during a write, program or erase cycle A further improvement in the time to Write tatus Register (WRR), Program (PP) or Erase (E or BE) can be achieved by not waiting for the worst case delay (t W, t PP, t E, or t BE ). The Write In Progress (WIP) bit is provided in the tatus Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. 4.4 Fast Program/Erase mode The Fast Program/Erase mode is used to speed up programming/erasing. The device enters the Fast Program/Erase mode during the Page Program, ector Erase or Bulk Erase instruction whenever a voltage equal to V PPH is applied to the W/V PP pin. The use of the Fast Program/Erase mode requires specific operating conditions in addition to the normal ones (V must be within the normal operating range): the voltage applied to the W/V PP pin must be equal to V PPH (see Table 10) ambient temperature, T A must be 25 ±10, the cumulated time during which W/V PP is at V PPH should be less than 80 hours 12/45

13 Operating features 4.5 Active power and standby power modes When hip elect () is Low, the device is selected, and in the Active Power mode. When hip elect () is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write tatus Register). The device then goes in to the tandby Power mode. The device consumption drops to I tatus Register The tatus Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. ee ection 6.4: Read tatus Register (RR) for a detailed description of the tatus Register bits. 4.7 Protection modes The environments where non-volatile memory devices are used can be very noisy. No PI device can operate correctly in the presence of excessive noise. To help combat this, the features the following data protection mechanisms: Power On Reset and an internal timer (t PUW ) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write tatus Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: Power-up Write isable (WRI) instruction completion Write tatus Register (WRR) instruction completion Page Program (PP) instruction completion ector Erase (E) instruction completion Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the oftware Protected Mode (PM). The Write Protect (W/V PP ) signal allows the Block Protect (BP2, BP1, BP0) bits and tatus Register Write isable (RW) bit to be protected. This is the Hardware Protected Mode (HPM). 13/45

14 Operating features Table 2. Protected area sizes tatus Register content Memory content BP2 Bit BP1 Bit BP0 Bit Protected area Unprotected area none All ectors (ectors 0 to 63) (1) Upper 64th (1 ector, 2Mb) ectors 0 to Upper 32nd (2 ectors, 4Mb) ectors 0 to Upper 16nd (4 ectors, 8Mb) ectors 0 to Upper 8nd (8 ectors, 16Mb) ectors 0 to Upper Quarter (16 ectors, 32Mb) Lower 3 Quarters (ectors 0 to 47) Upper Half (32 ectors, 64Mb) Lower Half (ectors 0 to 31) All sectors (64 ectors, 128Mb) none 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are Hold condition The Hold (HOL) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write tatus Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with hip elect () Low. The Hold condition starts on the falling edge of the Hold (HOL) signal, provided that this coincides with erial lock () being Low (as shown in Figure 6). The Hold condition ends on the rising edge of the Hold (HOL) signal, provided that this coincides with erial lock () being Low. If the falling edge does not coincide with erial lock () being Low, the Hold condition starts after erial lock () next goes Low. imilarly, if the rising edge does not coincide with erial lock () being Low, the Hold condition ends after erial lock () next goes Low. (This is shown in Figure 6). uring the Hold condition, the erial ata Output (Q) is high impedance, and erial ata Input () and erial lock () are on t are. Normally, the device is kept selected, with hip elect () driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If hip elect () goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOL) High, and then to drive hip elect () Low. This prevents the device from going back to the Hold condition. 14/45

15 Operating features Figure 6. Hold condition activation HOL Hold ondition (standard use) Hold ondition (non-standard use) AI /45

16 Memory organization 5 Memory organization The memory is organized as: bytes (8 bits each) 64 sectors (2 Mbits, bytes each) pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is ector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Figure 7. Block diagram HOL W/V PP ontrol Logic High Voltage Generator Q I/O hift Register Address Register and ounter 256 Byte ata Buffer tatus Register FFFFFFh Y ecoder ize of the read-only memory area 00000h 256 Bytes (Page ize) X ecoder 000FFh AI11316b 16/45

17 Memory organization Table 3. ector Memory organization Address Range 63 F0000h FFFFFFh 62 F80000h FBFFFFh 61 F40000h F7FFFFh 60 F00000h F3FFFFh 59 E0000h EFFFFFh 58 E80000h EBFFFFh 57 E40000h E7FFFFh 56 E00000h E3FFFFh h FFFFFh h BFFFFh h 7FFFFh h 3FFFFh h FFFFFh h BFFFFh h 7FFFFh h 3FFFFh 47 B0000h BFFFFFh 46 B80000h BBFFFFh 45 B40000h B7FFFFh 44 B00000h B3FFFFh 43 A0000h AFFFFFh 42 A80000h ABFFFFh 41 A40000h A7FFFFh 40 A00000h A3FFFFh h 9FFFFFh h 9BFFFFh h 97FFFFh h 93FFFFh h 8FFFFFh h 8BFFFFh h 87FFFFh h 83FFFFh h 7FFFFFh h 7BFFFFh h 77FFFFh 17/45

18 Memory organization Table 3. ector Memory organization (continued) Address Range h 73FFFFh h 6FFFFFh h 6BFFFFh h 67FFFFh h 63FFFFh h 5FFFFFh h 5BFFFFh h 57FFFFh h 53FFFFh h 4FFFFFh h 4BFFFFh h 47FFFFh h 43FFFFh h 3FFFFFh h 3BFFFFh h 37FFFFh h 33FFFFh h 2FFFFFh h 2BFFFFh h 27FFFFh h 23FFFFh h 1FFFFFh h 1BFFFFh h 17FFFFh h 13FFFFh h 0FFFFFh h 0BFFFFh h 07FFFFh h 03FFFFh 18/45

19 Instructions 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. erial ata Input () is sampled on the first rising edge of erial lock () after hip elect () is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on erial ata Input (), each bit being latched on the rising edges of erial lock (). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. epending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read ata Bytes (REA), Read ata Bytes at Higher peed (Fast_Read), Read tatus Register (RR) or Read Identification (RI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. hip elect () can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), ector Erase (E), Bulk Erase (BE), Write tatus Register (WRR), Write Enable (WREN) or Write isable (WRI), hip elect () must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, hip elect () must driven High when the number of clock pulses after hip elect () being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write tatus Register cycle, Program cycle or Erase cycle are ignored, and the internal Write tatus Register cycle, Program cycle or Erase cycle continues unaffected. Table 4. Instruction set Instruction escription One-byte Instruction ode Address Bytes ummy Bytes ata Bytes WREN Write Enable h WRI Write isable h RI Read Identification Fh to 3 RR Read tatus Register h to WRR Write tatus Register h REA Read ata Bytes h to FAT_REA Read ata Bytes at Higher peed Bh to PP Page Program h to 256 E ector Erase h BE Bulk Erase h /45

20 Instructions 6.1 Write Enable (WREN) The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), ector Erase (E), Bulk Erase (BE) and Write tatus Register (WRR) instruction. The Write Enable (WREN) instruction is entered by driving hip elect () Low, sending the instruction code, and then driving hip elect () High. Figure 8. Write Enable (WREN) instruction sequence Instruction Q High Impedance AI02281E 6.2 Write isable (WRI) The Write isable (WRI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write isable (WRI) instruction is entered by driving hip elect () Low, sending the instruction code, and then driving hip elect () High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write isable (WRI) instruction completion Write tatus Register (WRR) instruction completion Page Program (PP) instruction completion ector Erase (E) instruction completion Bulk Erase (BE) instruction completion Figure 9. Write isable (WRI) instruction sequence Instruction Q High Impedance AI /45

21 Instructions 6.3 Read Identification (RI) The Read Identification (RI) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEE, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (18h). Any Read Identification (RI) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving hip elect () Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on erial ata Output (Q), each bit being shifted out during the falling edge of erial lock (). The instruction sequence is shown in Figure 10. The Read Identification (RI) instruction is terminated by driving hip elect () High at any time during data output. When hip elect () is driven High, the device is put in the tandby Power mode. Once in the tandby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. Read Identification (RI) data-out sequence Manufacturer Identification Memory Type evice Identification Memory apacity 20h 20h 18h Figure 10. Read Identification (RI) instruction sequence and data-out sequence Instruction Q High Impedance Manufacturer Identification evice Identification MB MB AI06809b 21/45

22 Instructions 6.4 Read tatus Register (RR) The Read tatus Register (RR) instruction allows the tatus Register to be read. The tatus Register may be read at any time, even while a Program, Erase or Write tatus Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the tatus Register continuously, as shown in Figure 11. Table 6. b7 tatus Register format RW 0 0 BP2 BP1 BP0 WEL WIP b WIP bit WEL bit The status and control bits of the tatus Register are as follows: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write tatus Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write tatus Register, Program or Erase instruction is accepted BP2, BP1, BP0 bits The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write tatus Register (WRR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Page Program (PP) and ector Erase (E) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are RW bit tatus Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit The tatus Register Write isable (RW) bit is operated in conjunction with the Write Protect (W/V PP ) signal. The tatus Register Write isable (RW) bit and Write Protect (W/V PP ) signal allow the device to be put in the Hardware Protected mode (when the tatus Register Write isable (RW) bit is set to 1, and Write Protect (W/V PP ) is driven Low). In this mode, the non-volatile bits of the tatus Register (RW, BP2, BP1, BP0) become 22/45

23 Instructions read-only bits and the Write tatus Register (WRR) instruction is no longer accepted for execution. Figure 11. Read tatus Register (RR) instruction sequence and data-out sequence Instruction tatus Register Out High Impedance Q MB tatus Register Out MB 7 AI02031E 23/45

24 Instructions 6.5 Write tatus Register (WRR) The Write tatus Register (WRR) instruction allows new values to be written to the tatus Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write tatus Register (WRR) instruction is entered by driving hip elect () Low, followed by the instruction code and the data byte on erial ata Input (). The instruction sequence is shown in Figure 12. The Write tatus Register (WRR) instruction has no effect on b6, b5, b1 and b0 of the tatus Register. b6 and b5 are always read as 0. hip elect () must be driven High after the eighth bit of the data byte has been latched in. If not, the Write tatus Register (WRR) instruction is not executed. As soon as hip elect () is driven High, the self-timed Write tatus Register cycle (whose duration is t W ) is initiated. While the Write tatus Register cycle is in progress, the tatus Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write tatus Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write tatus Register (WRR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The Write tatus Register (WRR) instruction also allows the user to set or reset the tatus Register Write isable (RW) bit in accordance with the Write Protect (W/V PP ) signal. The tatus Register Write isable (RW) bit and Write Protect (W/V PP ) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write tatus Register (WRR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. Table 7. W/V PP ignal RW Bit Protection modes Mode Write Protection of the tatus Register Protected Area (1) Memory ontent Unprotected Area (1) oftware Protected (PM) tatus Register is Writable (if the WREN instruction has set the WEL bit) The values in the RW, BP2, BP1 and BP0 bits can be changed Protected against Page Program, ector Erase and Bulk Erase Ready to accept Page Program and ector Erase instructions 0 1 Hardware Protected (HPM) tatus Register is Hardware write protected The values in the RW, BP2, BP1 and BP0 bits cannot be changed Protected against Page Program, ector Erase and Bulk Erase Ready to accept Page Program and ector Erase instructions 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the tatus Register, as shown in Table 2: Protected area sizes. The protection features of the device are summarized in Table 7 When the tatus Register Write isable (RW) bit of the tatus Register is 0 (its initial delivery state), it is possible to write to the tatus Register provided that the Write Enable 24/45

25 Instructions Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/V PP ) is driven High or Low. When the tatus Register Write isable (RW) bit of the tatus Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W/V PP ): If Write Protect (W/V PP ) is driven High, it is possible to write to the tatus Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W/V PP ) is driven Low, it is not possible to write to the tatus Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the tatus Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (PM) by the Block Protect (BP2, BP1, BP0) bits of the tatus Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the tatus Register Write isable (RW) bit after driving Write Protect (W/V PP ) Low or by driving Write Protect (W/V PP ) Low after setting the tatus Register Write isable (RW) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W/V PP ) High. If Write Protect (W/V PP ) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the oftware Protected Mode (PM), using the Block Protect (BP2, BP1, BP0) bits of the tatus Register, can be used. Figure 12. Write tatus Register (WRR) instruction sequence Instruction tatus Register In Q High Impedance MB AI /45

26 Instructions 6.6 Read ata Bytes (REA) The device is first selected by driving hip elect () Low. The instruction code for the Read ata Bytes (REA) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of erial lock (). Then the memory contents, at that address, is shifted out on erial ata Output (Q), each bit being shifted out, at a maximum frequency f R, during the falling edge of erial lock (). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read ata Bytes (REA) instruction. When the highest address is reached, the address counter rolls over to h, allowing the read sequence to be continued indefinitely. The Read ata Bytes (REA) instruction is terminated by driving hip elect () High. hip elect () can be driven High at any time during data output. Any Read ata Bytes (REA) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read ata Bytes (REA) instruction sequence and data-out sequence Instruction 24-Bit Address Q High Impedance MB ata Out 1 ata Out MB AI /45

27 Instructions 6.7 Read ata Bytes at Higher peed (FAT_REA) The device is first selected by driving hip elect () Low. The instruction code for the Read ata Bytes at Higher peed (FAT_REA) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of erial lock (). Then the memory contents, at that address, is shifted out on erial ata Output (Q), each bit being shifted out, at a maximum frequency f, during the falling edge of erial lock (). The instruction sequence is shown in Figure 14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read ata Bytes at Higher peed (FAT_REA) instruction. When the highest address is reached, the address counter rolls over to h, allowing the read sequence to be continued indefinitely. The Read ata Bytes at Higher peed (FAT_REA) instruction is terminated by driving hip elect () High. hip elect () can be driven High at any time during data output. Any Read ata Bytes at Higher peed (FAT_REA) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Read ata Bytes at Higher peed (FAT_REA) instruction and data-out sequence Instruction 24 BIT ARE Q High Impedance ummy Byte ATA OUT 1 ATA OUT 2 Q MB MB 7 MB AI /45

28 Instructions 6.8 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving hip elect () Low, followed by the instruction code, three address bytes and at least one data byte on erial ata Input (). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). hip elect () must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 ata bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Table 14: A characteristics). hip elect () must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as hip elect () is driven High, the self-timed Page Program cycle (whose duration is t PP ) is initiated. While the Page Program cycle is in progress, the tatus Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed. 28/45

29 Instructions Figure 15. Page Program (PP) instruction sequence Instruction 24-Bit Address ata Byte MB MB ata Byte 2 ata Byte 3 ata Byte MB MB MB AI04082B 29/45

30 Instructions 6.9 ector Erase (E) The ector Erase (E) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The ector Erase (E) instruction is entered by driving hip elect () Low, followed by the instruction code, and three address bytes on erial ata Input (). Any address inside the ector (see Table 3) is a valid address for the ector Erase (E) instruction. hip elect () must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. hip elect () must be driven High after the eighth bit of the last address byte has been latched in, otherwise the ector Erase (E) instruction is not executed. As soon as hip elect () is driven High, the self-timed ector Erase cycle (whose duration is t E ) is initiated. While the ector Erase cycle is in progress, the tatus Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed ector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A ector Erase (E) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed. Figure 16. ector Erase (E) instruction sequence Instruction 24 Bit Address MB AI /45

31 Instructions 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving hip elect () Low, followed by the instruction code on erial ata Input (). hip elect () must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. hip elect () must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as hip elect () is driven High, the self-timed Bulk Erase cycle (whose duration is t BE ) is initiated. While the Bulk Erase cycle is in progress, the tatus Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 17. Bulk Erase (BE) instruction sequence Instruction AI /45

32 Power-up and power-down 7 Power-up and power-down At Power-up and Power-down, the device must not be selected (that is hip elect () must follow the voltage applied on V ) until V reaches the correct value: V (min) at Power-up, and then for a further delay of t VL V at Power-down Usually a simple pull-up resistor on hip elect () can be used to ensure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while V is less than the Power On Reset (POR) threshold voltage, V WI all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), ector Erase (E), Bulk Erase (BE) and Write tatus Register (WRR) instructions until a time delay of t PUW has elapsed after the moment that V rises above the V WI threshold. However, the correct operation of the device is not guaranteed if, by this time, V is still below V (min). No Write tatus Register, Program or Erase instructions should be sent until the later of: t PUW after V passed the V WI threshold t VL after V passed the V (min) level These values are specified in Table 8. If the delay, t VL, has elapsed, after V has risen above V (min), the device can be selected for REA instructions even if the t PUW delay is not yet fully elapsed. At Power-up, the device is in the following state: The device is in the tandby Power mode The Write Enable Latch (WEL) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the V supply. Each device in a system should have the V rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1µF). At Power-down, when V drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, V WI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.) Power up sequencing for Fast program/erase mode: V should attain V MIN before V PPH is applied. 32/45

33 Initial delivery state Figure 18. Power-up timing V V (max) Program, Erase and Write ommands are Rejected by the evice hip election Not Allowed V (min) Reset tate of the evice tvl Read Access allowed evice fully accessible V WI tpuw time AI04009 Table 8. Power-Up Timing and V WI Threshold ymbol Parameter Min. Max. Unit t VL (1) t PUW (1) V (min) to Low 60 µs Time delay to Write instruction 1 10 ms V WI Write Inhibit Voltage V 1. These parameters are characterized only. 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The tatus Register contains 00h (all tatus Register bits are 0). 33/45

34 Maximum rating 9 Maximum rating tressing the device outside the ratings listed in Table 9 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx URE Program and other relevant quality documents. Table 9. Absolute maximum ratings ymbol Parameter Min. Max. Unit T TG torage Temperature V IO Input and output voltage (with respect to Ground) 0.5 V V V upply voltage V V PP Fast Program/Erase voltage V V E Electrostatic ischarge Voltage (Human Body Model) (1) 1. JEE td JE22-A114A (1=100 pf, R1=1500 Ω, R2=500 Ω) V 34/45

35 and A parameters 10 and A parameters This section summarizes the operating and measurement conditions, and the and A characteristics of the device. The parameters in the and A haracteristic tables that follow are derived from tests performed under the Measurement onditions summarized in the relevant tables. esigners should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10. Operating conditions ymbol Parameter Min. Typ. Max. Unit V upply Voltage V V PPH upply Voltage on W/V PP pin for Fast Program/Erase mode 1. Output Hi-Z is defined as the point where data out is no longer driven V T A Ambient Operating Temperature T AVPP Table 11. Ambient Operating Temperature for Fast Program/Erase mode A measurement conditions ymbol Parameter Min. Max. Unit L Load apacitance 30 pf Input Rise and Fall Times 5 ns Input Pulse Voltages 0.2V to 0.8V V Input Timing Reference Voltages 0.3V to 0.7V V Output Timing Reference Voltages V / 2 V Figure 19. A measurement I/O waveform Input Levels 0.8V 0.2V Input and Output Timing Reference Levels 0.7V 0.5V 0.3V AI07455 Table 12. apacitance ymbol Parameter Test ondition Min. Max. Unit OUT Output apacitance (Q) V OUT = 0V 8 pf IN Input apacitance (other pins) V IN = 0V 6 pf 1. ampled only, not 100% tested, at T A =25 and a frequency of 20 MHz. 35/45

36 and A parameters Table 13. characteristics ymbol Parameter Test ondition (in addition to those in Table 10) Min. Max. Unit I LI Input Leakage urrent ± 2 µa I LO Output Leakage urrent ± 2 µa I 1 tandby urrent = V, V IN = V or V 100 µa I 3 Operating urrent (REA) = 0.1V / 0.9.V at 50MHz, Q = open = 0.1V / 0.9.V at 20MHz, Q = open 8 ma 4 ma I 4 Operating urrent (PP) = V 20 ma I 5 Operating urrent (WRR) = V 20 ma I 6 Operating urrent (E) = V 20 ma I 7 Operating urrent (BE) = V 20 ma I PP (1) I PP (1) Operating current for Fast Program/Erase mode V PP Operating current in Fast Program/Erase mode 1. haracterized only. = V, V PP = V PPH 20 ma = V, V PP = V PPH 20 ma V IL Input Low Voltage V V V IH Input High Voltage 0.7V V +0.2 V V OL Output Low Voltage I OL = 1.6mA 0.4 V V OH Output High Voltage IOH = 100μA V 0.2 V 36/45

37 and A parameters Table 14. A characteristics Test conditions specified in Table 10 and Table 11 ymbol Alt. Parameter Min. Typ. Max. Unit f f FAT_REA, PP, E, BE, WREN, WRI, lock Frequency for the following instructions: RI, RR, WRR.. 50 MHz f R lock Frequency for REA instructions.. 20 MHz t H (1) t L (1) t LH lock High Time 9 ns t LL lock Low Time 9 ns t LH (2) lock Rise Time (3) (peak to peak) 0.1 V/ns t HL (2) lock Fall Time (3) (peak to peak) 0.1 V/ns t LH t Active etup Time (relative to ) 5 ns t HL Not Active Hold Time (relative to ) 5 ns t VH t U ata In etup Time 2 ns t HX t H ata In Hold Time 5 ns t HH Active Hold Time (relative to ) 5 ns t HH Not Active etup Time (relative to ) 5 ns t HL t H eselect Time 100 ns t HQZ (2) t I Output isable Time 8 ns t LQV t V lock Low to Output Valid 8 ns t LQX t HO Output Hold Time 0 ns t HLH HOL etup Time (relative to ) 5 ns t HHH HOL Hold Time (relative to ) 5 ns t HHH HOL etup Time (relative to ) 5 ns t HHL HOL Hold Time (relative to ) 5 ns (2) t HHQX t LZ HOL to Output Low-Z 8 ns t HLQZ (2) t HZ HOL to Output High-Z 8 ns t WHL (4) t HWL (4) t VPPHL (2)(5) Write Protect etup Time 20 ns Write Protect Hold Time 100 ns Enhanced Program upply Voltage High to hip elect Low 200 ns t W Write tatus Register ycle Time 5 15 ms t PP (6) Page Program ycle Time (256 Bytes) 2.5 Page Program ycle Time (n Bytes) 2.5 Page Program ycle Time (V PP = V PPH ) (256 Bytes) 1.2 (2) t E ector Erase ycle Time (V PP = V PPH ) 1.6 (2) ector Erase ycle Time 2 7 ms 6 s 37/45