M25P80 8 Mbit, Low Voltage, Serial Flash Memory With 40MHz SPI Bus Interface

Transcription

1 8 Mbit, Low Voltage, erial Flash Memory With 40MHz PI Bus Interface FEATURE UMMARY 8 Mbit of Flash Memory Page Program (up to 256 Bytes) in 1.4ms (typical) ector Erase (512 Kbit) in 1s (typical) Bulk Erase (8 Mbit) in 10s (typical) 2.7 to 3.6V ingle upply Voltage PI Bus ompatible erial Interface 40MHz lock Rate (maximum) eep Power-down Mode 1µA (typical) Electronic ignature (13h) Packages EOPAK (RoH compliant) Figure 1. Packages VFQFPN8 (MP) (MLP8) 8 1 O8 (MW) 200 mil width October /41

2 TABLE OF ONTENT FEATURE UMMARY UMMARY ERIPTION IGNAL ERIPTION erial ata Output (Q) erial ata Input () erial lock () hip elect () Hold (HOL) Write Protect (W) PI MOE OPERATING FEATURE Page Programming ector Erase and Bulk Erase Polling uring a Write, Program or Erase ycle Active Power, tand-by Power and eep Power-own Modes tatus Register WIP bit WEL bit BP2, BP1, BP0 bits RW bit Protection Modes Hold ondition MEMORY ORGANIZATION INTRUTION Write Enable (WREN) Write isable (WRI) Read tatus Register (RR) WIP bit WEL bit BP2, BP1, BP0 bits RW bit Write tatus Register (WRR) Read ata Bytes (REA) Read ata Bytes at Higher peed (FAT_REA) Page Program (PP) ector Erase (E) Bulk Erase (BE) eep Power-down (P) /41

3 Release from eep Power-down and Read Electronic ignature (RE) POWER-UP AN POWER-OWN INITIAL ELIVERY TATE MAXIMUM RATING AN A PARAMETER PAKAGE MEHANIAL PART NUMBERING REVIION HITORY /41

4 UMMARY ERIPTION The M25P80 is a 8 Mbit (1M x 8) erial Flash Memory, with advanced write protection mechanisms, accessed by a high speed PI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1,048,576 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the ector Erase instruction. In order to meet environmental requirements, T offers these devices in EOPAK packages. EOPAK packages are Lead-free and RoH compliant. EOPAK is an T trademark. EOPAK specifications are available at: Table 1. ignal Names erial lock erial ata Input Q erial ata Output hip elect W Write Protect HOL Hold V upply Voltage V Ground Figure 3. VFQFPN and O8 onnections Figure 2. Logic iagram V M25P80 M25P80 Q Q W V AI04965B 5 V HOL W HOL V AI04964 Note: 1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to V, and must not be allowed to be connected to any other voltage or signal line on the PB. 2. ee PAKAGE MEHANIAL section for package dimensions, and how to identify pin-1. 4/41

5 IGNAL ERIPTION erial ata Output (Q). This output signal is used to transfer data serially out of the device. ata is shifted out on the falling edge of erial lock (). erial ata Input (). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of erial lock (). erial lock (). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at erial ata Input () are latched on the rising edge of erial lock (). ata on erial ata Output (Q) changes after the falling edge of erial lock (). hip elect (). When this input signal is High, the device is deselected and erial ata Output (Q) is at high impedance. Unless an internal Program, Erase or Write tatus Register cycle is in progress, the device will be in the tandby mode (this is not the eep Power-down mode). riving hip elect () Low enables the device, placing it in the active power mode. After Power-up, a falling edge on hip elect () is required prior to the start of any instruction. Hold (HOL). The Hold (HOL) signal is used to pause any serial communications with the device without deselecting the device. uring the Hold condition, the erial ata Output (Q) is high impedance, and erial ata Input () and erial lock () are on t are. To start the Hold condition, the device must be selected, with hip elect () driven Low. Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the tatus Register). 5/41

6 PI MOE These devices can be driven by a microcontroller with its PI peripheral running in either of the two following modes: POL=0, PHA=0 POL=1, PHA=1 For these two modes, input data is latched in on the rising edge of erial lock (), and output data is available from the falling edge of erial lock (). The difference between the two modes, as shown in Figure 5., is the clock polarity when the bus master is in tand-by mode and not transferring data: remains at 0 for (POL=0, PHA=0) remains at 1 for (POL=1, PHA=1) Figure 4. Bus Master and Memory evices on the PI Bus PI Interface with (POL, PHA) = (0, 0) or (1, 1) O I K Bus Master (T6, T7, T9, T10, Others) Q PI Memory evice Q PI Memory evice Q PI Memory evice W HOL W HOL W HOL AI03746 Note: The Write Protect (W) and Hold (HOL) signals should be driven, High or Low as appropriate. Figure 5. PI Modes upported POL PHA MB Q MB AI01438B 6/41

7 OPERATING FEATURE Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t PP ). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Page Program (PP), Instruction Times (evice Grade 6) and Instruction Times (evice Grade 3)). ector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the ector Erase (E) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration t E or t BE ). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling uring a Write, Program or Erase ycle A further improvement in the time to Write tatus Register (WRR), Program (PP) or Erase (E or BE) can be achieved by not waiting for the worst case delay (t W, t PP, t E, or t BE ). The Write In Progress (WIP) bit is provided in the tatus Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, tand-by Power and eep Power-own Modes When hip elect () is Low, the device is enabled, and in the Active Power mode. When hip elect () is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write tatus Register). The device then goes in to the tand-by Power mode. The device consumption drops to I 1. The eep Power-down mode is entered when the specific instruction (the Enter eep Power-down Mode (P) instruction) is executed. The device consumption drops further to I 2. The device remains in this mode until another specific instruction (the Release from eep Power-down Mode and Read Electronic ignature (RE) instruction) is executed. All other instructions are ignored while the device is in the eep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. tatus Register The tatus Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write tatus Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. RW bit. The tatus Register Write isable (RW) bit is operated in conjunction with the Write Protect (W) signal. The tatus Register Write isable (RW) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the tatus Register (RW, BP2, BP1, BP0) become read-only bits. 7/41

8 Protection Modes The environments where non-volatile memory devices are used can be very noisy. No PI device can operate correctly in the presence of excessive noise. To help combat this, the M25P80 boasts the following data protection mechanisms: Power-On Reset and an internal timer (t PUW ) can provide protection against inadvertant changes while the power supply is outside the operating specification. Program, Erase and Write tatus Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: Power-up Write isable (WRI) instruction completion Write tatus Register (WRR) instruction completion Page Program (PP) instruction completion ector Erase (E) instruction completion Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the oftware Protected Mode (PM). The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and tatus Register Write isable (RW) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the eep Power-down mode offers extra software protection from inadvertant Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from eep Powerdown instruction). Table 2. Protected Area izes tatus Register ontent Memory ontent BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area none All sectors 1 (sixteen sectors: 0 to 15) Upper sixteenth (ector 15) Lower fifteen-sixteenths (fifteen sectors: 0 to 14) Upper eighth (two sectors: 14 and 15) Lower seven-eighths (fourteen sectors: 0 to 13) Upper quarter (four sectors: 12 to 15) Lower three-quarters (twelve sectors: 0 to 11) Upper half (eight sectors: 8 to 15) Lower half (eight sectors: 0 to 7) All sectors (sixteen sectors: 0 to 15) none All sectors (sixteen sectors: 0 to 15) none All sectors (sixteen sectors: 0 to 15) none Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. 8/41

9 Hold ondition The Hold (HOL) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write tatus Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with hip elect () Low. The Hold condition starts on the falling edge of the Hold (HOL) signal, provided that this coincides with erial lock () being Low (as shown in Figure 6.). The Hold condition ends on the rising edge of the Hold (HOL) signal, provided that this coincides with erial lock () being Low. If the falling edge does not coincide with erial lock () being Low, the Hold condition starts after erial lock () next goes Low. imilarly, if the rising edge does not coincide with erial lock () being Low, the Hold condition ends after erial lock () next goes Low. (This is shown in Figure 6.). uring the Hold condition, the erial ata Output (Q) is high impedance, and erial ata Input () and erial lock () are on t are. Normally, the device is kept selected, with hip elect () driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If hip elect () goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOL) High, and then to drive hip elect () Low. This prevents the device from going back to the Hold condition. Figure 6. Hold ondition Activation HOL Hold ondition (standard use) Hold ondition (non-standard use) AI /41

10 MEMORY ORGANIZATION The memory is organized as: 1,048,576 bytes (8 bits each) 16 sectors (512 Kbits, bytes each) 4096 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is ector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 3. Memory Organization ector Address Range 15 F0000h FFFFFh 14 E0000h EFFFFh h FFFFh h FFFFh 11 B0000h BFFFFh 10 A0000h AFFFFh h 9FFFFh h 8FFFFh h 7FFFFh h 6FFFFh h 5FFFFh h 4FFFFh h 3FFFFh h 2FFFFh h 1FFFFh h 0FFFFh 10/41

11 Figure 7. Block iagram HOL W ontrol Logic High Voltage Generator Q I/O hift Register Address Register and ounter 256 Byte ata Buffer tatus Register FFFFFh Y ecoder ize of the read-only memory area 00000h 256 Bytes (Page ize) X ecoder 000FFh AI /41

12 INTRUTION All instructions, addresses and data are shifted in and out of the device, most significant bit first. erial ata Input () is sampled on the first rising edge of erial lock () after hip elect () is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on erial ata Input (), each bit being latched on the rising edges of erial lock (). The instruction set is listed in Table 4.. Every instruction sequence starts with a one-byte instruction code. epending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read ata Bytes (REA), Read ata Bytes at Higher peed (Fast_Read), Read tatus Register (RR) or Release from eep Power-down, and Read Electronic ignature (RE) instruction, the shifted-in instruction sequence is followed by a data-out sequence. hip elect () can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), ector Erase (E), Bulk Erase (BE), Write tatus Register (WRR), Write Enable (WREN), Write isable (WRI) or eep Power-down (P) instruction, hip elect () must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, hip elect () must driven High when the number of clock pulses after hip elect () being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write tatus Register cycle, Program cycle or Erase cycle are ignored, and the internal Write tatus Register cycle, Program cycle or Erase cycle continues unaffected. Table 4. Instruction et Instruction escription One-byte Instruction ode Address Bytes ummy Bytes ata Bytes WREN Write Enable h WRI Write isable h RR Read tatus Register h to WRR Write tatus Register h REA Read ata Bytes h to FAT_REA Read ata Bytes at Higher peed Bh to PP Page Program h to 256 E ector Erase h BE Bulk Erase h P eep Power-down B9h RE Release from eep Power-down, and Read Electronic ignature ABh to Release from eep Power-down /41

13 Write Enable (WREN) The Write Enable (WREN) instruction (Figure 8.) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), ector Erase (E), Bulk Erase (BE) and Write tatus Register (WRR) instruction. The Write Enable (WREN) instruction is entered by driving hip elect () Low, sending the instruction code, and then driving hip elect () High. Figure 8. Write Enable (WREN) Instruction equence Instruction Q High Impedance AI02281E Write isable (WRI) The Write isable (WRI) instruction (Figure 9.) resets the Write Enable Latch (WEL) bit. The Write isable (WRI) instruction is entered by driving hip elect () Low, sending the instruction code, and then driving hip elect () High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write isable (WRI) instruction completion Write tatus Register (WRR) instruction completion Page Program (PP) instruction completion ector Erase (E) instruction completion Bulk Erase (BE) instruction completion Figure 9. Write isable (WRI) Instruction equence Instruction Q High Impedance AI /41

14 Read tatus Register (RR) The Read tatus Register (RR) instruction allows the tatus Register to be read. The tatus Register may be read at any time, even while a Program, Erase or Write tatus Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the tatus Register continuously, as shown in Figure 10.. Table 5. tatus Register Format b7 RW 0 0 BP2 BP1 BP0 WEL WIP tatus Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit The status and control bits of the tatus Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write tatus Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. b0 WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write tatus Register, Program or Erase instruction is accepted. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write tatus Register (WRR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2.) becomes protected against Page Program (PP) and ector Erase (E) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0. RW bit. The tatus Register Write isable (RW) bit is operated in conjunction with the Write Protect (W) signal. The tatus Register Write isable (RW) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the tatus Register Write isable (RW) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the tatus Register (RW, BP2, BP1, BP0) become read-only bits and the Write tatus Register (WRR) instruction is no longer accepted for execution. Figure 10. Read tatus Register (RR) Instruction equence and ata-out equence Instruction tatus Register Out High Impedance Q MB MB tatus Register Out 7 AI02031E 14/41

15 Write tatus Register (WRR) The Write tatus Register (WRR) instruction allows new values to be written to the tatus Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write tatus Register (WRR) instruction is entered by driving hip elect () Low, followed by the instruction code and the data byte on erial ata Input (). The instruction sequence is shown in Figure 11.. The Write tatus Register (WRR) instruction has no effect on b6, b5, b1 and b0 of the tatus Register. b6 and b5 are always read as 0. hip elect () must be driven High after the eighth bit of the data byte has been latched in. If not, the Write tatus Register (WRR) instruction is not executed. As soon as hip elect () is driven High, the self-timed Write tatus Register cycle (whose duration is t W ) is initiated. While the Write tatus Register cycle is in progress, the tatus Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write tatus Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write tatus Register (WRR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2.. The Write tatus Register (WRR) instruction also allows the user to set or reset the tatus Register Write isable (RW) bit in accordance with the Write Protect (W) signal. The tatus Register Write isable (RW) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write tatus Register (WRR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. Figure 11. Write tatus Register (WRR) Instruction equence Instruction tatus Register In Q High Impedance MB AI /41

16 Table 6. Protection Modes W ignal RW Bit Mode oftware Protected (PM) Hardware Protected (HPM) Write Protection of the tatus Register tatus Register is Writable (if the WREN instruction has set the WEL bit) The values in the RW, BP2, BP1 and BP0 bits can be changed tatus Register is Hardware write protected The values in the RW, BP2, BP1 and BP0 bits cannot be changed Memory ontent Protected Area 1 Unprotected Area 1 Protected against Page Program, ector Erase and Bulk Erase Protected against Page Program, ector Erase and Bulk Erase Ready to accept Page Program and ector Erase instructions Ready to accept Page Program and ector Erase instructions Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the tatus Register, as shown in Table 2.. The protection features of the device are summarized in Table 6.. When the tatus Register Write isable (RW) bit of the tatus Register is 0 (its initial delivery state), it is possible to write to the tatus Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the tatus Register Write isable (RW) bit of the tatus Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W): If Write Protect (W) is driven High, it is possible to write to the tatus Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the tatus Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the tatus Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (PM) by the Block Protect (BP2, BP1, BP0) bits of the tatus Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the tatus Register Write isable (RW) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the tatus Register Write isable (RW) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the oftware Protected Mode (PM), using the Block Protect (BP2, BP1, BP0) bits of the tatus Register, can be used. 16/41

17 Read ata Bytes (REA) The device is first selected by driving hip elect () Low. The instruction code for the Read ata Bytes (REA) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of erial lock (). Then the memory contents, at that address, is shifted out on erial ata Output (Q), each bit being shifted out, at a maximum frequency f R, during the falling edge of erial lock (). The instruction sequence is shown in Figure 12.. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read ata Bytes (REA) instruction. When the highest address is reached, the address counter rolls over to h, allowing the read sequence to be continued indefinitely. The Read ata Bytes (REA) instruction is terminated by driving hip elect () High. hip elect () can be driven High at any time during data output. Any Read ata Bytes (REA) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read ata Bytes (REA) Instruction equence and ata-out equence Instruction 24-Bit Address Q High Impedance MB ata Out 1 ata Out MB AI03748 Note: Address bits A23 to A20 are on t are. 17/41

18 Read ata Bytes at Higher peed (FAT_REA) The device is first selected by driving hip elect () Low. The instruction code for the Read ata Bytes at Higher peed (FAT_REA) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of erial lock (). Then the memory contents, at that address, is shifted out on erial ata Output (Q), each bit being shifted out, at a maximum frequency f, during the falling edge of erial lock (). The instruction sequence is shown in Figure 13.. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read ata Bytes at Higher peed (FAT_REA) instruction. When the highest address is reached, the address counter rolls over to h, allowing the read sequence to be continued indefinitely. The Read ata Bytes at Higher peed (FAT_REA) instruction is terminated by driving hip elect () High. hip elect () can be driven High at any time during data output. Any Read ata Bytes at Higher peed (FAT_REA) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read ata Bytes at Higher peed (FAT_REA) Instruction equence and ata-out equence Instruction 24 BIT ARE Q High Impedance ummy Byte ATA OUT 1 ATA OUT 2 Q MB MB 7 MB AI04006 Note: Address bits A23 to A20 are on t are. 18/41

19 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving hip elect () Low, followed by the instruction code, three address bytes and at least one data byte on erial ata Input (). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). hip elect () must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14.. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 ata bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Instruction Times (evice Grade 6) and Instruction Times (evice Grade 3)). hip elect () must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as hip elect () is driven High, the selftimed Page Program cycle (whose duration is t PP ) is initiated. While the Page Program cycle is in progress, the tatus Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3. and Table 2.) is not executed. 19/41

20 Figure 14. Page Program (PP) Instruction equence Instruction 24-Bit Address ata Byte MB MB ata Byte 2 ata Byte 3 ata Byte MB MB MB AI04082B Note: Address bits A23 to A20 are on t are. 20/41

21 ector Erase (E) The ector Erase (E) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The ector Erase (E) instruction is entered by driving hip elect () Low, followed by the instruction code, and three address bytes on erial ata Input (). Any address inside the ector (see Table 3.) is a valid address for the ector Erase (E) instruction. hip elect () must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15.. hip elect () must be driven High after the eighth bit of the last address byte has been latched in, otherwise the ector Erase (E) instruction is not executed. As soon as hip elect () is driven High, the self-timed ector Erase cycle (whose duration is t E ) is initiated. While the ector Erase cycle is in progress, the tatus Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed ector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A ector Erase (E) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3. and Table 2.) is not executed. Figure 15. ector Erase (E) Instruction equence Instruction 24 Bit Address MB AI03751 Note: Address bits A23 to A20 are on t are. 21/41

22 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving hip elect () Low, followed by the instruction code on erial ata Input (). hip elect () must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16.. hip elect () must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as hip elect () is driven High, the self-timed Bulk Erase cycle (whose duration is t BE ) is initiated. While the Bulk Erase cycle is in progress, the tatus Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 16. Bulk Erase (BE) Instruction equence Instruction AI /41

23 eep Power-down (P) Executing the eep Power-down (P) instruction is the only way to put the device in the lowest consumption mode (the eep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. riving hip elect () High deselects the device, and puts the device in the tandby mode (if there is no internal cycle currently in progress). But this mode is not the eep Power-down mode. The eep Power-down mode can only be entered by executing the eep Power-down (P) instruction, to reduce the standby current (from I 1 to I 2, as specified in Table 12.). Once the device has entered the eep Powerdown mode, all instructions are ignored except the Release from eep Power-down and Read Electronic ignature (RE) instruction. This releases the device from this mode. The Release from eep Power-down and Read Electronic ignature (RE) instruction also allows the Electronic ignature of the device to be output on erial ata Output (Q). The eep Power-down mode automatically stops at Power-down, and the device always Powers-up in the tandby mode. The eep Power-down (P) instruction is entered by driving hip elect () Low, followed by the instruction code on erial ata Input (). hip elect () must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17.. hip elect () must be driven High after the eighth bit of the instruction code has been latched in, otherwise the eep Power-down (P) instruction is not executed. As soon as hip elect () is driven High, it requires a delay of t P before the supply current is reduced to I 2 and the eep Power-down mode is entered. Any eep Power-down (P) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. eep Power-down (P) Instruction equence t P Instruction tand-by Mode eep Power-down Mode AI /41

24 Release from eep Power-down and Read Electronic ignature (RE) Once the device has entered the eep Powerdown mode, all instructions are ignored except the Release from eep Power-down and Read Electronic ignature (RE) instruction. Executing this instruction takes the device out of the eep Power-down mode. The instruction can also be used to read, on erial ata Output (Q), the 8-bit Electronic ignature, whose value for the M25P80 is 13h. Except while an Erase, Program or Write tatus Register cycle is in progress, the Release from eep Power-down and Read Electronic ignature (RE) instruction always provides access to the 8- bit Electronic ignature of the device, and can be applied even if the eep Power-down mode has not been entered. Any Release from eep Power-down and Read Electronic ignature (RE) instruction while an Erase, Program or Write tatus Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving hip elect () Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on erial ata Input () during the rising edge of erial lock (). Then, the 8-bit Electronic ignature, stored in the memory, is shifted out on erial ata Output (Q), each bit being shifted out during the falling edge of erial lock (). The instruction sequence is shown in Figure 18.. The Release from eep Power-down and Read Electronic ignature (RE) instruction is terminated by driving hip elect () High after the Electronic ignature has been read at least once. ending additional clock cycles on erial lock (), while hip elect () is driven Low, cause the Electronic ignature to be output repeatedly. When hip elect () is driven High, the device is put in the tand-by Power mode. If the device was not previously in the eep Power-down mode, the transition to the tand-by Power mode is immediate. If the device was previously in the eep Power-down mode, though, the transition to the tandby Power mode is delayed by t RE2, and hip elect () must remain High for at least t RE2 (max), as specified in Table 17.. Once in the tand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 18. Release from eep Power-down and Read Electronic ignature (RE) Instruction equence and ata-out equence Instruction 3 ummy Bytes t RE Q High Impedance MB Electronic ignature Out MB eep Power-down Mode tand-by Mode AI04047 Note: The value of the 8-bit Electronic ignature, for the M25P80, is 13h. 24/41

25 Figure 19. Release from eep Power-down (RE) Instruction equence t RE1 Instruction Q High Impedance eep Power-down Mode tand-by Mode AI04078B riving hip elect () High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic ignature has been transmitted for the first time (as shown in Figure 19.), still insures that the device is put into tand-by Power mode. If the device was not previously in the eep Power-down mode, the transition to the tand-by Power mode is immediate. If the device was previously in the eep Powerdown mode, though, the transition to the tand-by Power mode is delayed by t RE1, and hip elect () must remain High for at least t RE1 (max), as specified in Table 17.. Once in the tand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 25/41

26 POWER-UP AN POWER-OWN At Power-up and Power-down, the device must not be selected (that is hip elect () must follow the voltage applied on V ) until V reaches the correct value: V (min) at Power-up, and then for a further delay of t VL V at Power-down Usually a simple pull-up resistor on hip elect () can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while V is less than the POR threshold value, V WI all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), ector Erase (E), Bulk Erase (BE) and Write tatus Register (WRR) instructions until a time delay of t PUW has elapsed after the moment that V rises above the V WI threshold. However, the correct operation of the device is not guaranteed if, by this time, V is still below V (min). No Write tatus Register, Program or Erase instructions should be sent until the later of: t PUW after V passed the V WI threshold t VL afterv passed the V (min) level These values are specified in Table 7.. If the delay, t VL, has elapsed, after V has risen above V (min), the device can be selected for REA instructions even if the t PUW delay is not yet fully elapsed. At Power-up, the device is in the following state: The device is in the tandby mode (not the eep Power-down mode). The Write Enable Latch (WEL) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the V feed. Each device in a system should have the V rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1µF). At Power-down, when V drops from the operating voltage, to below the POR threshold value, V WI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.) 26/41

27 Figure 20. Power-up Timing V V (max) Program, Erase and Write ommands are Rejected by the evice hip election Not Allowed V (min) Reset tate of the evice tvl Read Access allowed evice fully accessible V WI tpuw time AI04009 Table 7. Power-Up Timing and V WI Threshold ymbol Parameter Min. Max. Unit t 1 VL V (min) to low 10 µs 1 t PUW Time delay to Write instruction 1 10 ms 1 V WI Write Inhibit Voltage 1 2 V Note: 1. These parameters are characterized only. INITIAL ELIVERY TATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The tatus Register contains 00h (all tatus Register bits are 0). 27/41

28 MAXIMUM RATING tressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the TMicroelectronics URE Program and other relevant quality documents. Table 8. Absolute Maximum Ratings ymbol Parameter Min. Max. Unit T TG torage Temperature V IO Input and Output Voltage (with respect to Ground) V V upply Voltage V V E Electrostatic ischarge Voltage (Human Body model) V Note: 1. JEE td JE22-A114A (1=100 pf, R1=1500 Ω, R2=500 Ω) 28/41

29 AN A PARAMETER This section summarizes the operating and measurement conditions, and the and A characteristics of the device. The parameters in the and A haracteristic tables that follow are derived from tests performed under the Measurement onditions summarized in the relevant tables. esigners should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 9. Operating onditions ymbol Parameter Min. Max. Unit V upply Voltage V T Ambient Operating Temperature (evice Grade 6) A Ambient Operating Temperature (evice Grade 3) Table 10. ata Retention and Endurance Parameter ondition Min. Max. Unit Erase/Program ycles ata Retention Note: 1. This is preliminary data evice Grade evice Grade evice Grade 6 20 evice Grade 3 1 (at 85 ) 20 cycles per sector years Table 11. apacitance ymbol Parameter Test ondition Min. Max. Unit OUT Output apacitance (Q) V OUT = 0V 8 pf IN Input apacitance (other pins) V IN = 0V 6 pf Note: ampled only, not 100% tested, at T A =25 and a frequency of 20MHz. 29/41

30 Table 12. haracteristics (evice Grade 6) ymbol Parameter Test ondition (in addition to those in Table 9.) Min. Max. Unit I LI Input Leakage urrent ± 2 µa I LO Output Leakage urrent ± 2 µa I 1 tandby urrent = V, V IN = V or V 50 µa I 2 eep Power-down urrent = V, V IN = V or V 10 µa =0.1V / 0.9.V at 40MHz, 8 ma Q = open I 3 Operating urrent (REA) =0.1V / 0.9.V at 20MHz, Q = open 4 ma I 4 Operating urrent (PP) = V 15 ma I 5 Operating urrent (WRR) = V 15 ma I 6 Operating urrent (E) = V 15 ma I 7 Operating urrent (BE) = V 15 ma V IL Input Low Voltage V V V IH Input High Voltage 0.7V V +0.4 V V OL Output Low Voltage I OL = 1.6mA 0.4 V V OH Output High Voltage I OH = 100µA V 0.2 V Table 13. haracteristics (evice Grade 3) ymbol Parameter Test ondition Min. (in addition to those in Table 9.) 1 Max. 1 Unit I LI Input Leakage urrent ± 2 µa I LO Output Leakage urrent ± 2 µa I 1 tandby urrent = V, V IN = V or V 100 µa I 2 eep Power-down urrent = V, V IN = V or V 50 µa =0.1V / 0.9.V at 40MHz, 8 ma Q = open I 3 Operating urrent (REA) =0.1V / 0.9.V at 20MHz, Q = open 4 ma I 4 Operating urrent (PP) = V 15 ma I 5 Operating urrent (WRR) = V 15 ma I 6 Operating urrent (E) = V 15 ma I 7 Operating urrent (BE) = V 15 ma V IL Input Low Voltage V V V IH Input High Voltage 0.7V V +0.4 V V OL Output Low Voltage I OL = 1.6mA 0.4 V V OH Output High Voltage I OH = 100µA V 0.2 V Note: 1. This is preliminary data 30/41

31 Table 14. Instruction Times (evice Grade 6) Test conditions specified in Table 9. and Table 16. ymbol Alt. Parameter Min. Typ. Max. Unit t W Write tatus Register ycle Time 5 15 ms t PP (1) Page Program ycle Time (256 Bytes) 1.4 Page Program ycle Time (n Bytes) 0.4+ n*1/256 5 ms t E ector Erase ycle Time 1 3 s t BE Bulk Erase ycle Time s 1. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 n 256) Table 15. Instruction Times (evice Grade 3) Test conditions specified in Table 9. and Table 16. ymbol Alt. Parameter Min. Typ. 1,2 Max. 2 Unit t W Write tatus Register ycle Time 8 15 ms Page Program ycle Time (256 Bytes) 1.5 t PP 3 Page Program ycle Time (n Bytes) 0.4+ n*1.1/ ms t E ector Erase ycle Time 1 3 s t BE Bulk Erase ycle Time s Note: 1. At This is preliminary data 3. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 n 256) Table 16. A Measurement onditions ymbol Parameter Min. Max. Unit L Load apacitance 30 pf Input Rise and Fall Times 5 ns Input Pulse Voltages 0.2V to 0.8V V Input Timing Reference Voltages 0.3V to 0.7V V Output Timing Reference Voltages V / 2 V Note: Output Hi-Z is defined as the point where data out is no longer driven. 31/41

32 Figure 21. A Measurement I/O Waveform Input Levels 0.8V 0.2V Input and Output Timing Reference Levels 0.7V 0.5V 0.3V AI07455 Table 17. A haracteristics (25MHz Operation, evice Grade 6 or 3) Test conditions specified in Table 9. and Table 16. ymbol Alt. Parameter Min. 5 Typ. Max. 5 Unit f f FAT_REA, PP, E, BE, P, RE, lock Frequency for the following instructions: WREN, WRI, RR, WRR.. 25 MHz f R lock Frequency for REA instructions.. 20 MHz t H 1 t LH lock High Time 18 ns t L 1 t LL lock Low Time 18 ns t LH 2 t HL 2 lock Rise Time 3 (peak to peak) 0.1 V/ns lock Fall Time 3 (peak to peak) 0.1 V/ns t LH t Active etup Time (relative to ) 10 ns t HL Not Active Hold Time (relative to ) 10 ns t VH t U ata In etup Time 5 ns t HX t H ata In Hold Time 5 ns t HH Active Hold Time (relative to ) 10 ns t HH Not Active etup Time (relative to ) 10 ns t HL t H eselect Time 100 ns 2 t HQZ t I Output isable Time 15 ns t LQV t V lock Low to Output Valid 15 ns t LQX t HO Output Hold Time 0 ns t HLH HOL etup Time (relative to ) 10 ns t HHH HOL Hold Time (relative to ) 10 ns t HHH HOL etup Time (relative to ) 10 ns t HHL HOL Hold Time (relative to ) 10 ns 2 t HHQX t LZ HOL to Output Low-Z 15 ns 32/41