M95640, M95320 M95160, M /32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock

Transcription

1 M95640, M95320 M9560, M /32/6/8 Kbit erial PI Bus EEPROM With High peed lock PRELIMINARY ATA PI Bus ompatible erial Interface upports Positive lock PI Modes 5 MHz lock Rate (maximum) ingle upply Voltage: 4.5V to 5.5V for M95xxx 2.7V to 5.5V for M95xxx-V 2.5V to 5.5V for M95xxx-W.8V to 3.6V for M95xxx-R tatus Register Hardware and oftware Protection of the tatus Register BYTE and PAGE WRITE (up to 32 Bytes) elf-timed Programming ycle Adjustable ize Read-Only EEPROM Area Enhanced E Protection 00,000 Erase/Write ycles (minimum) 40 Year ata Retention (minimum) ERIPTION These PI-compatible electrically erasable programmable memory (EEPROM) devices are organized as 8K x 8 bits and 4K x 8 bits (M95640, M95320) and 2K x 8 bits and K x 8 bits (M9560, M95080), and operate down to 2.5 V (for the -W 8 PIP8 (BN) 0.25 mm frame 8 TOP8 (W) 69 mil width Figure. Logic iagram V 8 O8 (MN) 50 mil width 4 TOP4 (L) 69 mil width Table. ignal Names erial lock erial ata Input erial ata Output hip elect W Write Protect W HOL M95xxx HOL Hold V upply Voltage V AI0789 V Ground July 2000 This is preliminary information on a new product now in development or undergoing evaluation. etails are subject to change without notice. /2

2 Figure 2A. IP onnections Figure 2. TOP4 onnections M95xxx W V M95xxx AI0790 V HOL N N N W V V 3 HOL 2 N N 0 N 9 8 AI02346B Note:. N = Not onnected Figure 2B. O8 and TOP8 onnections W V M95xxx AI079 5 V HOL version of each device), and down to.8 V (for the -R version of each device). The M95640, M95320 and M9560, M95080 are available in Plastic ual-in-line, Plastic mall Outline and Thin hrink mall Outline packages. Each memory device is accessed by a simple serial interface that is PI bus compatible. The bus signals are, and, as shown in Table and Figure 3. The device is selected when the chip select input () is held low. ommunications with the chip can be interrupted using the hold input (HOL). Table 2. Absolute Maximum Ratings ymbol Parameter Value Unit T A Ambient Operating Temperature 40 to 25 T TG torage Temperature 65 to 50 T LEA Lead Temperature during oldering PIP8: 0 sec O8: 40 sec TOP4: t.b.c t.b.c. V O Output Voltage 0.3 to V +0.6 V V I Input Voltage 0.3 to 6.5 V V upply Voltage 0.3 to 6.5 V V E Electrostatic ischarge Voltage (Human Body model) V Note:. Except for the rating Operating Temperature Range, stresses above those listed in the Table Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the T URE Program and other relevant quality documents. 2. JEE td JE22-A4A (=00 pf, R=500 Ω, R2=500 Ω) 2/2

3 Figure 3. Microcontroller and Memory evices on the PI Bus PI Interface with (POL, PHA) = ('0', '0') or ('', '') O I K Master (T6, T7, T9, T0, Others) M95xxx M95xxx M95xxx 3 2 AI0958 IGNAL ERIPTION erial Output () The output pin is used to transfer data serially out of the Memory. ata is shifted out on the falling edge of the serial clock. erial Input () The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock. erial lock () The serial clock provides the timing for the serial interface (as shown in Figure 4). Instructions, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the pin changes state after the falling edge of the clock input. hip elect () When is high, the memory device is deselected, and the output pin is held in its high impedance state. Unless an internal write operation is underway, the memory device is placed in its stand-by power mode. After power-on, a high-to-low transition on is required prior to the start of any operation. Write Protect (W) The protection features of the memory device are summarized in Table 3. The hardware write protection, controlled by the W pin, restricts write access to the tatus Register (though not to the WIP and WEL bits, which are set or reset by the device internal logic). Bit 7 of the status register (as shown in Table 5) is the tatus Register Write isable bit (RW). When this is set to 0 (its initial delivery state) it is possible to write to the status register if the WEL bit (Write Enable Latch) has been set by the WREN instruction (irrespective of the level being applied to the W input). When bit 7 (RW) of the status register is set to, the ability to write to the status register depends on the logic level being presented at pin W: If W pin is high, it is possible to write to the status register, after having set the WEL bit using the WREN instruction (Write Enable Latch). If W pin is low, any attempt to modify the status register is ignored by the device, even if the WEL bit has been set. As a consequence, all the data bytes in the EEPROM area, protected by the BPn bits of the status register, are also hardware protected against data corruption, and appear as a Read Only EEPROM area for the microcontroller. This mode is called the Hardware Protected Mode (HPM). It is possible to enter the Hardware Protected Mode (HPM) either by setting the RW bit after pulling low the W pin, or by pulling low the W pin after setting the RW bit. The only way to abort the Hardware Protected Mode, once entered, is to pull high the W pin. If W pin is permanently tied to the high level, the Hardware Protected Mode is never activated, and 3/2

4 Figure 4. ata and lock Timing POL PHA 0 0 or MB LB AI0438 the memory device only allows the user to protect a part of the memory, using the BPn bits of the status register, in the oftware Protected Mode (PM). Hold (HOL) The HOL pin is used to pause the serial communications between the PI memory and controller, without losing bits that have already been decoded in the serial sequence. For a hold condition to occur, the memory device must already have been selected ( = 0). The hold condition starts when the HOL pin is held low while the clock pin () is also low (as shown in Figure 4). uring the hold condition, the output pin is held in its high impedance state, and the levels on the input pins ( and ) are ignored by the memory device. It is possible to deselect the device when it is still in the hold state, thereby resetting whatever transfer had been in progress. The memory remains in the hold state as long as the HOL pin is low. To restart communication with the device, it is necessary both to remove the hold condition (by taking HOL high) and to select the memory (by taking low). OPERATION All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input () sampled on the first rising edge of the clock () after the chip select () goes low. Every instruction starts with a single-byte code, as summarised in Table 4. This code is entered via the data input (), and latched on the rising edge of the clock input (). To enter an instruction code, the product must have been previously selected ( held low). If an invalid instruction is sent (one not contained in Table 4), the chip automatically deselects itself. Write Enable (WREN) and Write isable (WRI) The write enable latch, inside the memory device, must be set prior to each WRITE and WRR operation. The WREN instruction (write enable) sets this latch, and the WRI instruction (write disable) resets it. Table 3. Write Protection ontrol on the M95640, M95320, M9560, M95080 W RW Bit Mode tatus Register Protected Area ata Bytes Unprotected Area 0 or 0 oftware Protected (PM) Writeable (if the WREN instruction has set the WEL bit) The data write protection is defined by the BP, BP0 bits. The BP, BP0 bits can be modified by software (using WREN and WRR) Writeable (if the WREN instruction has set the WEL bit) 0 Hardware Protected (HPM) Hardware write protected The data write protection is defined by the BP, BP0 bits, which are, themselves, hardware write protected. Writeable (if the WREN instruction has set the WEL bit) 4/2

5 Figure 5. Block iagram HOL W ontrol Logic High Voltage Generator I/O hift Register Address Register and ounter ata Register An - 3 tatus Register An ize of the Read only EEPROM area Y ecoder 32 Bytes 0000h 00Fh X ecoder AI0792 Note:. The cell An represents the byte at the highest address in the memory The latch becomes reset by any of the following events: Power on WRI instruction completion WRR instruction completion WRITE instruction completion. As soon as the WREN or WRI instruction is received, the memory device first executes the instruction, then enters a wait mode until the device is deselected. Read tatus Register (RR) The RR instruction allows the status register to be read, and can be sent at any time, even during a Write operation. Indeed, when a Write is in progress, it is recommended that the value of the Write-In-Progress (WIP) bit be checked. The value in the WIP bit (whose position in the status register is shown in Table 5) can be continuously polled, before sending a new WRITE instruction. This can be performed in one of two ways: Repeated RR instructions (each one consisting of being taken low, being clocked 8 times for the instruction and 8 times for the read operation, and being taken high) A single, prolonged RR instruction (consisting of being taken low, being 5/2

6 Table 4. Instruction et Instruc tion escription Table 5. tatus Register Format Note:. RW, BP0 and BP are Read and write bits. 2. WEL and WIP are Read only bits. Instruction Format WREN et Write Enable Latch WRI Reset Write Enable Latch RR Read tatus Register WRR Write tatus Register REA Read ata from Memory Array WRITE Write ata to Memory Array b7 RW X X X BP BP0 WEL WIP clocked 8 times for the instruction and kept running for repeated read operations), as shown in Figure 6. The Write-In-Process (WIP) bit is read-only, and indicates whether the memory is busy with a Write operation. A indicates that a write is in progress, and a 0 that no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. It, too, is read-only. Its value can only be changed by one of the events listed in the previous paragraph, or as a result of executing WREN or WRI instruction. It cannot be changed using a WRR instruction. A indicates that the latch is set (the forthcoming Write instruction will be executed), and a 0 that it is reset (and any forthcoming Write instructions will be ignored). b0 The Block Protect (BP0 and BP) bits indicate the amount of the memory that is to be writeprotected. These two bits are non-volatile. They are set using a WRR instruction. uring a Write operation (whether it be to the memory area or to the status register), all bits of the status register remain valid, and can be read using the RR instruction. However, during a Write operation, the values of the non-volatile bits (RW, BP0, BP) become frozen at a constant value. The updated value of these bits becomes available when a new RR instruction is executed, after completion of the write cycle. On the other hand, the two read-only bits (WEL, WIP) are dynamically updated during internal write cycles. Using this facility, it is possible to poll the WIP bit to detect the end of the internal write cycle. Write tatus Register (WRR) The format of the WRR instruction is shown in Figure 7. After the instruction and the eight bits of the status register have been latched-in, the internal Write cycle is triggered by the rising edge of the line. This must occur after the falling edge of the 6 th clock pulse, and before the rising edge of the 7 th clock (as indicated in Figure 7), otherwise the internal write sequence is not performed. The WRR instruction is used for the following: to select the size of memory area that is to be write-protected to select between PM (oftware Protected Mode) and HPM (Hardware Protected Mode). The size of the write-protection area applies equally in PM and HPM. The BP and BP0 bits of the status register have the appropriate value (see Table 6) written into them after the contents of the protected area of the EEPROM have been written. Figure 6. RR: Read tatus Register equence INTRUTION TATU REG. OUT HIGH IMPEANE MB TATU REG. OUT MB 7 MB AI0203 6/2

7 Table 6. Write Protected Block ize tatus Register Bits Protected Block Array Addresses Protected BP BP0 M95640 M95320 M9560 M none none none none none 0 Upper quarter 800h - FFFh 000h - 0FFFh 0600h - 07FFh 0300h - 03FFh 0 Upper half 000h - FFFh 0800h - 0FFFh 0400h - 07FFh 0200h - 03FFh Whole memory 0000h - FFFh 0000h - 0FFFh 0000h - 07FFh 0000h - 03FFh The initial delivery state of the BP and BP0 bits is 00, indicating a write-protection size of 0. oftware Protected Mode (PM) The act of writing a non-zero value to the BP and BP0 bits causes the oftware Protected Mode (PM) to be started. All attempts to write a byte or page in the protected area are ignored, even if the Write Enable Latch is set. However, writing is still allowed in the unprotected area of the memory array and to the RW, BP and BP0 bits of the status register, provided that the WEL bit is first set. Hardware Protected Mode (HPM) The Hardware Protected Mode (HPM) offers a higher level of protection, and can be selected by setting the RW bit after pulling down the W pin or by pulling down the W pin after setting the RW bit. The RW is set by the WR instruction, provided that the WEL bit is first set. The setting of the RW bit can be made independently of, or at the same time as, writing a new value to the BP and BP0 bits. Once the device is in the Hardware Protected Mode, the data bytes in the protected area of the memory array, and the content of the status register, are write-protected. The only way to reenable writing new values to the status register is to pull the W pin high. This cause the device to leave the Hardware Protected Mode, and to revert to being in the oftware Protected Mode. (The value in the BP and BP0 bits will not have been changed). Further details of the operation of Write Protect (W) are given earlier, on page 3. Typical Use of HPM and PM Write Protect (W) can be driven by an output port of a microcontroller. It is important that Write Protect (W) remains stable (permanently High, or permanently Low) throughout the duration of the Write tatus Register sequence, shown in Figure 7). It is also possible to connect it permanently to V (by a solder connection, or through a pull-down resistor). The manufacturer of such a printed circuit board can take the memory device, still in its initial delivery state, and can solder it directly on to the board. After power on, the microcontroller can be instructed to write the protected data into the appropriate area of the memory. When it has finished, the appropriate values are written to the Figure 7. WRR: Write tatus Register equence INTRUTION TATU REG. HIGH IMPEANE MB AI02282B 7/2

8 Figure 8. Read EEPROM Array Operation equence INTRUTION 6 BIT ARE HIGH IMPEANE MB ATA OUT AI0793 Note:. epending on the memory size, as shown in Table 7, the most significant address bits are on t are. BP, BP0 and RW bits, thereby putting the device in the hardware protected mode. An alternative method is to write the protected data, and to set the BP, BP0 and RW bits, before soldering the memory device to the board. Again, this results in the memory device being placed in its hardware protected mode. If the W pin has been connected to V by a pulldown resistor, the memory device can be taken out of the hardware protected mode by driving the W pin high, to override the pull-down resistor. If the W pin has been directly soldered to V, there is only one way of taking the memory device out of the hardware protected mode: the memory device must be de-soldered from the board, and connected to external equipment in which the W pin is allowed to be taken high. Table 7. Address Range Bits evice M95640 M95320 M9560 M95080 Address Bits A2-A0 A-A0 A0-A0 A9-A0 Note:. Other address bits up to b5 are treated as on t are. Read Operation The chip is first selected by holding low. The serial one byte read instruction is followed by a two byte address (A5-A0), each bit being latched-in during the rising edge of the clock (). The data stored in the memory, at the selected address, is shifted out on the output pin. Each bit is shifted out during the falling edge of the clock () as shown in Figure 8. The internal address counter is automatically incremented to the next higher address after each byte of data has been shifted out. The data stored in the memory, at the next address, can be read by successive clock Figure 9. Write Enable Latch equence INTRUTION HIGH IMPEANE AI0228 8/2

9 Figure 0. Byte Write Operation equence INTRUTION 6 BIT ARE ATA BYTE HIGH IMPEANE AI0795 Note:. epending on the memory size, as shown in Table 7, the most significant address bits are on t are. pulses. When the highest address is reached, the address counter rolls over to 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by deselecting the chip. The chip can be deselected at any time during data output. If a read instruction is received during a write cycle, it is rejected, and the memory device deselects itself. Byte Write Operation Before any write can take place, the WEL bit must be set, using the WREN instruction. The write state is entered by selecting the chip, issuing three Figure. Page Write Operation equence INTRUTION 6 BIT ARE ATA BYTE ATA BYTE 2 ATA BYTE 3 ATA BYTE N AI0796 Note:. epending on the memory size, as shown in Table 7, the most significant address bits are on t are. 9/2

10 bytes of instruction and address, and one byte of data. hip elect () must remain low throughout the operation, as shown in Figure 0. The product must be deselected just after the eighth bit of the data byte has been latched in, as shown in Figure 0, otherwise the write process is cancelled. As soon as the memory device is deselected, the selftimed internal write cycle is initiated. While the write is in progress, the status register may be read to check the status of the RW, BP, BP0, WEL and WIP bits. In particular, WIP contains a during the self-timed write cycle, and a 0 when the cycle is complete, (at which point the write enable latch is also reset). Page Write Operation A maximum of 32 bytes of data can be written during one Write time, t W, provided that they are all to the same page (see Figure 5). The Page Write operation is the same as the Byte Write operation, except that instead of deselecting the device after the first byte of data, up to 3 additional bytes can be shifted in (and then the device is deselected after the last byte). Any address of the memory can be chosen as the first address to be written. If the address counter reaches the end of the page (an address of the form xxxx xxxx xxx ) and the clock continues, the counter rolls over to the first address of the same page (xxxx xxxx xxx0 0000) and over-writes any previously written data. As before, the Write cycle only starts if the transition occurs just after the eighth bit of the last data byte has been received, as shown in Figure. After execution of a WREN, WRI, or RR instruction, the chip enters a wait state, and waits to be deselected. Invalid and HOL transitions are ignored. POWER ON TATE After power-on, the memory device is in the following state: low power stand-by state deselected (after power-on, a high-to-low transition is required on the input before any operations can be started). not in the hold condition the WEL bit is reset the RW, BP and BP0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). Table 8. Initial tatus Register Format b INITIAL ELIVERY TATE The device is delivered with the memory array in a fully erased state (all data set at all s, FFh). The status register bits are initialized to 00h, as shown in Table 8. b0 ATA PROTETION AN PROTOOL AFETY To protect the data in the memory from inadvertent corruption, the memory device only responds to correctly formulated commands. The main security measures can be summarised as follows: The WEL bit is reset at power-up. must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register). Accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. Table 9. Input Parameters (T A = 25, f = 5 MHz) ymbol Parameter Test ondition Min. Max. Unit OUT Output apacitance () 8 pf IN Input apacitance (other pins) 6 pf Note:. ampled only, not 00% tested. 0/2

11 Table 0. haracteristics (T A = 0 to 70, 40 to 85 or -40 to 25 ; V = 4.5 to 5.5 V) (T A = 0 to 70 or 40 to 85 ; V = 2.7 to 5.5 V) (T A = 0 to 70 or 40 to 85 ; V = 2.5 to 5.5 V) (T A = 0 to 70 or 20 to 85 ; V =.8 to 3.6 V) ymbol I LI I LO Parameter Input Leakage urrent Output Leakage urrent Voltage Range Temp. Range Test ondition Min. Max. Unit all all ± 2 µa all all ± 2 µa = 0.V /0.9V, at 5 MHz, V = 5 V, = open 4 ma I upply urrent = 0.V /0.9V, at 2 MHz, V = 5 V, = open = 0.V /0.9V, at 5 MHz, V = 2.7 V, = open 4 ma 3 ma = 0.V /0.9V, at 2 MHz, V = 2.5 V, = open 2 ma = 0.V /0.9V, at MHz, V =.8 V, = open 2 ma I V IL V IH V OL V OH upply urrent (tand-by) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage = V, V IN = V or V, V = 5 V 0 µa = V, V IN = V or V, V = 5 V 0 µa = V, V IN = V or V, V = 2.7 V 2 µa = V, V IN = V or V, V = 2.5 V 2 µa = V, V IN = V or V, V =.8 V µa all all V V all all 0.7 V V + V I OL = 2 ma 0.4 V I OL = 2 ma 0.4 V I OL =.5 ma 0.4 V I OL =.5 ma 0.4 V I OL = 0.5 ma 0.3 V I OH = 2 ma 0.8 V V I OH = 2 ma 0.8 V V I OH = 0.4 ma 0.8 V V I OH = 0.4 ma 0.8 V V I OH = 0. ma 0.8 V V Note:. For all 5V range devices, the device meets the output requirements for both TTL and MO standards. /2

12 Table A. A haracteristics ymbol Alt. Parameter M95640, M95320, M9560, M95080 V =4.5 to 5.5 V T A =0 to 70 or 40 to 85 V =4.5 to 5.5 V T A = 40 to 25 Min Max Min Max Unit f f K lock Frequency MHz t LH t Active etup Time ns t HH t 2 Not Active etup Time ns t HL t eselect Time ns t HH t H Active Hold Time ns t HL Not Active Hold Time ns t H t LH lock High Time ns t L t LL lock Low Time ns t LH 2 t R lock Rise Time µs t HL 2 t F lock Fall Time µs t VH t U ata In etup Time ns t HX t H ata In Hold Time ns t LH 2 t RI ata In Rise Time µs t HL 2 t FI ata In Fall Time µs t HHH t lock Low Hold Time after HOL not Active ns t HLH lock Low Hold Time after HOL Active ns t LHL lock Low et-up Time before HOL Active 0 0 ns t LHH lock Low et-up Time before HOL not Active 0 0 ns t HZ 2 t I Output isable Time ns t LV t V lock Low to Output Valid ns t LX t HO Output Hold Time 0 0 ns t LH 2 t RO Output Rise Time ns t HL 2 t FO Output Fall Time ns t HHX 2 t LZ HOL High to Output Low-Z ns t HLZ 2 t HZ HOL Low to Output High-Z ns t W t W Write Time 0 0 ms Note:. t H + t L / f. 2. Value guaranteed by characterization, not 00% tested in production. 2/2

13 Table B. A haracteristics ymbol Alt. Parameter M95xxx-V M95xxx-W M95xxx-R V =2.7 to 5.5 V T A =0 to 70 or 40 to 85 V =2.5 to 5.5 V T A =0 to 70 or 40 to 85 V =.8 to 3.6 V T A =0 to 70 or 20 to 85 Min Max Min Max Min Max Unit f f K lock Frequency MHz t LH t Active etup Time ns t HH t 2 Not Active etup Time ns t HL t eselect Time ns t HH t H Active Hold Time ns t HL Not Active Hold Time ns t H t LH lock High Time ns t L t LL lock Low Time ns 2 t LH t R lock Rise Time µs 2 t HL t F lock Fall Time µs t VH t U ata In etup Time ns t HX t H ata In Hold Time ns 2 t LH t RI ata In Rise Time µs 2 t HL t FI ata In Fall Time µs t HHH t lock Low Hold Time after HOL not Active ns t HLH t LHL t LHH lock Low Hold Time after HOL Active lock Low et-up Time before HOL Active lock Low et-up Time before HOL not Active ns ns ns t HZ 2 t I Output isable Time ns t LV t V lock Low to Output Valid ns t LX t HO Output Hold Time ns t LH 2 t RO Output Rise Time ns t HL 2 t FO Output Fall Time ns t HHX 2 t LZ HOL High to Output Low-Z ns t HLZ 2 t HZ HOL Low to Output High-Z ns t W t W Write Time ms Note:. t H + t L / f. 2. Value guaranteed by characterization, not 00% tested in production. 3/2

14 Table 2. A Measurement onditions Input Rise and Fall Times 50 ns Input Pulse Voltages 0.2V to 0.8V Figure 2. A Testing Input Output Waveforms 0.8V 0.7V Input and Output Timing Reference Voltages Output Load 0.3V to 0.7V L = 00 pf Note:. Output Hi-Z is defined as the point where data is no longer driven. 0.2V 0.3V AI00825 Figure 3. erial Input Timing thl thl tlh thh thh tvh thl thx tlh MB IN LB IN HIGH IMPEANE tlh thl AI0447 Figure 4. Hold Timing thlh tlhl thhh tlhh thlz thhx HOL AI0448 4/2

15 Figure 5. Output Timing th tlv tl thz tlx LB OUT tlh thl AR.LB IN AI0449 ORERING INFORMATION The notation used for the device number is as shown in Table 3. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest T ales Office. Table 3. Ordering Information cheme Example: M95640 W MN 6 T Memory apacity 4 Option Kbit (8K x 8) with positive clock strobe T Tape and Reel Packing Kbit (4K x 8) with positive clock strobe 60 6 Kbit (2K x 8) with positive clock strobe Temperature Range Kbit (K x 8) with positive clock strobe 0 to to to 85 Operating Voltage to 25 blank 4.5 V to 5.5 V V 2.7 V to 5.5 V Package W 2.5 V to 5.5 V BN PIP8 (0.25 mm frame) R 3.8 V to 3.6 V MN O8 (50 mil width) L 5 TOP4 (69 mil width) W 6 TOP8 (69 mil width) Note:. Temperature range available only on request. 2. Produced with High Reliability ertified Flow (HRF), in V range 4.5 V to 5.5 V only. 3. The -R version (V range.8 V to 3.6 V) only available in temperature ranges 5 or. 4. All devices use a positive clock strobe: ata In is strobed on the rising edge of the clock () and ata Out is synchronised from the falling edge of the clock. 5. TOP4, 69 mil width, package is available for the M95640 series only. 6. Not available on all products. Please contact your T ales Office for further information. 5/2

16 Table 4. PIP8-8 pin Plastic kinny IP, 0.25mm lead frame ymb. mm inches Typ. Min. Max. Typ. Min. Max. A A A B B E E e ea eb L N 8 8 Figure 6. PIP8 (BN) A A2 A L B B e ea eb N E E PIP-a Note:. rawing is not to scale. 6/2

17 Table 5. O8-8 lead Plastic mall Outline, 50 mils body width mm inches ymb. Typ. Min. Max. Typ. Min. Max. A A B E e H h L α N 8 8 P Figure 7. O8 narrow (MN) h x 45 B e A P N E H A α L O-a Note:. rawing is not to scale. 7/2

18 Table 6. TOP8-8 lead Thin hrink mall Outline mm inches ymb. Typ. Min. Max. Typ. Min. Max. A A A B E E e L α N 8 8 P Figure 8. TOP8 (W) N IE E E N/2 α A A2 A L P B e TOP Note:. rawing is not to scale. 8/2

19 Table 7. TOP4-4 lead Thin hrink mall Outline mm inches ymb. Typ. Min. Max. Typ. Min. Max. A A A B E E e L α N 4 4 P Figure 9. TOP4 (L) N IE E E N/2 α A A2 A L P B e TOP Note:. rawing is not to scale. 9/2

20 Table 8. Revision History ate escription of Revision 3-Jul-2000 Human Body Model meets JEE std (Table 2). Minor adjustments on pp,,5. New clause on p7. Addition of TOP8 package on pp, 2, Ordering Info, Mechanical ata 20/2

21 Information furnished is believed to be accurate and reliable. However, TMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TMicroelectronics. pecifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. TMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of TMicroelectronics TMicroelectronics - All Rights Reserved The T logo is a registered trademark of TMicroelectronics. All other names are the property of their respective owners. TMicroelectronics GROUP OF OMPANIE Australia - Brazil - hina - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - ingapore - pain - weden - witzerland - United Kingdom - U..A. 2/2