M25P10 1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface

Transcription

1 1 Mbit Low Voltage Paged Flash Memory With 2 MHz erial PI Bus Interface PRELIMINARY ATA 1 Mbit PAGE Flash Memory 128 BYTE PAGE PROGRAM IN 3 ms TYPIAL 256 Kbit ETOR ERAE IN 1 s TYPIAL BULK ERAE IN 2 s TYPIAL INGLE 2.7 V to 3.6 V UPPLY VOLTAGE PI BU OMPATIBLE ERIAL INTERFAE 2 MHz LOK RATE AVAILABLE UPPORT POITIVE LOK PI MOE EEP POWER OWN MOE (1 µa TYPIAL) ELETRONI IGNATURE 1, ERAE/PROG YLE PER ETOR 2 YEAR ATA RETENTION 4 TO 85 TEMPERATURE RANGE ERIPTION The M25P1 is an 1 Mbit Paged Flash Memory fabricated with TMicroelectronics High Endurance MO technology. The memory is accessed by a simple PI bus compatible serial interface. The bus signals are a serial clock input (), a serial data input () and a serial data output (). The device connected to the bus is selected when the chip select input () goes low. ata is clocked in during the low to high transition of clock, data 8 O8 (MN) 15 mil width 8 Figure 1. Logic iagram V 1 1 O8 (MW) 2 mil width Table 1. ignal Names erial lock erial ata Input M25P1 W erial ata Output hip elect Write Protect W HOL HOL Hold V upply Voltage V AI3744 V Ground June 2 This is preliminary information on a new product now in development or undergoing evaluation. etails are subject to change without notice. 1/21

2 Figure 2. O onnections W V M25P AI3745 is clocked out during the high to low transition of clock IGNAL ERIPTION erial Output () The output pin is used to transfer data serially out of the memory. ata is shifted out on the falling edge of the serial clock. erial Input () The input pin is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Input is latched on the rising edge of the serial clock. erial lock () The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the pin changes after the falling edge of the clock input V HOL hip elect () When is high, the memory is deselected and the output pin is at high impedance and, unless an internal Read, Program, Erase or Write tatus Register operation is underway, the device will be in the tandby Power mode (this is not the eep Power own mode). low enables the memory, placing it in the active power mode. It should be noted that after power-on, a high to low transition on is required prior to the start of any operation. Hold (HOL) The HOL pin is used to pause serial communications with a PI memory without resetting the serial sequence. To take the Hold condition into account, the product must be selected. The HOL condition is validated by a state on the Hold pin synchronized with the state on the lock, as shown in Figure 4. The ehol condition is validated by a 1 state on the Hold pin synchronized with the state on the lock. uring the Hold condition,, and are at a high impedance state. When the memory is under HOL condition, it is possible to deselect the device. Then, the protocol is reset. The memory remains on HOL as long as the Hold pin is Low. To restart communication with the device, it is necessary to both ehol (H = 1) and to ELET the memory. Write Protect (W) This pin is for hardware write protection of the tatus Register (R); except WIP and WEL bits. When bit 7 (RW) of the status register is (the initial delivery state); it is possible to write the R once the WEL (Write Enable Latch) has been set with the WREN instruction and whatever is the status of pin W (high or low). Table 2. Absolute Maximum Ratings 1 ymbol Parameter Value Unit T A Ambient Operating Temperature 4 to 85 T TG torage Temperature 65 to 15 T LEA Lead Temperature during oldering O8: 4 seconds 215 V IO Input and Output Voltage Range (with respect to Ground).3 to 5. V V upply Voltage Range.6 to 5. V V E Electrostatic ischarge Voltage (Human Body model) 2 2 V Note: 1. Except for the rating Ambient Operating Temperature Range, stresses above those listed in this table may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the T URE Program and other relevant quality documents. 2. MIL-T-883, (1 pf, 15 Ω) 2/21

3 Figure 3. Microcontroller and Memory evices on the PI Bus PI Interface with (POL, PHA) = ('', '') or ('1', '1') O I K Master (T6, T7, T9, T1, Others) M25P1 M25P1 M25P AI3746 Once bit 7 (RW) of the status register has been set to 1, the possibility to rewrite the R depends on the logical level present at pin W: If W pin is high, it will be possible to rewrite the status register after having set the WEL (Write Enable Latch). If W pin is low, any attempt to modify the status register will be ignored by the device even if the WEL was set. As a consequence: all the data bytes in the memory area software protected (PM) by the BPi bits of the status register are also hardware protected against data modification and can be seen as a Read Only memory area. This mode is called the Hardware Protected Mode (HPM). It is possible to enter the Hardware Protected Mode (HPM) by setting RW bit after pulling down the W pin or by pulling down the W pin after setting RW bit. The only way to abort the Hardware Protected Mode once entered is to pull high the W pin. If W pin is permanently tied to high level, the Hardware Protected Mode will never be activated and the memory will only allow the user to software protect a part of the memory with the BPi bits of the status register. All protection features of the device are summarized in Table 3. Figure 4. Hold ondition Activation LOK HOL PIN MEMORY TATU ATIVE HOL ATIVE HOL ATIVE AI229B 3/21

4 Figure 5. M25P1-ompatible PI Modes POL PHA 1 1 or MB LB AI1438 lock Polarity (POL) and lock Phase (PHA) with PI Bus As shown in Figure 5, the M25P1 can be driven by a microcontroller with its PI peripheral running in either of the two following modes: (POL, PHA) = (, ) or (POL, PHA) = ( 1, 1 ). For these two modes, input data is latched in by the low to high transition of clock, and output data is available from the high to low transition of lock ().The difference between (POL, PHA) = (, ) and (POL, PHA) = (1, 1) is the clock polarity when in stand-by: remains at for (POL, PHA) = (, ) and remains at 1 for (POL, PHA) = (1, 1) when there is no data transfer. MEMORY ORGANIZATION The memory is organized in 131,72 words of 8 bits each. The device features 1,24 pages of 128 bytes each. Each page can be individually programmed (bits are programmed from 1 to state). The device is also organized in 4 sectors of 262,144 bits (32,768 x 8 bits) each.the device is ector or Bulk Erasable but not Page Erasable (bits are erased from to 1 state). OPERATION All instructions, addresses and data are shifted in and out of the chip MB first. ata input () is sampled on the first rising edge of clock () after the chip select () goes low. Prior to any Table 4. Memory Organization ector Address Range 3 18h 1FFFFh 2 1h 17FFFh 1 8h FFFFh h 7FFFh Table 3. Protection Features W RW tatus Register (R) ata Bytes (oftware Protected Area by BPi bits) Mode ata Bytes (Unprotected Area) X Writeable after setting WEL oftware protected by the BPi bits of the tatus Register PM Paged Programmable and ector Erasable 1 1 Writeable after setting WEL oftware protected by the BPi bits of the tatus Register PM Paged Programmable and ector Erasable 1 Hardware protected Hardware protected by the BPi bits of the tatus Register and the W pin Note: 1. PM: oftware Protected Mode. 2. HPM: Hardware Protected Mode. 3. BPi: Bits BP and BP1 of the tatus Register. 4. WEL: Write Enable Latch of the tatus Register. 5. W: Write Protect Input Pin. 6. RW: tatus Register Write isable Bits of the tatus Register. 7. The device is Bulk Erasable if, and only if, (BP, BP1) = (, ), (see Bulk Erase paragraph). HPM Paged Programmable and ector Erasable 4/21

5 Figure 6. Block iagram HOL W ontrol Logic High Voltage Generator I/O hift Register Address Register and ounter ata Register tatus 1FF8h 1FFFFh ize of the Read only Memory area Y ecoder An An + 7Fh 128 Bytes h 7Fh X ecoder AI3747 Table 5. Protected Area izes BP1 BP oftware Protected Area none 1 Upper quarter = ector 3 1 Upper half = ectors 2 & Whole memory= ectors, 1, 2 & 3 5/21

6 Table 6. Instruction et Instruc tion escription Instruction Format WREN et Write Enable Latch 11 WRI Reset Write Enable Latch 1 RR Read tatus Register 11 WRR Write tatus Register 1 REA Read ata from Memory Array 11 PP E Program up to 128 ata bytes to Memory Array ector Erase (set to FFh) one sector of Memory Array BE Bulk Erase (set to FFh) whole of Memory Array P Enter eep Power-down mode RE Release from eep Powerdown mode, and Read Electronic ignature operation, a one-byte instruction code must be sent to the chip. This code is entered via the data input (), and latched on the rising edge of the clock input (). To enter an instruction code, the device must have been previously selected ( = low). Table 6 shows the available instruction set. At Power-up and Power-down, the device must not be selected (that is the input must follow the voltage applied on the V pin) until the supply voltage reaches the correct V values which are V (min) at Power-up and V at Power-down (a simple pull-up resistor on insures safe and proper power up and down phases). Read ata Byte(s) (REA) The device is first selected by putting low. The Read instruction byte is followed by a three bytes address (A23-A), each bit being latched-in during the rising edge of the clock (). Then the data stored in the memory at the selected byte address is shifted out on the output pin, each bit being shifted out during the falling edge of the clock (). The first byte addressed can be any byte within a page. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can therefore be read with a single Read instruction. When the highest address is reached, the address counter rolls over to h allowing the read cycle to be continued indefinitely. The Read operation is terminated by deselecting the chip. The chip can be deselected at any time during data output. Any read attempt during an Erase, Program or Write tatus Register cycle will be rejected and will deselect the chip without having any effects on the ongoing operation. The timing sequence is shown in Figure 11. Page Program (PP) Prior to any Page Program attempt, a write enable instruction (WREN) must have been previously sent (the input driven low, WREN instruction properly transmitted and the input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows the execution of any further Page Program instruction. The Page Program instruction is entered by driving the hip select input () low, followed by the instruction byte, 3 address bytes and at least 1 data byte on ata In input (). If the least significant address bits differ from [A6- A]=., all transmitted data exceeding the addressed page boundary will roll over and will be programmed from address [A6-A]=. of this same page. The hip elect input () must be driven low for the entire duration of the sequence. Figure 7. WREN: et Write Enable Latch equence INTRUTION HIGH IMPEANE AI2281B 6/21

7 Figure 8. WRI: Reset Write Enable Latch equence INTRUTION HIGH IMPEANE AI375 If more than 128 bytes are sent to the device, previously latched data are discarded and the last 128 data bytes are guaranteed to be programmed correctly within the same page. If less than 128 ata bytes are sent to device; they are correctly programmed at the requested addresses without having any effects on the other bytes of the same Page. The device must be deselected just after the eighth bit of the last data byte has been latched in. If not, the Page Program instruction is not executed. As soon as the device is deselected, the self-timed Page Program cycle (t PP ) is initiated. While the Page Program cycle is in progress, the status register may be read to check the WIP bit value. WIP is high during the self-timed Page Program cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. A Page Program instruction applied to a Page which is software protected by the BPi bits (see Table 4 and Table 5) is not initiated. The timing sequence is shown in Figure 12. Write Enable (WREN) and Write isable (WRI) The Write Enable Latch must be set prior to every Page Program (PP), ector Erase (E), Bulk Erase (BE) and Write tatus Register (WRR) operation. The WREN instruction, whose timing sequence is shown in Figure 7, will set the latch and the WRI instruction, whose timing sequence is shown in Figure 8, will reset the latch. The Write Enable Latch is reset under the following conditions: Power on WRI instruction completion WRR instruction completion Page Program instruction completion ector Erase instruction completion Bulk Erase instruction completion. After completion of either WREN or WRI instruction, the chip enters a wait state and waits for a deselect. Figure 9. RR: Read tatus Register equence INTRUTION TATU REG. OUT HIGH IMPEANE MB TATU REG. OUT MB 7 MB AI231 7/21

8 Figure 1. WRR: Write tatus Register equence INTRUTION TATU REG. HIGH IMPEANE MB AI2282 Read tatus Register (RR) The RR instruction provides access to the tatus Register content. The tatus Register may be read at any time, even during a Page Program, ector Erase, Bulk Erase or Write tatus Register. When one of these instructions is in progress, it is recommended to check the WIP bit before sending a new instruction to the device. For this, it is possible to continuously read the tatus Register value. WIP bit: The Write-In-Process (WIP) bit indicates whether the memory is busy with a Write tatus Register, Program or Erase operation. When set to a 1, such an operation is in progress, when set to a no such operation is in progress. WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to a 1 the latch is set, when set to a the latch is reset and no Write tatus Register, Program or Erase sequence will be allowed. BP1,BP bits: The Block Protect bits BPi are nonvolatile bits. They define the size of the area to be software protected against Program and Erase operations. These bits are written with the WRR instruction (see Table 5). Once (BP, BP1) are set to a value different from (,), the relevant area becomes protected against Page Program and ector Erase operations. BPi bits can be written provided that the Hardware Protected Mode has not been set. The Bulk Erase instruction is Figure 11. REA: Read ata Bytes equence INTRUTION 24 BIT ARE HIGH IMPEANE ATA OUT MB AI3748 Note: 1. Address bits A23 to A17 are on t are on the M25P1 series. 8/21

9 Table 7. tatus Register Format b7 RW BP1 BP WEL WIP Note: 1. RW, BP and BP1 are non-volatile read and write bits. 2. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device). internally taken into account if, and only if, (BP, BP1) = (,). RW bit: The RW bit operates together with the W pin. RW bit and W pin allow the part to be put in the Hardware protected mode. In this mode (W pin = and RW = 1), the non-volatile bits of the tatus Register (RW, BP1, BP) become read only bits and the Write tatus Register (WRR) instruction has no more effect on the device (please see the section entitled Write Protect (W) on page 2, and Table 3). Write in the tatus Register (WRR) Prior to any WRR instruction, a write enable instruction (WREN) must have been previously sent (the input driven low, WREN instruction properly transmitted and the input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows b the execution of any further WRR instruction. The WRR instruction is entered by driving the hip select input () low, followed by the instruction byte and the data byte on ata In input (). WRR instruction has no effect on b6, b5, b4, b1 and b of the tatus Register. b6, b5 and b4 are always read at. The device must be deselected just after the eighth bit of the data byte has been latched in. If not, the WRR instruction is not executed. As soon as the device is deselected, the self-timed Write tatus Register cycle (t W ) is initiated. While the Write tatus Register cycle is in progress, the tatus Register may still be read to check the WIP bit value. WIP is high during the self-timed Write tatus Register cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The WRR instruction allows the user to define the size of the software Protected area (Read Only) when setting the BP1,BP values, according to Table 4. The WRR instruction also allows the user to set or reset the RW bit in accordance with the W pin. RW bit and W pin allow the part to be put in the Hardware protected mode (please see the sections entitled Read tatus Register (RR) on page 8, Write Protect (W) on page 2, and Table 3). WRR instruction has no effect on Figure 12. PP: Page Program equence INTRUTION 24 BIT ARE ATA BYTE ATA BYTE 2 ATA BYTE 3 ATA BYTE AI3749 Note: 1. Address bits A23 to A17 are on t are on the M25P1 series. 9/21

10 Figure 13. E: ector Erase equence INTRUTION 24 BIT ARE MB AI3751 Note: 1. Address bits A23 to A17 are on t are on the M25P1 series. the device once the Hardware Protected Mode is entered. The timing sequence is shown in Figure 1. ector Erase (E) Prior to any ector Erase attempt, a write enable instruction (WREN) must have been previously sent (the input driven low, WREN instruction properly transmitted and the input driven high). After the WREN instruction decoding, the memory sets the Write Enable Latch (WEL) which allows the execution of any further ector Erase. The ector Erase instruction is entered by driving the hip select input () low, followed by the instruction byte and 3 address bytes on ata In input (). Any address of the ector (see Table 4) is a valid address for the ector Erase instruction. The hip elect input () must be driven low for the entire duration of the sequence. The device must be deselected just after the eighth bit of the last address byte has been latched in. If not, the ector Erase instruction is not executed. As soon as the device is deselected, the self-timed ector Erase cycle (t E ) is initiated. While the ector Erase cycle is in progress, the status register may be read to check the WIP bit value. WIP is high during the self-timed ector Erase cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. A ector Erase instruction applied to a ector which is software protected by the BPi bits (see Table 4 and Table 5) is not initiated. The timing sequence is shown in Figure 13. Bulk Erase (BE) Prior to any Bulk Erase attempt, a write enable instruction (WREN) must have been previously sent (the input driven low, WREN instruction properly transmitted and the input driven high). After the WREN instruction decoding, the memory Figure 14. BE: Bulk Erase equence INTRUTION AI3752 1/21

11 Figure 15. P: Enter eep Power own Mode equence tp INTRUTION tand-by Power own Mode eep Power own Mode AI3753 sets the Write Enable Latch (WEL) which allows the execution of any further Bulk Erase. The Bulk Erase instruction is entered by driving the hip select input () low, followed by the instruction byte on ata In input (). The hip elect input () must be driven low for the entire duration of the sequence. The device must be deselected just after the eighth bit of the instruction byte has been latched in. If not, the Bulk Erase instruction is not executed. As soon as the device is deselected, the self-timed Bulk Erase cycle (t BE ) is initiated. While the Bulk Erase cycle is in progress, the status register may be read to check the WIP bit value. WIP is high during the self-timed Bulk Erase cycle and is low when it is completed. When the cycle is completed, the write enable latch (WEL) is reset. The Bulk Erase instruction is internally taken into account if, and only if, (BP, BP1) = (,). In other words, the Bulk Erase instruction is ignored if at least one ector is software protected. In this case the Bulk Erase instruction is discarded and none of the ectors are erased. The timing sequence is shown in Figure 14. Enter eep Power own Mode (P) After Power-on, when is high, the memory is deselected, the output pin is at high impedance and the device is in the tandby Power Mode state (I 1 ). Under this state, the Memory waits for a select condition and is able to receive, decode and execute all instructions.this mode is not the eep Power own Mode which is entered by the way of a specific instruction. The purpose of the eep Power down mode is to drastically reduce the standby current from I 1 to I 2 (see Table 1). Once the device has entered the eep Power own Mode, all instructions are ignored except the RE instruction which releases the part from this Figure 16. RE: Release from eep Power own Mode and Read Electronic ignature equence INTRUTION 24 BIT ARE HIGH IMPEANE ATA OUT (Electronic ignature) MB eep Power own Mode tand-by Power own Mode AI /21

12 Figure 17. RE: Release from eep Power own Mode equence tre INTRUTION HIGH IMPEANE eep Power own Mode tand-by Power own Mode AI3754 mode. At the same time, the RE instruction provides the Electronic ignature of the device on the output pin. At power down, the eep own Mode is automatically discarded. This causes the device to always wake up in the tandby Power Mode state after power-on. The P instruction is entered by driving the hip select input () low, followed by the instruction byte on ata In input (). The hip elect input () must be driven low for the entire duration of the sequence. The device must be deselected just after the eighth bit of the instruction byte has been latched in. If not, the P instruction is not executed. As soon as the device is deselected, it requires t P to enter the eep Power own Mode where standby current is reduced to I 2. The timing sequence is shown in Figure 15. Release from eep Power own Mode and Read Electronic ignature (RE) Once the device has entered the eep Power own Mode, all instructions are ignored except the RE instruction which releases the part from this mode. At the same time, the RE instruction provides the Electronic ignature of the device on the output pin. Except during an Erase, Program cycle or Write tatus register, the RE instruction always provides access to the Electronic ignature of the device and can be applied even if the eep Power own Mode has not been entered. Any RE attempt during an Erase, Program cycle or Write tatus register, will be rejected and will deselect the chip without having any effects on the ongoing Erase, Program cycle or Write tatus Register. The device is first selected by putting low. The RE instruction byte is followed by a dummy three bytes address (A23-A), each bit being latched-in on ata In input () during the rising edge of the clock (). Then, the Electronic ignature stored in the memory is shifted out on the output pin, each bit being shifted out during the falling edge of the clock (). It is possible to continuously read the Electronic ignature value. The RE operation is terminated by deselecting the chip after the Electronic ignature has been read at least one time (see Figure 16). At this step, the device is immediately put again in the tandby Power Mode state. It waits for a select condition and is able to receive, decode and execute all instructions. eselecting the device after the 8 bits RE instruction has been sent but before the LB of the Electronic ignature has been read, will insure the eep Power own Mode to be released but will generate a delay (t RE ) before the device is put in tandby Power Mode state (see Figure 17) and must remain high for at least t RE max value (see Table 13). POWER ON TATE At Power-up, the device must not be selected (that is the input must follow the voltage supplied on the V pin) until the supply voltage reaches the minimum V value (2.7 V). Once V has reached the minimum operating voltage (2.7 V), the hip elect input pin () must remain high for a time higher than t VL min (ee Table 8). After a Power up, the memory is in the following state: 12/21

13 Table 8. Power-Up Timing and V WI Threshold (T A = 4 to 85 ) ymbol Parameter Test ondition Min. Max. Unit I VL 1 V (min) to low 1 µs I PUW 1 Time delay to Write operation 15 ms V WI 1 Write Inhibit Voltage V Note: 1. These parameters are characterized only. The device is in the low power standby state (not the eep Power own Mode). The chip is deselected. The Write Enable Latch is reset. POWER UP OPERATION In order to prevent data corruption and inadvertent Page Program, Erase or Write tatus Register operations, an internal V comparator inhibits all these features if the V voltage is lower than V WI (see Table 8). Once the voltage applied on the V pin goes over the V WI threshold (V >V WI ): Page Program, Erase and Write tatus Register operations are allowed after a time-out of t PUW, as specified in Table 8. This time-out delay allows the voltage applied on V pin to reach V (min) of the device. It should be noted that none of the device's operation are guaranteed till V is not V (min). Table 9. Initial tatus Register Format b7 tatus Register content is h (all tatus Register bits are ). b ATA PROTETION AN PROTOOL ONTROL Once all bits of a Page Program, ector Erase, Bulk Erase or tatus Register Write instruction are received; the input must be driven high (eselect) right after the proper clock count in order to execute the instruction, that is the hip elect must driven high after a clock pulses count multiple of 8 bit. Attempting to access the memory array during a Write, Program or Erase cycle is ignored, however the internal cycle continues. ELETRONI IGNATURE The device features an 8 bits Electronic ignature (1h) which can be read with the help of the RE instruction (please see the section entitled Release from eep Power own Mode and Read Electronic ignature (RE) on page 12). INITIAL ELIVERY TATE The device is delivered with the memory array erased: all bits are set at 1 (each byte = FFh). The 13/21

14 Table 1. haracteristics (T A = 4 to 85 ; V = 2.7 to 3.6 V) ymbol Parameter Test ondition Min. Max. Unit I LI Input Leakage urrent ± 2 µa I LO Output Leakage urrent ± 2 µa I 1 tand-by mode urrent = V, V IN = V or V 5 µa I 2 eep Power own urrent = V, V IN = V or V 5 µa I 3 Operating urrent (REA) =.1V /.9.V at 2 MHz, = open 3 ma I 4 Operating urrent (PP) = V 15 ma I 5 Operating urrent (WRR) = V 15 ma I 6 Operating urrent (E) = V 15 ma I 7 Operating urrent (BE) = V 15 ma V IL Input Low Voltage.6.3V V V IH Input High Voltage.7V V +1 V V OL Output Low Voltage I OL = 1.6 ma.4 V V OH Output High Voltage I OH = 1 µa V.2 V Table 11. Input Parameters 1 (T A = 25, f = 2 MHz) ymbol Parameter Test ondition Min. Max. Unit OUT Output apacitance () 8 pf IN Input apacitance (other pins) 6 pf Note: 1. ampled only, not 1% tested. Table 12. A Measurement onditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 5ns.2V to.8v.3v to.7v Output Load L = 3 pf Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 18. A Testing Input Output Waveforms.8V.7V.3V.2V AI825 14/21

15 Table 13. A haracteristics ymbol Alt. Parameter M25P1 V =2.7 to 3.6 V T A = 4 to 85 Unit Min Max f f lock Frequency.. 2 MHz t LH t Active etup Time (relative to ) 1 ns t HL Not Active Hold Time (relative to ) 1 ns t H 1 t LH lock High Time 22 ns t L 1 t LL lock Low Time 22 ns t VH t U ata In etup Time 5 ns t HX t H ata In Hold Time 5 ns t HH Active Hold Time (relative to ) 1 ns t HH Not Active etup Time (relative to ) 1 ns t HL t H eselect Time 5 ns t HZ 2 t I Output isable Time 2 ns t LV t V lock Low to Output Valid 2 ns t LX t HO Output Hold Time ns t HLH HOL etup Time (relative to ) 1 ns t HHH HOL Hold Time (relative to ) 1 ns t HHH HOL etup Time (relative to ) 1 ns t HHL HOL Hold Time (relative to ) 1 ns t HHX 2 t LZ HOL to Output Low-Z 2 ns t HLZ 2 t HZ HOL to Output High-Z 2 ns t P 2 High to eep Power own Mode 1.6 µs t RE 2 High to tand-by Power Mode 1.6 µs t W Write tatus Register ycle Time 5 ms t PP Page Program ycle Time 5 ms t E ector Erase ycle Time 2 s t BE Bulk Erase ycle Time 4 s Note: 1. t H + t L 1 / f. 2. Value guaranteed by characterization, not 1% tested in production. These parameters are specified with an output load capacitance of 3 pf. 15/21

16 Figure 19. erial Input Timing thl thl tlh thh thh tvh thl thx tlh MB IN LB IN HIGH IMPEANE tlh thl AI1447 Figure 2. Hold Timing thlh thhl thhh thhh thlz thhx HOL AI232 Figure 21. Output Timing th tlv tl thz tlx LB OUT tlh thl AR.LB IN AI1449B 16/21

17 Table 14. Ordering Information cheme Example: M25P1 V MW 6 T Memory apacity Option 1 1 Mbit (128K x 8) T Tape and Reel Packing Temperature Range 6 4 to 85 Operating Voltage Package V 2.7 V to 3.6 V MN O8 (15 mil width) MW O8 (2 mil width) ORERING INFORMATION The notation used for the device number is as shown in Table 14. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest T ales Office. 17/21

18 Table 15. O8-8 lead Plastic mall Outline, 15 mils body width mm inches ymb. Typ. Min. Max. Typ. Min. Max. A A B E e H h L α 8 8 N 8 8 P.1.4 Figure 22. O8 narrow (MN) h x 45 B e A P N 1 E H A1 α L O-a Note: 1. rawing is not to scale. 18/21

19 Table 16. O8-8 lead Plastic mall Outline, 2 mils body width mm inches ymb. Typ. Min. Max. Typ. Min. Max. A A A B E e H L α 1 1 N 8 8 P.1.4 Figure 23. O8 wide (MW) A2 A B e P N E H 1 A1 α L O-b Note: 1. rawing is not to scale. 19/21

20 Table 17. Revision History ate 24-Feb-2 3-May-2 escription of Revision ocument reformatted in preparation for full release; no parameters changed except data retention, which has been changed to 2 years. Title changed from Paged Non-Volatile Memory to Paged Flash Memory 2/21

21 Information furnished is believed to be accurate and reliable. However, TMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TMicroelectronics. pecifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. TMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of TMicroelectronics. 2 TMicroelectronics - All Rights Reserved The T logo is a registered trademark of TMicroelectronics. All other names are the property of their respective owners. TMicroelectronics GROUP OF OMPANIE Australia - Brazil - hina - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - ingapore - pain - weden - witzerland - United Kingdom - U..A. 21/21

22 Mouser Electronics Authorized istributor lick to View Pricing, Inventory, elivery & Lifecycle Information: TMicroelectronics: M25PE1-VMN6P M25P1-VMN6