Computer Systems. Fifth edition Documentation for Exam Handouts. J. Stanley Warford

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1 Computer Systems Fifth edition Documentation for Exam Handouts J. Stanley Warford March 22, 2016

2 Instruction set Instruction Mnemonic Instruction ddressing Status Specifier Mode Bits STOP Stop execution U RET Return from CLL U RETTR Return from trap U MOVSP Move SP to U MOVFLG Move NZVC flags to U MOVFLG Move to NZVC flags U r NOTr Bitwise invert r U NZ r NEGr Negate r U NZV r SLr rithmetic shift left r U NZVC r SRr rithmetic shift right r U NZC r ROLr Rotate left r U C r RORr Rotate right r U C a BR Branch unconditional i, x a BRLE Branch if less than or equal to i, x a BRLT Branch if less than i, x a BREQ Branch if equal to i, x a BRNE Branch if not equal to i, x a BRGE Branch if greater than or equal to i, x a BRGT Branch if greater than i, x a BRV Branch if V i, x a BRC Branch if C i, x a CLL Call subroutine i, x n NOPn Unary no operation trap U aaa NOP Nonunary no operation trap i aaa DECI Decimal input trap d, n, s, sf, x, sx, sfx NZV aaa DECO Decimal output trap i, d, n, s, sf, x, sx, sfx aaa HEXO Hexadecimal output trap i, d, n, s, sf, x, sx, sfx aaa STRO String output trap d, n, sf, x aaa DDSP dd to stack pointer (SP) i, d, n, s, sf, x, sx, sfx NZVC aaa SUBSP Subtract from stack pointer (SP) i, d, n, s, sf, x, sx, sfx NZVC 0110 raaa DDr dd to r i, d, n, s, sf, x, sx, sfx NZVC 0111 raaa SUBr Subtract from r i, d, n, s, sf, x, sx, sfx NZVC 1000 raaa NDr Bitwise ND to r i, d, n, s, sf, x, sx, sfx NZ 1001 raaa ORr Bitwise OR to r i, d, n, s, sf, x, sx, sfx NZ 1010 raaa CPWr Compare word to r i, d, n, s, sf, x, sx, sfx NZVC 1011 raaa CPBr Compare byte to r 8..1 i, d, n, s, sf, x, sx, sfx NZVC 1100 raaa LDWr Load word r from memory i, d, n, s, sf, x, sx, sfx NZ 1101 raaa LDBr Load byte r 8..1 from memory i, d, n, s, sf, x, sx, sfx NZ 1110 raaa STWr Store word r to memory d, n, s, sf, x, sx, sfx 1111 raaa STBr Store byte r 8..1 to memory d, n, s, sf, x, sx, sfx 1

3 RTL specification of the instruction set Instruction Register transfer language specification STOP Stop execution RET PC Mem[SP] ; SP SP + 2 RETTR NZVC Mem[SP] 4..7 ; Mem[SP + 1] ; X Mem[SP + 3] ; PC Mem[SP + ] ; SP Mem[SP + 7] MOVSP SP MOVFLG , NZVC MOVFLG NZVC NOTr r r ; N r < 0, Z r = 0 NEGr r r ; N r < 0, Z r = 0, V {overflow} SLr C r 0, r r 1..1, r 1 0 ; N r < 0, Z r = 0, V {overflow} SRr C r 1, r 1..1 r ; N r < 0, Z r = 0 ROLr C r 0, r r 1..1, r 1 C RORr C r 1, r 1..1 r 0..14, r 0 C BR BRLE BRLT BREQ BRNE BRGE BRGT BRV BRC CLL NOPn NOP DECI DECO HEXO STRO DDSP SUBSP PC Oprnd N = 1 Z = 1 PC Oprnd N = 1 PC Oprnd Z = 1 PC Oprnd Z = 0 PC Oprnd N = 0 PC Oprnd N = 0 Z = 0 PC Oprnd V = 1 PC Oprnd C = 1 PC Oprnd SP SP 2 ; Mem[SP] PC ; PC Oprnd Trap: Unary no operation Trap: Nonunary no operation Trap: Oprnd {decimal input} Trap: {decimal output} Oprnd Trap: {hexadecimal output} Oprnd Trap: {string output} Oprnd SP SP + Oprnd SP SP Oprnd DDr r r + Oprnd ; N r < 0, Z r = 0, V {overflow}, C {carry} SUBr r r Oprnd ; N r < 0, Z r = 0, V {overflow}, C {carry} NDr r r Oprnd ; N r < 0, Z r = 0 ORr r r Oprnd ; N r < 0, Z r = 0 CPWr T r Oprnd ; N T < 0, Z T = 0, V {overflow}, C {carry} ; N N V CPBr T r 8..1 byte Oprnd ; N T < 0, Z T = 0, V 0, C 0 LDWr r Oprnd ; N r < 0, Z r = 0 LDBr r 8..1 byte Oprnd ; N 0, Z r 8..1 = 0 STWr Oprnd r STBr byte Oprnd r 8..1 Trap T Mem[FFF6] ; Mem[T 1] IR 0..7 ; Mem[T 3] SP ; Mem[T ] PC ; Mem[T 7] X ; Mem[T 9] ; Mem[T 10] 4..7 NZVC ; SP T 10 ; PC Mem[FFFE] 2

4 SCII chart Char Bin Hex Char Bin Hex Char Bin Hex Char Bin Hex NUL SP SOH ! a STX " B b ETX # C c EOT $ D d ENQ % E e CK & F f BEL ' G g BS ( H h HT ) I i LF * J j VT B B K B k B FF C, C L C l C CR D D M D m D SO E E N E n E SI F / F O F o F DLE P p DC Q q DC R r DC S s DC T t NK U u SYN V v ETB W w CN X x EM Y y SUB : Z z ESC B ; B [ B { B FS C < C \ C C GS D = D ] D } D RS E > E ˆ E ~ E US F? F _ F DEL F bbreviations for Control Characters NUL SOH STX ETX EOT ENQ CK BEL BS HT LF VT null, or all zeros start of heading start of text end of text end of transmission enquiry acknowledge bell backspace horizontal tabulation line feed vertical tabulation FF form feed CR carriage return SO shift out SI shift in DLE data link escape DC1 device control 1 DC2 device control 2 DC3 device control 3 DC4 device control 4 NK negative acknowledge SYN synchronous idle ETB end of transmission block CN EM SUB ESC FS GS RS US SP DEL cancel end of medium substitute escape file separator group separator record separator unit separator space delete 3

5 ddressing modes Central processing unit (CPU) Status bits (NZVC) ccumulator () Index register (X) Program counter (PC) Stack pointer (SP) Instruction register (IR) N Z V C Instruction specifier Operand specifier (a) The two parts of a nonunary instruction. Instruction specifier (b) unary instruction. aaa ddressing Mode a ddressing Mode r Register 000 Immediate 001 Direct 010 Indirect 011 Stack-relative 100 Stack-relative deferred 101 Indexed 110 Stack-indexed 111 Stack-deferred indexed (a) The addressing-aaa field. 0 Immediate 1 Indexed (b) The addressing-a field. 0 ccumulator, 1 Index register, X (c) The register-r field. ddressing Mode aaa Letters Operand Immediate 000 i OprndSpec Direct 001 d Mem[OprndSpec] Indirect 010 n Mem[Mem[OprndSpec]] Stack-relative 011 s Mem[SP + OprndSpec] Stack-relative deferred 100 sf Mem[Mem[SP + OprndSpec]] Indexed 101 x Mem[OprndSpec + X] Stack-indexed 110 sx Mem[SP + OprndSpec + X] Stack-deferred indexed 111 sfx Mem[Mem[SP + OprndSpec] + X] 4

6 Memory map The shaded portion is ROM Mem Globals FB8F FC0F FC1 FC16 FC17 FC2 pplication program Heap Run-time stack System stack System globals Input port Output port Loader Trap handler Operating system pplication FFF4 FFF6 FFF8 FFF FFFC FFFE FB8F FC0F FC1 FC16 FC17 FC2

7 rithmetic Logic Unit B 4 Cin Result Cout V Zout N Control Status Bits (bin) (dec) Result N Zout V Cout N Z plus B N Z V C plus B plus Cin N Z V C plus B plus 1 N Z V C plus B plus Cin N Z V C 0101 B N Z B N Z B N Z B N Z B N Z N Z SL N Z V C ROL N Z V C SR N Z 0 C ROR N Z 0 C <4> <> <6> <7> 6

8 CPU data section X 4 SP 6 7 PC CPU registers 8 IR T T2 T3 T4 T T M1 0x00 24 M2 0x02 26 M3 0x04 28 M4 0xF0 30 M 0xFE 23 0x01 2 0x x xF6 31 0xFF LoadCk C B System Bus MRB CBus Bus BBus MRCk MR MDRCk MDR MDRMux Mux Mux MDRMux CMux Cin 4 CMux CSMux CSMux Mem Cout S C SCk CCk ddr V VCk Data Zout ndz Z ndz ZCk N NCk MemWrite MemRead 7

9 CPU data section with two-byte data bus X 4 SP 6 7 PC CPU registers 8 IR T T2 T3 T4 T T M1 0x00 24 M2 0x02 26 M3 0x04 28 M4 0xF0 30 M 0xFE 23 0x01 2 0x x xF6 31 0xFF LoadCk C B System Bus MRB CBus Bus BBus MRMux MRMux MRCk MR MDROCk MDROdd MDROMux MDROMux MDREven MDREMux EOMux MDRECk MDREMux EOMux Mux Mux Mem ddr ddr CMux Cin CSMux 4 CMux CSMux Data Data Cout S C SCk CCk V VCk Zout ndz Z ndz ZCk N NCk MemWrite MemRead 8

10 System bus protocols The memory read bus protocol The bus protocol for a memory read over the Pep/9 system bus requires three consecutive cycles, with MemRead asserted on each cycle. The read operation must adhere to the following specification: You must clock the address into the MR before the first MemRead cycle. You must clock the data into the MDR from the system bus on or before the third MemRead cycle. On the third MemRead cycle, you cannot clock a new value into MR in anticipation of a following memory operation. The memory write bus protocol The bus protocol for a memory write requires three consecutive cycles, with MemWrite asserted on each cycle. The write operation must adhere to the following specification: You must clock the address into the MR before the first MemWrite cycle. On the first or second MemWrite cycle, you can clock the data to be written into the MDR. On the third MemWrite cycle, you can clock a new data value into the MDR in anticipation of a following memory write. However, you cannot clock a new address value into the MR in anticipation of a following memory operation. 9

11 MIPS Registers (a) MIPS registers. (b) Pep/9 registers. 0 0x $zero $at $v0 $v1 $a0 $a1 $a2 $a3 $t0 $t1 $t2 $t3 $t4 $t $t6 $t7 32 X PC SP $s0 $s1 $s2 $s3 $s4 $s $s6 $s7 $t8 $t9 $k1 $k0 $gp $sp $fp $ra 10

12 MIPS ddressing modes ddressing Instruction Operands Mode Type Destination Source Source Immediate I-type Reg[rt] Reg[rs] SE(im) Register R-type Reg[rd] Reg[rs] Reg[rt] Base with load I-type Reg[rt] Mem[Reg[rb] + SE(im)] Base with store I-type Mem[Reg[rb] + SE(im)] Reg[rt] PC-relative I-type PC PC + 4 SE(im 4) Pseudodirect J-type PC (PC + 4) 0..3 : (ta 4) op Opcode rs Source register rt Dest register immediate Immediate (a) Immediate addressing with the I-type instruction. 6 6 op Opcode rs Source register rt Source register (b) Register addressing with the R-type instruction. rd Dest register shamt Shift amount funct Function field 6 16 op Opcode rs Base register rt Target register immediate ddress displacement (c) Base addressing with the I-type instruction op Opcode rs Source register rt Branch cond immediate Branch displacement (d) PC-relative addressing with the I-type instruction. 6 op Opcode 26 target Target address (e) Pseudodirect addressing with the J-type instruction. 11

13 MIPS Instruction set Mnemonic Meaning Binary Instruction Encoding add dd ss ssst tttt dddd d addi dd immediate ss sssd dddd iiii iiii iiii iiii sub Subtract ss ssst tttt dddd d and Bitwise ND ss ssst tttt dddd d andi Bitwise ND immediate ss sssd dddd iiii iiii iiii iiii or Bitwise OR ss ssst tttt dddd d ori Bitwise OR immediate ss sssd dddd iiii iiii iiii iiii sll Shift left logical t tttt dddd dhhh hh sra Shift right arithmetic t tttt dddd dhhh hh srl Shift right logical t tttt dddd dhhh hh lb Load byte bb bbbd dddd aaaa aaaa aaaa aaaa lw Load word bb bbbd dddd aaaa aaaa aaaa aaaa lui Load upper immediate d dddd iiii iiii iiii iiii sb Store byte bb bbbt tttt aaaa aaaa aaaa aaaa sw Store word bb bbbt tttt aaaa aaaa aaaa aaaa beq Branch if equal to ss ssst tttt aaaa aaaa aaaa aaaa bgez bgtz blez bltz bne Branch if greater than or equal to zero ss sss aaaa aaaa aaaa aaaa Branch if greater than zero ss sss aaaa aaaa aaaa aaaa Branch if less than or equal to zero ss sss aaaa aaaa aaaa aaaa Branch if less than zero ss sss aaaa aaaa aaaa aaaa Branch if not equal to ss ssst tttt aaaa aaaa aaaa aaaa j Jump aa aaaa aaaa aaaa aaaa aaaa aaaa jr Jump register bb bbb

14 MIPS CPU data section PC JMux 32 PCMux L1 instruction cache ddress Instruction address SL2 4 Plus4 IF Instruction fetch C Decode instruction Register bank B address 16 Sign extend ID Instruction decode/register file read CBus Bus BBus 32 Mux SL2 Ex Execute/address calculation dder Data in ddress Data out L1 data cache Mem Memory access CMux WB Write back 13

15 MIPS CPU control signals PC PCCk JMux PCMux L1 instruction cache ddress Instruction Decode instruction C B Register bank LoadCk CBus Bus BBus Mux Data in ddress L1 data cache Data out DCCk CMux 14

16 MIPS CPU pipelining PC JMux PCMux L1 instruction cache ddress Instruction Plus4 IF Instruction fetch address SL2 IF/ID registers address C Decode instruction Register bank B Sign extend ID Instruction decode/register file read CBus Bus BBus ID/Ex registers Mux SL2 dder Ex Execute/address calculation Ex/Mem registers Data in ddress L1 data cache Mem Memory access Data out Mem/WB registers CMux WB Write back 1

n NOPn Unary no operation trap U aaa NOP Nonunary no operation trap i

n NOPn Unary no operation trap U aaa NOP Nonunary no operation trap i Instruction set Instruction Mnemonic Instruction Addressing Status Specifier Mode Bits 0000 0000 STOP Stop execution U 0000 0001 RET Return from CALL U 0000 0010 RETTR Return from trap U 0000 0011 MOVSPA