Lecture 4: Review of MIPS. Instruction formats, impl. of control and datapath, pipelined impl.

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1 Lecture 4: Review of MIPS Instruction formats, impl. of control and datapath, pipelined impl. 1

2 MIPS Instruction Types Data transfer: Load and store Integer arithmetic/logic Floating point arithmetic Control instructions (branches and jumps) A few others LW $16, 100($2) LB $17, 200($2) ADDI $8, $16, 17 SLT $10, $8, $9 ADD.D $f0, $f1, $f0 BEQ $0, $1, loop J _fprintf 2

3 MIPS Instruction Format I-type R-type J-type opcode rs rt Immediate/offset opcode rs rt rd shamt funct 6 26 opcode offset opcdoe: 6-bit operation of the instruction rs: first source registers rt: second source register rd: destination register immediate: immediate value or displacment shamt: shift amount funct: function variants offset: offset added to PC for jumps 3

4 Simplified Instruction Set LW/SW Instructions I-type R-type Arithmetic Instructions R-type opcode rs rt offset opcode rs rt rd shamt funct Branch Instructions I-type opcode rs rt offset 4

5 Normal Usage of isters Name ister number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address 5

6 Simple Implementation Available datapath elements Instruction address Instruction PC Add Sum MemWrite Instruction memory a. Instruction memory b. Program counter c. Adder Address Write data Data memory Read data 16 Sign 32 extend ister numbers Data 5 Read 3 register Read register 2 isters Write register Write data Read data 1 Read data 2 Data ALU control Zero ALU ALU result MemRead a. Data memory unit b. Sign-extension unit Write a. isters b. ALU 6

7 Operations in Instruction Execution 1. Fetch the inst at PC; PC incr by 4 2. Decode the inst; Read $a and $b LW $a, 100($b) 3. Add $b and Read memory 5. Wirte $a SW $a, 100($b) 3. Add $b and 100; 4. Write memory ADD $c, $a, $b 3. Add $a and $b 4. Write $c BEQ $a, $b, offset 3. Compare $a and $b 4. If equal, PC<=PC+offset 7

8 Single-cycle Implementation This one supports LW, SW, BEQ, Alu inst e.g. ADD PCSrc 4 Add Write Shift left 2 Add ALU result 1 M u x 0 PC Read address Instruction [31 0] Instruction memory Instruction [25 21] Instruction [20 16] 1 M u Instruction [15 11] x 0 Dst Instruction [15 0] Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 isters 16 Sign 32 extend ALUSrc 1 M u x 0 ALU control Zero ALU ALU result MemWrite Address Write data Data memory MemRead Read data Memto 1 M u x 0 Instruction [5 0] ALUOp 8

9 ularize Instruction Execution LW/SW ALU Branch IF IF IF ID/REG ID/REG ID/REG EX EX EX MEM WB WB -- 9

10 Pipelined Instruction Executions 10

11 Implementation Pipeline registers: Between pipeline stages; separate operations of concurrent instructions IF/ID register: inst ID/EX register ister index: reg_rs, reg_rt, reg_rd Data values: val_a, val_b, imm_value Controls: alusrc, aluop(2), branch, memread, memwrite, memtoreg, regdst, regwrite EX/MEM register: ister index: reg_rs, reg_rt, reg_rd Data values: aluout, val_b Controls: memread, memwrite, memtoreg, regdst, regwrite MEM/WB register ister index: reg_rs, reg_rt, reg_rd Data values: aluout, memout Controls: regdst, regwrite 11

12 Data Dependence and Data Hazards RAW Data Dependence: One instruction writes a register or a memory address, a following instruction reads the register or memory address Can be seen as communication between instructions Two Significant cases for MIPS 5-stage pipeline: CASE I: The first instruction is not a load ADD r16, r8, 100 SUB r17, r17, r16 CASE II: The first instruction is a load LW r16, 0x1004(r28) SUB r17, r17, r16 We consider more types of dependences with dynamical scheduling 12

13 Data Forwarding Time (clock cycles) I n s t r. add r1,r2,r3 sub r4,r1,r3 Ifetch Ifetch ALU DMem ALU DMem O r d e r and r6,r1,r7 or r8,r1,r9 Ifetch Ifetch ALU DMem ALU DMem xor r10,r1,r11 Ifetch ALU DMem Use mostly recent data values to replace obsolete data values Adapted from UCB CS252 S01 13

14 Data Forwarding Implementation Detect forwarding from MEM to EX Compare reg_rs and reg_rt of the inst at EX stage with reg_rd of the inst at MEM stage Detect forwarding from WB to EX Compare reg_rs and reg_rt of the inst at EX stage with reg_rd of the inst at WB stage Replace ALU inputs with forwarding values if forwarding is detected 14

15 Load-use Stall Time (clock cycles) I n s t r. O r d e r lw r1, 0(r2) sub r4,r1,r6 and r6,r1,r7 Ifetch Ifetch ALU Ifetch DMem Bubble Bubble ALU DMem ALU DMem or r8,r1,r9 Bubble Ifetch ALU DMem Why does the pipeline must stall in this RAW case? Adapted from UCB CS252 S01, Copyright 2001 USB 15

16 Load-use Stall Enforcement Detection: Compare reg_rs and reg_rt of inst at ID stage with reg_rt of inst at EX stage Memread of inst at EX stage must be asserted To stall pipeline: Hold instructions at IF and ID Insert a bubble at EX Move forward instructions at MEM and WB 16

17 Branch Hazard and Pipeline Flush Branch output is not available until at ID (with some pipeline changes), but a wrong instruction has been fetched into IF Question: why not suspend fetching instructions on branch instructions? Action: flush instruction at IF whenever a branch is taken How: Write a bubble into IF/ID register 17

18 How Many Wasted Cycles? C = (a+b >= 0)? a+b : 0 Simple rules: LW $16, 0x1000($28) LW $17, 0x1004($29) ADD $18, $16, $17 SLT $19, $0, $18 BEQ $19, $0, SKIP ADD $18, $0, $0 SKIP: SW $18, 0x1008($28) Rule 1: Rule 2: Only valid on simple MIPS 5-stage pipeline 18

19 Deep Pipeline IF1 IF2 ID EX MEM1 MEM2 WB More data forwarding paths More load-use stall detections More flushing for taken branch 19

20 Multi-issue Single-issue Two-way issue IF ID EX IF ID EX IF ID EX MEM WB MEM WB MEM WB Stall check Data forwarding 20

21 80x86 ISA Early History Source: An Alternative to RISC: The Intel 80x86. Appendix D of the textbook. Available at : 16-bit 8086 Extended from 8-bit 8080 Hybrid of accumulator and GRP 1980: 8087 FP coprocessor Add 60 FP instructions to 8086 Hybrid of stack and GRP 1982: address Virtual 24-bit memory management 1985: 32-bit Add new addressing modes, paging support Nearly a GPR machine 21

22 80x86 Integer isters 22

23 Addressing Modes Absolute: 16-bit or 32-bit displacement ister indirect: selected registers EAX, ECX, EDX, EBS, ESI, and EDI Displacement: selected registers or 32-bit offset Indexed: (for 16-bit mode only) Based indexed: reg + reg + 8- or 16-bit disp Base plus scaled indexed: reg + reg*d Base plus scaled index with displacement: reg + reg*d + 8- or 16-bit disp Byte order: little endian 23

24 Instruction Encoding Examples 24

Chapter 4. The Processor. Computer Architecture and IC Design Lab

Chapter 4. The Processor. Computer Architecture and IC Design Lab Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS