Four Views of a Computer. The User s View of a Computer

Transcription

1 Four Views of a Coputer The user ss view The prograer s view The architect s view The hardware designer s view The User s View of a Coputer The user sees for factors, software, speed, storage capacity, and peripheral device functionality. Page 1

2 Ebedded (Coputer) Syste A special purpose coputer syste enclosed or encapsulated within a physical syste Usually the ebedded syste provides the control of the physical syste They are everywhere today: Consuer electronics, counications, entertainent, transportation, health, hoe appliances, etc. 3 Machine/assebly Language Prograer s View Machine language: Set of fundaental instructions ti the achine can execute Expressed as a pattern of 1 s and 0 s Assebly language: Alphanueric equivalent of achine language Mneonics ore huan oriented than 1 s and 0 s Assebler: Coputer progra that transliterates (one-to-one apping) assebly to achine language Coputer s native language is assebly/achine language Prograer, as used in this course, eans assebly/achine language prograer Page 2

3 The Fetch-Execute Cycle Prograer s Model: Instruction Set Architecture (ISA) Instruction set: the collection of all achine operations. Prograer sees set of instructions, along with the achine resources anipulated by the. ISA includes instruction set, eory, and prograer accessible registers of the syste. There ay be teporary or scratch-pad eory used to ipleent soe function is not part of ISA. Non Prograer Accessible. Page 3

4 Fig 1.3 Prograer s Models of 4 coercial achines The Coputer Architect s View Architect is concerned with design & perforance Designs the ISA for optiu prograing utility and optiu perforance of ipleentation Designs the hardware for best ipleentation of the instructions Uses perforance easureent tools, such as benchark progras, to see that goals are et Balances perforance of building blocks such as CPU, eory, I/O devices, and interconnections Meets perforance goals at lowest cost Page 4

5 Fig 1.4 One and Two Bus Architecture Exaples Hardware Designer s View Designs the achine at the RTL/logic gate level The design deterines whether the architect eets cost and perforance goals Architect and hardware designer ay be a single person or tea Page 5

6 Two Views of the CPU PC Register Prograer: 31 0 PC B Bus 32 D 32 A Bus Hardware Designer (Fig 1.8): PC PC out CK PC in Chapter 2: Machines, Machine Languages, and Digital Logic Topics 2.1 Classification of Coputers and Their Instructions 2.2 Coputer Instruction Sets 2.3 Inforal Description of the Siple RISC Coputer, SRC 2.4 Foral Description of SRC Using Register Transfer Notation, RTN 2.5 Describing Addressing Modes with RTN 2.6 Register Transfers and Logic Circuits: Fro Behavior to Hardware Page 6

7 What Are the Coponents of an ISA? Soeties known as The Prograer s Model of the achine Storage cells General and special purpose registers in the CPU Many general purpose cells of sae size in eory Storage associated with I/O devices The achine instruction set The instruction set is the entire repertoire of achine operations Makes use of storage cells, forats, and results of the fetch/execute cycle i.e., register transfers The instruction forat Size and eaning of fields within the instruction Prograer s Models of Various Machines Page 7

8 What Must an Instruction Specify? Data Flow Which operation to perfor add r0, r1, r3 Ans: Op code: add, load, branch, etc. Where to find the operand or operands add r0, r1, r3 In CPU registers, eory cells, I/O locations, or part of instruction Place to store result add r0, r1, r3 Again CPU register or eory cell Location of next instruction ti add r0, r1, r3 br endloop Alost always eory cell pointed to by progra counter PC Instructions Can Be Divided into 3 Classes Data oveent instructions Move data fro a eory location or register to another eory location or register without changing g its for Load source is eory and destination is register Store source is register and destination is eory Arithetic and logic (ALU) instructions Change the for of one or ore operands to produce a result stored in another location Add, Sub, Shift, etc. Branch instructions (control flow instructions) Alter the noral flow of control fro executing the next instruction in sequence Br Loc, Brz Loc2, unconditional or conditional branches Page 8

9 Exaples of Data Moveent Instructions Instruction Meaning Machine MOV A, B Move 16 bits fro eory location A to VAX11 Location B LDA A, Addr Load accuulator A with the byte at eory M6800 location Addr lwz R3, A Move 32-bit data fro eory location A to PPC601 register R3 li $3, 455 Load the 32-bit integer 455 into register $3 MIPS R3000 ov R4, dout Move 16-bit data fro R4 to output t port dout DEC PDP11 IN, AL, KBD Load a byte fro in port KBD to accuulator Intel Pentiu LEA.L (A0), A2 Load the address pointed to by A0 into A2 M6800 Lots of variation, even with one instruction type Exaples of ALU Instructions Instruction Meaning Machine MULF A, B, C ultiply the 32-bit floating point values at VAX11 e loc ns. A and B, store at C nabs r3, r1 Store abs value of r1 in r3 PPC601 ori $2, $1, 255 Store logical OR of reg $ 1 with 255 into reg $2 MIPS R3000 DEC R2 Decreent the 16-bit value stored in reg R2 DEC PDP11 SHL AX, 4 Shift the 16-bit value in reg AX left by 4 bit pos ns. Intel 8086 Notice again the coplete dissiilarity of both syntax and seantics. Page 9

10 Exaples of Branch Instructions Instruction Meaning Machine BLSS A, Tgt Branch to address Tgt if the least significant VAX11 bit of e loc n. A is set (i.e. = 1) bun r2 Branch to location in R2 if result of previous PPC601 floating point coputation was Not a Nuber (NAN) beq $2, $1, 32 Branch to location (PC ) if contents MIPS R3000 of $1 and $2 are equal SOB R4, Loop Decreent R4 and branch to Loop if R4 0 DEC PDP11 JCXZ Addr Jup to Addr if contents of register CX 0. Intel , 2-, 1-, & 0-Address ISAs Classification is based on arithetic instructions that have two operands and one result The key issue is how any of these are specified by eory addresses, as opposed to being specified iplicitly itl A 3-address instruction specifies eory addresses for both operands and the result R Op1 op Op2 A 2-address instruction overwrites one operand in eory with the result Op2 Op1 op Op2 A 1-address instruction has a processor, called the accuulator register, to hold one operand & the result (no addr. needed) Acc Acc op Op1 A 0-address + uses a CPU register stack to hold both operands and the result TOS TOS op SOS (where TOS is Top Of Stack, SOS is Second On Stack) The 4-address instruction, hardly ever seen, also allows the address of the next instruction to specified explicitly Page 10

11 The 4-Address Machine and Instruction Forat Meory CPU add, Res, Op1, Op2, Nexti (Res Op1 + Op2) Op1Addr: Op2Addr: ResAddr: Op1 Op2 Res NextiAddr: Nexti Instruction forat Bits: Explicit addresses for operands, result, & next instruction Exaple assues 24-bit addresses Discuss: size of instruction in bytes add ResAddr Op1Addr Op2Addr NextiAddr Which operation Where to put result Where to find operands Wheretofind next instruction The 3-Address Machine and Instruction Forat Meory CPU add, Res, Op1, Op2 (Res Op2 + Op1) Op1Addr: Op2Addr: ResAddr: Op1 Op2 Res NextiAddr: Nexti Progra counter Wheretofind next instruction 24 Instruction forat Bits: add ResAddr Op1Addr Op2Addr Which operation Where to put result Where to find operands Address of next instruction kept in processor state register the PC (except for explicit branches/jups) Rest of addresses in instruction Discuss: savings in instruction word size Page 11

12 The 2-Address Machine and Instruction Forat Meory CPU add Op2, Op1 (Op2 Op2 + Op1) Op1Addr: Op1 Op2Addr: Op2,Res NextiAddr: Nexti Progra counter Where to find next instruction 24 Instruction forat Bits: add Op2Addr Op1Addr Which Wheretofindoperands operation Where to put result Result overwrites Operand 2 Needs only 2 addresses in instruction but less choice in placing data 1-Address Machine and Instruction Forat Meory CPU add Op1 (Acc Acc + Op1) Op1Addr: Op1 NextiAddr: Nexti Need instructions to load and store operands: LDA OpAddr STA OpAddr Accuulator Progra counter 24 Where to find next instruction Special CPU register, the accuulator, supplies 1 operand and stores result One eory address used for other operand Where to find operand2, and where to put result Instruction forat Bits: 8 24 add Which operation Op1Addr Where to find operand1 Page 12

13 The 0-Address, or Stack, Machine and Instruction Forat Instruction forats Meory CPU push Op1 (TOS Op1) Op1Addr: NextiAddr: Op1 Nexti TOS SOS etc. Stack Progra 24 counter Where to find next instruction Bits: 8 24 Forat push Operation Op1Addr Result add (TOS TOS + SOS) Bits: 8 Forat add Which operation Where tofind operands, and where to put result (on the stack) Uses a push-down stack in CPU Coputer ust have a 1-address instruction to push and pop operands to and fro the stack Exaple 2.1 Expression Evaluation for 3-, 2-, 1-, and 0-Address Machines Evaluate a = (b+c)*d - e 3 - a d d r e s s 2 - a d d r e s s 1 - a d d r e s s S t a c k add a, b, c py a, a, d sub a, a, e load a, b add a, c py a, d sub a, e load b add c py d sub e store a push b push c add push d py push e sub pop a Nuber of instructions & nuber of addresses both vary Discuss as exaples: size of code in each case Page 13

14 General Register Machine and Instruction Forats CPU Meory Registers Instruction forats Op1Addr: Op1 load R8 R6 load R8, Op1 (R8 Op1) load R8 Op1Addr R4 add R2, R4, R6 (R2 R4 + R6) R2 add R2 R4 R6 Nexti Progra counter Most coon choice in today s general-purpose coputers Which register is specified by sall address (3 to 6 bits for 8 to 64 registers) Load and store have one long & one short address: 1½ addresses Arithetic instruction has 3 half addresses Addressing Modes An addressing ode is hardware support for a useful way of deterining a eory address Different addressing odes solve different HLL probles Soe addresses ay be known at copile tie, e.g., global variables Others ay not be known until run tie, e.g., pointers Addresses ay have to be coputed. Exaples include: Record (struct) coponents: variable base (full address) + constant (sall) Array coponents: constant base (full address) + index variable (sall) Possible to store constant values w/o using another eory cell by storing the with or adjacent to the instruction itself Page 14

15 Coon Addressing Modes a-d Coon Addressing Modes e-g Page 15

16 Exaple: Coputer, SRC Siple RISC Coputer 32 general purpose registers of 32 bits 32-bit progra counter, PC, and instruction register, IR 2 32 bytes of eory address space The SRC CPU Main eory R0 R31 PC IR bit 0 general purpose 2 32 bytes registers of ain eory R[7] eans contents of register 7 M[32] eans contents of eory location 32 SRC Characteristics (=) Load-store design: only way to access eory is through load and store instructions ( ) Operation on 21-bit words only, no byte or half-word operations. (=) Only a few addressing odes are supported (=) ALU Instructions are 3-register type ( ) Branch instructions can branch unconditionally or conditionally on whether the value in a specified register is = 0, <> 0, >= 0, or < 0. ( ) Branch-and-link instructions are siilar, but leave the value of current PC in any register, useful for subroutine return. ( ) Can only branch to an address in a register, not to a direct address. (=) All instructions are 32-bits (1-word) long. (=) Siilar to coercial RISC achines ( ) Less powerful than coercial RISC achines. Page 16

17 SRC Basic Instruction Forats There are three basic instruction forat types The nuber of register specifier fields and length of the constant field vary Other forats result fro unused fields or parts Details of forats on next slide op ra c1 Type op ra rb c2 0 Type op ra rb rc c3 0 Type 3 Total of 7 Detailed Forats Instruction forats 1. Id, st, la, Op ra rb addi, andi, ori c Idr, str, lar Op ra c1 Id r3, A Id r3, 4(r5) addi r2, r4, #1 Idr r5, 8 Iar r6, 45 Exaple (R[3] = M[A]) (R[3] = M[R[5] + 4]) (R[2] = R[4] +1) (R[5] = M[PC + 8]) (R[6] = PC + 45) neg, not Op ra rc unused unused neg r7, r9 (R[7] = R[9]) br Op rb rc (c3) unused Cond unused brl Op ra rb rc (c3) unused Cond brzr r4, r0 (branch to R[4] if R[0] == 0) brlnz r6, r4, r0 (R[6]=PC;branchtoR[4]ifR[0] 0) 6. add, sub, and, or Op ra rb rc unused add r0, r2, r4 (R[0] = R[2] + R[4]) a Op ra rb (c3) unused Count 7. shr, shra shl, shic b Op ra rb rc (c3) unused shr r0, r1, #4 (R[0] = R[1] shifted right by 4 bits shl r2, r4, r6 (R[2] = R[4] shifted left by count in R[6]) nop, stop Op unused stop Page 17

18 Exaple SRC Load and Store Instructions Address can be constant, constant + register, or constant + PC Meory contents or address itself can be loaded Instruction op ra rb c1 Meaning Addressing Mode ld r1, R[1] M[32] Direct ld r22, 24(r4) R[22] M[24+R[4]] Displaceent st r4, 0(r9) M[R[9]] R[4] Register indirect la r7, R[7] 32 Iediate ldr r12, R[12] M[PC -48] Relative lar r3, R[3] PC Register (!) (note use of la to load a constant) Assebly Language Fors of Arithetic and Logic Instructions Forat Exaple Meaning neg ra, rc neg r1, r2 ;Negate (r1 = -r2) not ra, rc not r2, r3 ;Not (r2 = r3 ) add ra, rb, rc add r2, r3, r4 ;2 s copleent addition sub ra, rb, rc ;2 s copleent subtraction and ra, rb, rc ;Logical and or ra, rb, rc ;Logical or addi ra, rb, c2 addi r1, r3, #1 ;Iediate 2s 2 s copleent add andi ra, rb, c2 ;Iediate logical and ori ra, rb, c2 ;Iediate logical or Iediate subtract not needed since constant in addi ay be negative Page 18

19 Branch Instruction Forat There are actually only two branch instructions: br rb, rc, c3<2..0> ; branch to R[rb] if R[rc] eets ; the condition defined by c3<2..0> brl ra, rb, rc, c3<2..0> ; R[ra] PC; branch as above It is c3<2..0>, the 3 lsbs of c3, that governs what the branch condition is: lsbs condition Assy language for Exaple 000 never brlnv brlnv r6 001 always br, brl br r5, brl r5 010 if rc = 0 brzr, brlzr brzr r2, r4, r5 011 if rc 0 brnz, brlnz 100 if rc >= 0 brpl, brlpl 101 if rc < 0 bri, brli Note that branch target address is always in register R[rb]. It ust be placed there explicitly by a previous instruction. Fors and Forats of the br and brl Instructions Ass y lang. Exaple instr. Meaning op ra rb rc c Branch Cond n. brlnv brlnv r6 R[6] PC never br br r4 PC R[4] always brl brl r6,r4 R[6] PC; always PC R[4] brzr brzr r5,r1 if (R[1]=0) zero PC R[5] brlzr brlzr r7,r5,r1 R[7] PC; zero brnz brnz r1, r0 if (R[0] 0) PC R[1] nonzero brlnz brlnz r2,r1,r0 R[2] PC; nonzero if (R[0] 0) PC R[1] brpl brpl r3, r2 if (R[2]>=0) PC R[3] plus brlpl brlpl r4,r3,r2 R[4] PC; plus if (R[2]>=0) PC R[3] bri bri r0, r1 if (R[1]<0) PC R[0] inus brli brli r3,r0,r1 R[3] PC; if (r1<0) PC R[0] inus Page 19

20 RTN (Register Transfer Notation) Provides a foral eans of describing achine structure and function Can be used to describe what a achine does (an abstract RTN) without describing how the achine does it Can also be used to describe a particular hardware ipleentation (a concrete RTN) Soe RTN Features Using RTN to Describe a Machine s Static Properties Static Properties Specifying registers IR specifies a register naed IR having 32 bits nubered 31 to 0 Naing using the := naing operator: op 4..0 := IR specifies that the 5 sbs of IR be called op, with bits 4..0 Notice that this does not create a new register, it just generates another nae, or alias, for an already existing register or part of a register Page 20

21 Using RTN to Describe Dynaic Properties Dynaic Properties Conditional expressions: (op=12) R[ra] R[rb] + R[rc]: ; defines the add instruction if condition then RTN Assignent Operator This fragent of RTN describes the SRC add instruction. It says, when the op field of IR = 12, then store in the register specified by the ra field, the result of adding the register specified by the rb field to the register specified by the rc field. Using RTN to Describe the SRC (Static) Processor State Processor state PC : progra counter (eory addr. of next inst.) IR : instruction register Run: one bit run/halt indicator Strt: start signal R[0..31] : general purpose registers Page 21

22 RTN Register Declarations General register specifications shows soe features of the notation Describes a set of bit registers with naes R[0] to R[31] Nae of registers R[0..31] : Register # sb # in square brackets.. specifies a range of indices lsb# Bit # in angle brackets Colon separates stateents with no ordering Meory Declaration: RTN Naing Operator Defining naes with foral paraeters is a powerful foratting tool Used here to define word eory (big-endian) Main eory state Me[ ] 7..0 : 2 32 addressable bytes of eory M[x] := Me[x]#Me[x+1]#Me[x+2]#Me[x+3]: Duy paraeter Naing operator Concatenation operator All bits in register if no bit index given Page 22

23 RTN Instruction Foratting Uses Renaing of IR Bits Instruction forats op 4..0 := IR : ra 4..0 := IR : rb 4..0 := IR : rc 4..0 := IR : c := IR : c := IR : c := IR : operation code field target register field operand, address index, or branch target register second operand, conditional test, or shift count register long displaceent field short displaceent or iediate field count or odifier field Specifying Dynaic Properties of SRC: RTN Gives Specifics of Address Calculation Effective address calculations (occur at runtie): disp := ((rb=0) c {sign extend}: displaceent (rb 0) R[rb] + c {sign extend, 2's cop.} ): address rel := PC c {sign extend, 2 s cop.}: relative address Renaing defines displaceent and relative addresses New RTN notation is used condition expression eans if condition then expression odifiers in { } describe type of arithetic or how short nubers are extended to longer ones arithetic operators (+ - * / etc.) can be used in expressions Register R[0] cannot be added to a displaceent Page 23

24 Instruction Interpretation: RTN Description of Fetch-Execute Need to describe actions (not just declarations) Soe new notation: Logical NOT Logical AND instruction_interpretation := ( Run Strt R t Run 1: Run (IR M[PC]: PC PC + 4; instruction_execution) ); Register transfer Separates stateents that occur in sequence RTN Sequence and Clocking In general, RTN stateents separated by : take place during the sae clock pulse Stateents separated by ; take place on successive clock pulses This is not entirely accurate since soe things written with one RTN stateent can take several clocks to perfor More precise difference between : and ; The order of execution of stateents separated by : does not atter If stateents are separated by ; the one on the left ust be coplete before the one on the right starts Page 24

25 More About Instruction Interpretation RTN In the expression IR M[PC]: PC PC + 4; which value of PC applies to M[PC]? The rule in RTN is that all right hand sides of : - separated RTs are evaluated before any LHS is changed In logic design, this corresponds to aster-slave operation of flip-flops What happens when Run and Strt are both false? Since no action is specified for this case, the RTN iplicitly says that no action occurs in this case Individual Instructions instruction_interpretation contained a forward reference to instruction_execution instruction_execution is a long list of conditional operations The condition is that the op code specifies a given instruction The operation describes what that instruction does Note that the operations of the instruction are done after (;) the instruction is put into IR and the PC has been advanced to the next instruction Page 25

26 RTN Instruction Execution for Load and Store Instructions instruction_execution ec tion := ( ld (:= op= 1) R[ra] M[disp]: ldr (:= op= 2) R[ra] M[rel]: st (:= op= 3) M[disp] R[ra]: str (:= op= 4) M[rel] R[ra]: la (:= op= 5 ) R[ra] disp: lar (:= op= 6) R[ra] rel: load register load register relative store register store register relative load displaceent address load relative address The in-line definition (:= op=1) saves writing a separate definition ld := op=1 for the ld neonic The previous definitions of disp and rel are needed to understand all the details SRC RTN The Main Loop ii := instruction_interpretation: ie := instruction_execution : ii := ( Run Strt Run 1: Run (IR M[PC]: PC PC + 4; ie) ); ie := ( ld (:= op= 1) R[ra] M[disp]: Big switch ldr (:= op= 2) R[ra] M[rel]: stateent... on the opcode stop (:= op= 31) Run 0: ); ii Thus ii and ie invoke each other, as coroutines. Page 26

27 Use of RTN Definitions: Text Substitution Seantics ld (:= op= 1) R[ra] M[disp]: disp := ((rb=0) c {sign extend}: (rb 0) R[rb] + c {sign extend, 2's cop.} ): ld (:= op= 1) R[ra] M[ ((rb=0) c {sign extend}: (rb 0) R[rb] + c {sign extend, 2's cop.} ): ]: An exaple: If IR = then ld R[5] M[ R[3] + 11 ]: RTN Descriptions of SRC Branch Instructions Branch condition deterined by 3 lsbs of instruction Link register (R[ra]) set to point to next instruction cond := ( c =0 0: never c =1 1: always c =2 R[rc]=0: if register is zero c =3 R[rc] 0: if register is nonzero c =4 R[rc] 31 =0: if positive or zero c =5 R[rc] 31 =1 ): if negative br (:= op= 8) (cond PC R[rb]): conditional branch brl (:= op= 9) (R[ra] PC: cond (PC R[rb]) ): branch and link Page 27

28 RTN for Arithetic and Logic add (:= op=12) R[ra] R[rb] + R[rc]: addi (:= op=13) R[ra] R[rb] + c {2's cop. sign ext.}: sub (:= op=14) R[ra] R[rb] - R[rc]: neg (:= op=15) R[ra] -R[rc]: and (:= op=20) R[ra] R[rb] R[rc]: andi (:= op=21) R[ra] R[rb] c {sign extend}: or (:= op=22) R[ra] R[rb] R[rc]: ori (:= op=23) R[ra] R[rb] c {sign extend}: not (:= op=24) R[ra] R[rc]: Logical operators: and or and not RTN for Shift Instructions Count ay be 5 lsbs of a register or the instruction - replication, # - concatenation n := ( (c =0) R[rc] 4..0 : (c ) c ): shr (:= op=26) R[ra] ) # R[rb] 31..n : shra (:= op=27) R[ra] R[rb] 31 ) #R[rb] 31..n : shl (:= op=28) R[ra] R[rb] 31-n..0 # 0): shc (:= op=29) R[ra] R[rb] 31-n..0 # R[rb] n : Page 28

29 Exaple of Replication and Concatenation in Shift Arithetic shift right by 13 concatenates 13 copies of the sign bit with the upper 19 bits of the operand shra r1, r2, 13 R[2]= R[1]= # R[2] Assebly Language for Shift For of assebly language g instruction tells whether to set c3=0 shr ra, rb, rc ;Shift rb right into ra by 5 lsbs of rc shr ra, rb, count ;Shift rb right into ra by 5 lsbs of inst shra ra, rb, rc ;AShift rb right into ra by 5 lsbs of rc shra ra, rb, count ;AShift rb right into ra by 5 lsbs of inst shl ra, rb, rc ;Shift rb left into ra by 5 lsbs of rc shl ra, rb, count ;Shift rb left into ra by 5 lsbs of inst shc ra, rb, rc ;Shift rb circ. into ra by 5 lsbs of rc shc ra, rb, count ;Shift rb circ. into ra by 5 lsbs of inst Page 29

30 End of RTN Definition of instruction_execution nop (:= op= 0) : No operation stop (:= op= 31) Run 0: Stop instruction ); End of instruction_execution instruction_interpretation. We will find special use for nop in pipelining The achine waits for Strt after executing stop The long conditional stateent defining instruction_execution ends with a direction to go repeat instruction_interpretation, which will fetch and execute the next instruction (if Run still =1) Confused about RTN and SRC? SRC is a Machine Language It can be interpreted by either hardware or software siulator. RTN is a Specification Language Specification languages are languages that are used to specify other languages or systes a etalanguage. Other exaples: LEX, YACC, VHDL, Verilog Page 30

31 The Relationship of RTN to SRC SRC specification written in RTN RTN copiler Generated processor SRC progra and data SRC interpreter or siulator Data output A Note About Specification Languages They allow the description of what without having to specify how. They allow precise and unabiguous specifications, unlike natural language. They reduce errors: Errors due to isinterpretation of iprecise specifications written in natural language. Errors due to confusion o in design and ipleentation huan error. Now the designer ust debug the specification! Page 31

32 Addressing Modes Described in RTN (Not SRC) Target register Mode nae Assebler RTN eaning Use Syntax Register Ra R[t] R[a] Tp. Var. Register indirect (Ra) R[t] M[R[a]] Pointer Iediate #X R[t] X Constant Direct, absolute X R[t] M[X] Global Var. Indirect (X) R[t] M[ M[X] ] Pointer Var. Indexed, based, X(Ra) R[t] M[X + R[a]] Arrays, structs or displaceent Relative X(PC) R[t] M[X + PC] Vals stored w pg Autoincreent (Ra)+ R[t] M[R[a]]; R[a] R[a] + 1 Sequential Autodecreent - (Ra) R[a] R[a] - 1; R[t] M[R[a]] access. Register Transfers Hardware and Tiing for a Single-Bit Register Transfer: A B Ipleenting the RTN stateent A B D B Strobe D A B 1 0 Strobe 1 0 A 1 0 (a) Hardware (b) Tiing Page 32

33 Multiple Bit Register Transfer: A..1 B..1 D 1 D 1 D 2 D 2 D B..1 D A..1 D D Strobe B Strobe A (a) Individual flip-flops (b) Abbreviated notation Data Transission View of Logic Gates Logic gates can be used to control the transission of data: data gate data gate data gate 0 Data gate control data data 1 data 2 data 1 data 2 data1(2), provided data2(1) is zero control control data Data erge Controlled copleent Page 33

34 Two-Way Gated Merge, or Multiplexer Data fro ultiple sources can be selected for transission x x G x y x y G y Tie y Basic Multiplexer and Sybol Abbreviation An n-way gated erge An n-way ultiplexer with decoder D 0 G 0 D 0 D 1 D 1 G 1 D n 1 D n 1 G n 1 k Select (a) Multiplexer in ters of gates (b) Sybol abbreviation Multiplexer gate signals G i ay be produced by a binary to one-out-of-n decoder Page 34

35 Separating Merged Data x y x 0 G x Tie Merged data can be separated by gating at the right tie It can also be strobed into a flip-flop when valid Multiplexed Register Transfers Using Gates and Strobes D C G C S A D A G C Hold tie D D G D S B D B S B Propagation tie Gates Strobes Selected gate and strobe deterine which RT A C and B C can occur together, but not A C and B D Page 35

36 Tri-State Gate Internal Structure and Sybol +V Data Out Data Tristate Out Enable Enable (a) Tri-state gate structure (b) Tri-state gate sybol Enable Data Output Hi-Z Hi-Z 0 1 (c) Tri-state gate truth table Registers Connected by a Tri-State Bus D R[0] D R[1]... D R[n 1] S 0 G 0 S 1 G 1 S n 1 G n 1 Tri-state bus Can ake any register transfer R[i] R[j] Can t have G i = G j = 1 for i j Violating this constraint gives low resistance path fro power supply to ground with predictable results! Page 36

37 Registers and Arithetic Units Connected by One Bus Exaple: Abstract RTN R[3] R[1]+R[2]; R[0] in D R[0] R[0] out Increenter D Concrete RTN Y R[2]; Z R[1]+Y; R[3] Z; R[1] in D R[1] R[1] out W W out D Y Y in W in Cobinational logic no eory Control Sequence R[2] out, Y in ; R[1] out, Z in ; Z out, R[3] in ;... D R[n 1] R[n 1] in R[n Ð 1] out Z in Notice that what could be described in one step in the abstract RTN took three steps on this particular hardware Z out Adder Z D Fro Abstract RTN to Concrete RTN to Control Sequences The ability to begin with an abstract description, then describe a hardware design and resulting concrete RTN and control sequence is powerful. We shall use this ethod in Chapter 4 to develop various hardware designs for SRC. Page 37

38 Chapter 2 Suary Classes of coputer ISAs Meory addressing odes SRC: a coplete exaple ISA RTN as a description ethod for ISAs RTN description of addressing odes Ipleentation of RTN operations with digital logic circuits Gates, strobes, and ultiplexers l Page 38