Example: Computer, SRC Simple RISC Computer

Transcription

1 2-24 Chapter 2 Machines, Machine Languages, and Digital Logic Exaple: Coputer, SRC Siple RISC Coputer 32 general purpose registers of 32 bits 32-bit progra counter, PC, and instruction register, IR 2 32 bytes of eory address space The SRC CPU Main eory R0 R31 PC IR bit general purpose registers 2 32 bytes of ain eory R[7] eans contents of register 7 M[32] eans contents of eory location 32

2 2-25 Chapter 2 Machines, Machine Languages, and Digital Logic SRC Characteristics Load-store design: only way to access eory is through load and store instructions Only a few addressing odes are supported ALU instructions are 3-register type Branch instructions can branch unconditionally or conditionally on whether the value in a specified register is = 0, <> 0, >= 0, or < 0 Branch and link instructions are siilar, but leave the value of current PC in any register, useful for subroutine return All instructions are 32 bits (1 word) long

3 2-26 Chapter 2 Machines, Machine Languages, and Digital Logic SRC Basic Instruction Forats There are three basic instruction forat types The nuber of register specifier fields and length of the constant field vary Other forats result fro unused fields or parts Details of forats on next slide op r a c1 Type op ra rb c2 0 Type op ra rb rc c3 0 Type 3

4 2-27 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.9 (Partial) Total of 7 Detailed Forats 1. Id, st, la, addi, andi, ori Instruction forats Op ra rb c Idr, str, lar Op ra c neg, not Op ra rc unused unused br Op rb rc (c3) unused Cond unused brl Op ra rb rc (c3) unused Cond Id r3, A Id r3, 4(r5) addi r2, r4, #1 Idr r5, 8 Iar r6, 45 neg r7, r9 Exaple (R[3] = M[A]) (R[3] = M[R[5] + 4]) (R[2] = R[4] +1) (R[5] = M[PC + 8]) (R[6] = PC + 45) (R[7] = R[9]) brzr r4, r0 (branch to R[4] if R[0] == 0) brlnz r6, r4, r0 (R[6] = PC; branch to R[4] if R[0] 0) 6. add, sub, and, or Op ra rb rc unused add r0, r2, r4 (R[0] = R[2] + R[4]) 7. shr, shra shl, shic 7a 7b Op ra rb (c3) unused Count Op ra rb rc (c3) unused shr r0, r1, #4 (R[0] = R[1] shifted right by 4 bits shl r2, r4, r6 (R[2] = R[4] shifted left by count in R[6]) nop, stop Op unused stop

5 2-28 Chapter 2 Machines, Machine Languages, and Digital Logic Tbl 2.4 Exaple SRC Load and Store Instructions Address can be constant, constant + register, or constant + PC Meory contents or address itself can be loaded Instruction op ra rb c1 Meaning Addressing Mode ld r1, R[1] M[32] Direct ld r22, 24(r4) R[22] M[24+R[4]] Displaceent st r4, 0(r9) M[R[9]] R[4] Register indirect la r7, R[7] 32 Iediate ldr r12, R[12] M[PC -48] Relative lar r3, R[3] PC Register (!) (note use of la to load a constant)

6 2-29 Chapter 2 Machines, Machine Languages, and Digital Logic Assebly Language Fors of Arithetic and Logic Instructions Forat Exaple Meaning neg ra, rc neg r1, r2 ;Negate (r1 = -r2) not ra, rc not r2, r3 ;Not (r2 = r3 ) add ra, rb, rc add r2, r3, r4 ;2 s copleent addition sub ra, rb, rc ;2 s copleent subtraction and ra, rb, rc ;Logical and or ra, rb, rc ;Logical or addi ra, rb, c2 addi r1, r3, #1 ;Iediate 2 s copleent add andi ra, rb, c2 ;Iediate logical and ori ra, rb, c2 ;Iediate logical or Iediate subtract not needed since constant in addi ay be negative

7 2-30 Chapter 2 Machines, Machine Languages, and Digital Logic Branch Instruction Forat There are actually only two branch instructions: br rb, rc, c3<2..0> ; branch to R[rb] if R[rc] eets ; the condition defined by c3<2..0> brl ra, rb, rc, c3<2..0> ; R[ra] PC; branch as above It is c3<2..0>, the 3 lsbs of c3, that governs what the branch condition is: lsbs condition Assy language for Exaple 000 never brlnv brlnv r6 001 always br, brl br r5, brl r5 010 if rc = 0 brzr, brlzr brzr r2, r4, r5 011 if rc 0 brnz, brlnz 100 if rc 0 brpl, brlpl 101 if rc < 0 bri, brli Note that branch target address is always in register R[rb]. It ust be placed there explicitly by a previous instruction.

8 2-31 Chapter 2 Machines, Machine Languages, and Digital Logic Tbl 2.6 Fors and Forats of the br and brl Instructions Ass y lang. Exaple instr. Meaning op ra rb rc c Branch Cond n. brlnv brlnv r6 R[6] PC never br br r4 PC R[4] always brl brl r6,r4 R[6] PC; always PC R[4] brzr brzr r5,r1 if (R[1]=0) zero PC R[5] brlzr brlzr r7,r5,r1 R[7] PC; zero brnz brnz r1, r0 if (R[0] 0) PC R[1] nonzero brlnz brlnz r2,r1,r0 R[2] PC; nonzero if (R[0] 0) PC R[1] brpl brpl r3, r2 if (R[2] 0) PC R[3] plus brlpl brlpl r4,r3,r2 R[4] PC; plus if (R[2] 0) PC R[3] bri bri r0, r1 if (R[1]<0) PC R[0] inus brli brli r3,r0,r1 R[3] PC; if (r1<0) PC R[0] inus

9 2-32 Chapter 2 Machines, Machine Languages, and Digital Logic Branch Instructions Exaple C: goto Label3 SRC: reg. lar r0, Label3 br r0 ; put branch target address into tgt ; and branch Label3

10 2-33 Chapter 2 Machines, Machine Languages, and Digital Logic Exaple of Conditional Branch in C: #define Cost 125 if (X<0) then X = -X; in SRC: Cost.equ 125 ;define sybolic constant.org 1000 ;next word will be loaded at address X:.dw 1 ;reserve 1 word for variable X.org 5000 ;progra will be loaded at location lar r0, Over ;load address of false jup location ld r1, X ;load value of X into r1 brpl r0, r1 ;branch to Else if r1 0 neg r1, r1 ;negate value Over: ;continue

11 2-34 Chapter 2 Machines, Machine Languages, and Digital Logic RTN (Register Transfer Notation) Provides a foral eans of describing achine structure and function Is at the just right level for achine descriptions Does not replace hardware description languages Can be used to describe what a achine does (an abstract RTN) without describing how the achine does it Can also be used to describe a particular hardware ipleentation (a concrete RTN)

12 2-35 Chapter 2 Machines, Machine Languages, and Digital Logic RTN (cont d.) At first you ay find this eta description confusing, because it is a language that is used to describe a language You will find that developing a failiarity with RTN will aid greatly in your understanding of new achine design concepts We will describe RTN by using it to describe SRC

13 2-36 Chapter 2 Machines, Machine Languages, and Digital Logic Soe RTN Features Using RTN to Describe a Machine s Static Properties Static Properties Specifying registers IR specifies a register naed IR having 32 bits nubered 31 to 0 Naing using the := naing operator: op 4..0 := IR specifies that the 5 sbs of IR be called op, with bits 4..0 Notice that this does not create a new register, it just generates another nae, or alias, for an already existing register or part of a register

14 2-37 Chapter 2 Machines, Machine Languages, and Digital Logic Using RTN to Describe Dynaic Properties Dynaic Properties Conditional expressions: (op=12) R[ra] R[rb] + R[rc]: ; defines the add instruction if condition then RTN Assignent Operator This fragent of RTN describes the SRC add instruction. It says, when the op field of IR = 12, then store in the register specified by the ra field, the result of adding the register specified by the rb field to the register specified by the rc field.

15 2-38 Chapter 2 Machines, Machine Languages, and Digital Logic Using RTN to Describe the SRC (Static) Processor State Processor state PC : progra counter (eory addr. of next inst.) IR : instruction register Run: one bit run/halt indicator Strt: start signal R[0..31] : general purpose registers

16 2-39 Chapter 2 Machines, Machine Languages, and Digital Logic RTN Register Declarations General register specifications shows soe features of the notation Describes a set of bit registers with naes R[0] to R[31] R[0..31] : Nae of registers Register # in square brackets.. specifies a range of indices sb # lsb# Bit # in angle brackets Colon separates stateents with no ordering

17 2-40 Chapter 2 Machines, Machine Languages, and Digital Logic Meory Declaration: RTN Naing Operator Defining naes with foral paraeters is a powerful foratting tool Used here to define word eory (big-endian) Main eory state Me[ ] 7..0 : 232 addressable bytes of eory M[x] := Me[x]#Me[x+1]#Me[x+2]#Me[x+3]: Duy paraeter Naing operator Concatenation operator All bits in register if no bit index given

18 2-41 Chapter 2 Machines, Machine Languages, and Digital Logic RTN Instruction Foratting Uses Renaing of IR Bits Instruction forats op 4..0 := IR : ra 4..0 := IR : rb 4..0 := IR : rc 4..0 := IR : c := IR : c := IR : c := IR : operation code field target register field operand, address index, or branch target register second operand, conditional test, or shift count register long displaceent field short displaceent or iediate field count or odifier field

19 2-42 Chapter 2 Machines, Machine Languages, and Digital Logic Specifying Dynaic Properties of SRC: RTN Gives Specifics of Address Calculation Effective address calculations (occur at runtie): disp := ((rb=0) c {sign extend}: displaceent (rb 0) R[rb] + c {sign extend, 2 s cop.} ): address rel := PC c {sign extend, 2 s cop.}: relative address Renaing defines displaceent and relative addresses New RTN notation is used condition expression eans if condition then expression odifiers in { } describe type of arithetic or how short nubers are extended to longer ones arithetic operators (+ - * / etc.) can be used in expressions Register R[0] cannot be added to a displaceent

20 2-43 Chapter 2 Machines, Machine Languages, and Digital Logic Detailed uestions Answered by the RTN for Addresses What set of eory cells can be addressed by direct addressing (displaceent with rb=0) If c2 16 =0 (positive displaceent) absolute addresses range fro H to 0000FFFFH If c2 16 =1 (negative displaceent) absolute addresses range fro FFFF0000H to FFFFFFFFH What range of eory addresses can be specified by a relative address The largest positive value of C is and its ost negative value is -221, so addresses up to forward and 221 backward fro the current PC value can be specified Note the difference between rb and R[rb]

21 2-44 Chapter 2 Machines, Machine Languages, and Digital Logic Instruction Interpretation: RTN Description of Fetch-Execute Need to describe actions (not just declarations) Soe new notation Logical NOT Logical AND instruction_interpretation := ( Run Strt Run 1: Run (IR M[PC]: PC PC + 4; instruction_execution) ); Register transfer Separates stateents that occur in sequence

22 2-45 Chapter 2 Machines, Machine Languages, and Digital Logic RTN Sequence and Clocking In general, RTN stateents separated by : take place during the sae clock pulse Stateents separated by ; take place on successive clock pulses This is not entirely accurate since soe things written with one RTN stateent can take several clocks to perfor More precise difference between : and ; The order of execution of stateents separated by : does not atter If stateents are separated by ; the one on the left ust be coplete before the one on the right starts

23 2-46 Chapter 2 Machines, Machine Languages, and Digital Logic More About Instruction Interpretation RTN In the expression IR M[PC]: PC PC + 4; which value of PC applies to M[PC]? The rule in RTN is that all right hand sides of : - separated RTs are evaluated before any LHS is changed In logic design, this corresponds to aster-slave operation of flip-flops We see what happens when Run is true and when Run is false but Strt is true. What about the case of Run and Strt both false? Since no action is specified for this case, the RTN iplicitly says that no action occurs in this case

24 2-47 Chapter 2 Machines, Machine Languages, and Digital Logic Individual Instructions instruction_interpretation contained a forward reference to instruction_execution instruction_execution is a long list of conditional operations The condition is that the op code specifies a given instruction The operation describes what that instruction does Note that the operations of the instruction are done after (;) the instruction is put into IR and the PC has been advanced to the next instruction

25 2-48 Chapter 2 Machines, Machine Languages, and Digital Logic RTN Instruction Execution for Load and Store Instructions instruction_execution := ( ld (:= op= 1) R[ra] M[disp]: ldr (:= op= 2) R[ra] M[rel]: st (:= op= 3) M[disp] R[ra]: str (:= op= 4) M[rel] R[ra]: la (:= op= 5 ) R[ra] disp: lar (:= op= 6) R[ra] rel: load register load register relative store register store register relative load displaceent address load relative address The in-line definition (:= op=1) saves writing a separate definition ld := op=1 for the ld neonic The previous definitions of disp and rel are needed to understand all the details

26 2-49 Chapter 2 Machines, Machine Languages, and Digital Logic SRC RTN The Main Loop ii := instruction_interpretation: ie := instruction_execution : ii := ( Run Strt Run 1: Run (IR M[PC]: PC PC + 4; ie) ); ie := ( ld (:= op= 1) R[ra] M[disp]: Big switch ldr (:= op= 2) R[ra] M[rel]: stateent... on the opcode stop (:= op= 31) Run 0: ); ii Thus ii and ie invoke each other, as coroutines.

27 2-50 Chapter 2 Machines, Machine Languages, and Digital Logic Use of RTN Definitions: Text Substitution Seantics ld (:= op= 1) R[ra] M[disp]: disp := ((rb=0) c {sign extend}: (rb 0) R[rb] + c {sign extend, 2 s cop.} ): ld (:= op= 1) R[ra] M[ ((rb=0) c {sign extend}: (rb 0) R[rb] + c {sign extend, 2 s cop.} ): ]: An exaple: If IR = then ld R[5] M[ R[3] + 11 ]:

28 2-51 Chapter 2 Machines, Machine Languages, and Digital Logic RTN Descriptions of SRC Branch Instructions Branch condition deterined by 3 lsbs of instruction Link register (R[ra]) set to point to next instruction cond := ( c =0 0: c =1 1: c =2 R[rc]=0: c =3 R[rc] 0: c =4 R[rc] 31 =0: c =5 R[rc] 31 =1 ): br (:= op= 8) (cond PC R[rb]): brl (:= op= 9) (R[ra] PC: cond (PC R[rb]) ): never always if register is zero if register is nonzero if positive or zero if negative conditional branch branch and link

29 2-52 Chapter 2 Machines, Machine Languages, and Digital Logic RTN for Arithetic and Logic add (:= op=12) R[ra] R[rb] + R[rc]: addi (:= op=13) R[ra] R[rb] + c {2's cop. sign ext.}: sub (:= op=14) R[ra] R[rb] - R[rc]: neg (:= op=15) R[ra] -R[rc]: and (:= op=20) R[ra] R[rb] R[rc]: andi (:= op=21) R[ra] R[rb] c {sign extend}: or (:= op=22) R[ra] R[rb] R[rc]: ori (:= op=23) R[ra] R[rb] c {sign extend}: not (:= op=24) R[ra] R[rc]: Logical operators: and or and not

30 2-53 Chapter 2 Machines, Machine Languages, and Digital Logic RTN for Shift Instructions Count ay be 5 lsbs of a register or the instruction - replication, # - concatenation n := ( (c =0) R[rc] 4..0 : (c ) c ): shr (:= op=26) R[ra] ) # R[rb] 31..n : shra (:= op=27) R[ra] R[rb] 31 ) # R[rb] 31..n : shl (:= op=28) R[ra] R[rb] 31-n..0 # 0): shc (:= op=29) R[ra] R[rb] 31-n..0 # R[rb] n :

31 2-54 Chapter 2 Machines, Machine Languages, and Digital Logic Exaple of Replication and Concatenation in Shift Arithetic shift right by 13 concatenates 13 copies of the sign bit with the upper 19 bits of the operand shra r1, r2, 13 R[2]= R[1]= 13@R[2] # R[2]

32 2-55 Chapter 2 Machines, Machine Languages, and Digital Logic Assebly Language for Shift For of assebly language instruction tells whether to set c3=0 shr ra, rb, rc shr ra, rb, count shra ra, rb, rc shra ra, rb, count shl ra, rb, rc shl ra, rb, count shc ra, rb, rc shc ra, rb, count ;Shift rb right into ra by 5 lsbs of rc ;Shift rb right into ra by 5 lsbs of inst ;AShift rb right into ra by 5 lsbs of rc ;AShift rb right into ra by 5 lsbs of inst ;Shift rb left into ra by 5 lsbs of rc ;Shift rb left into ra by 5 lsbs of inst ;Shift rb circ. into ra by 5 lsbs of rc ;Shift rb circ. into ra by 5 lsbs of inst

33 2-56 Chapter 2 Machines, Machine Languages, and Digital Logic End of RTN Definition of instruction_execution nop (:= op= 0) : No operation stop (:= op= 31) Run 0: Stop instruction ); End of instruction_execution instruction_interpretation. We will find special use for nop in pipelining The achine waits for Strt after executing stop The long conditional stateent defining instruction_execution ends with a direction to go repeat instruction_interpretation, which will fetch and execute the next instruction (if Run still =1)

34 2-57 Chapter 2 Machines, Machine Languages, and Digital Logic Confused about RTN and SRC? SRC is a Machine Language It can be interpreted by either hardware or software siulator. RTN is a Specification Language Specification languages are languages that are used to specify other languages or systes a etalanguage. Other exaples: LEX, YACC, VHDL, Verilog Figure 2.10 ay help clear this up...

35 2-58 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.10 The Relationship of RTN to SRC SRC specification written in RTN RTN copiler Generated processor SRC progra and data SRC interpreter or siulator Data output

36 2-59 Chapter 2 Machines, Machine Languages, and Digital Logic A Note About Specification Languages They allow the description of what without having to specify how. They allow precise and unabiguous specifications, unlike natural language. They reduce errors: Errors due to isinterpretation of iprecise specifications written in natural language. Errors due to confusion in design and ipleentation huan error. Now the designer ust debug the specification! Specifications can be autoatically checked and processed by tools. An RTN specification could be input to a siulator generator that would produce a siulator for the specified achine. An RTN specification could be input to a copiler generator that would generate a copiler for the language, whose output could be run on the siulator.

37 2-60 Chapter 2 Machines, Machine Languages, and Digital Logic Addressing Modes Described in RTN (Not SRC) Target register Mode nae Assebler RTN eaning Use Syntax Register Ra R[t] R[a] Tp. Var. Register indirect (Ra) R[t] M[R[a]] Pointer Iediate #X R[t] X Constant Direct, absolute X R[t] M[X] Global Var. Indirect (X) R[t] M[ M[X] ] Pointer Var. Indexed, based, X(Ra) R[t] M[X + R[a]] Arrays, structs or displaceent Relative X(PC) R[t] M[X + PC] Vals stored w pg Autoincreent (Ra)+ R[t] M[R[a]]; R[a] R[a] + 1 Sequential Autodecreent - (Ra) R[a] R[a] - 1; R[t] M[R[a]] access.

38 2-61 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.11 Register Transfers Hardware and Tiing for a Single-Bit Register Transfer: A B Ipleenting the RTN stateent A B D B Strobe D A B Strobe A (a) Hardware (b) Tiing

39 2-62 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.12 Multiple Bit Register Transfer: A..1 B..1 D 1 D 1 D 2 D 2 D B..1 D A..1 D D Strobe B Strobe A (a) Individual flip-flops (b) Abbreviated notation

40 2-63 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.13 Data Transission View of Logic Gates Logic gates can be used to control the transission of data: data gate data gate data gate 0 Data gate control data data 1 data 2 data 1 data 2 data1(2), provided data2(1) is zero control control data Data erge Controlled copleent

41 2-64 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.14 Two-Way Gated Merge, or Multiplexer Data fro ultiple sources can be selected for transission x x G x y x y G y Tie y

42 2-65 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.15 Basic Multiplexer and Sybol Abbreviation An n-way gated erge An n-way ultiplexer with decoder D 0 G 0 D 0 D 1 D 1 G 1 D n 1 D n 1 G n 1 k Select (a) Multiplexer in ters of gates (b) Sybol abbreviation Multiplexer gate signals G i ay be produced by a binary to one-out-of-n decoder

43 2-66 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.16 Separating Merged Data x y x 0 G x Tie Merged data can be separated by gating at the right tie It can also be strobed into a flip-flop when valid

44 2-67 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.17 Multiplexed Register Transfers Using Gates and Strobes D D Hold tie C A S A G C G C D D S B D B S B Propagation tie G D Gates Strobes Selected gate and strobe deterine which RT A C and B C can occur together, but not A C and B D

45 2-68 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.18 Open-Collector NAND Gate Output Circuit +V Inputs Output 0v 0v +V 0v +V 0v Open Open Open (Out = +V) (Out = +V) (Out = +V) +V +V Out o.c. +V +V Closed (Out = 0v) (a) Open-collector NAND truth table (b) Open-collector NAND (c) Sybol

46 2-69 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.19 Wired AND Connection of Open-Collector Gates +V +V a Out b o.c. o.c. (a) Wired AND connection (b) With sybols a Switch b Wired AND output Closed(0) Closed(0) Open (1) Open (1) Closed(0) Open (1) Closed(0) Open (1) (c) Truth table 0v (0) 0v (0) 0v (0) +V (1)

47 2-70 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.20 Open-Collector Wired OR Bus DeMorgan s OR by not of AND of NOTS Pull-up resistor reoved fro each gate - open collector One pull-up resistor for whole bus Fors an OR distributed over the connection +V D 0 D 1 D n 1 G 0 o.c. o.c. o.c. G 1 G n 1

48 2-71 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.21 Tri-State Gate Internal Structure and Sybol +V Data Out Data Tristate Out Enable Enable (a) Tri-state gate structure (b) Tri-state gate sybol Enable Data Output Hi-Z Hi-Z 0 1 (c) Tri-state gate truth table

49 2-72 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.22 Registers Connected by a Tri-State Bus D R[0] D R[1] D R[n 1] S 0 G 0 S 1 G 1 S n 1 G n 1 Tri-state bus Can ake any register transfer R[i] R[j] Can t have G i = G j = 1 for i j Violating this constraint gives low resistance path fro power supply to ground with predictable results!

50 2-73 Chapter 2 Machines, Machine Languages, and Digital Logic Fig 2.23 Registers and Arithetic Units Connected by One Bus Exaple: Abstract RTN R[3] R[1]+R[2]; R[0] in D R[0] R[0] out Increenter D Concrete RTN Y R[2]; Z R[1]+Y; R[3] Z; R[1] in D R[1] R[1] out W W out D Y Y in W in Cobinational logic no eory Control Sequence R[2] out, Y in ; R[1] out, Z in ; Z out, R[3] in ; D R[n 1] Adder D Z R[n 1] in R[n 1] out Z out Z in Notice that what could be described in one step in the abstract RTN took three steps on this particular hardware

51 2-74 Chapter 2 Machines, Machine Languages, and Digital Logic RTs Possible with the One-Bus Structure R[i] or Y can get the contents of anything but Y Since result different fro operand, it cannot go on the bus that is carrying the operand Arithetic units thus have result registers Only one of two operands can be on the bus at a tie, so adder has register for one operand R[i] R[j] + R[k] is perfored in 3 steps: Y R[k]; Z R[j] + Y; R[i] Z; R[i] R[j] + R[k] is high level RTN description Y R[k]; Z R[j] + Y; R[i] Z; is concrete RTN Map to control sequence is: R[2] out, Y in ; R[1] out, Z in ; Z out, R[3] in ;

52 2-75 Chapter 2 Machines, Machine Languages, and Digital Logic Fro Abstract RTN to Concrete RTN to Control Sequences The ability to begin with an abstract description, then describe a hardware design and resulting concrete RTN and control sequence is powerful. We shall use this ethod in Chapter 4 to develop various hardware designs for SRC.

53 2-76 Chapter 2 Machines, Machine Languages, and Digital Logic Chapter 2 Suary Classes of coputer ISAs Meory addressing odes SRC: a coplete exaple ISA RTN as a description ethod for ISAs RTN description of addressing odes Ipleentation of RTN operations with digital logic circuits Gates, strobes, and ultiplexers