The Microarchitecture Level
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1 The Microarchitecture Level Chapter 4
2 The Data Path (1) The data path of the example microarchitecture used in this chapter.
3 The Data Path (2) Useful combinations of ALU signals and the function performed.
4 Data Path Timing Timing diagram of one data path cycle.
5 Memory Operation Mapping of the bits in MAR to the address bus.
6 Microinstructions The microinstruction format for the Mic-1.
7 Microinstruction Control: The Mic-1 (1) The complete block diagram of our example microarchitecture, the Mic-1.
8 Microinstruction Control: The Mic-1 (2) A microinstruction with JAMZ set to 1 has two potential successors.
9 Stacks (1) Use of a stack for storing local variables. b) While A is active. b) After A calls B. c) (c) After B calls C. d) After C and B return and A calls D.
10 Stacks (2) Use of an operand stack for doing an arithmetic computation.
11 The IJVM Memory Model The various parts of the IJVM memory.
12 The IJVM Instruction Set (1) The IJVM instruction set. The operands byte, const, and varnum are 1 byte. The operands disp, index, and offset are 2 bytes.
13 The IJVM Instruction Set (2) a) b) Memory before executing INVOKEVIRTUAL. After executing it.
14 The IJVM Instruction Set (3) a) b) Memory before executing IRETURN. After executing it.
15 Compiling Java to IJVM (1) a) b) c) A Java fragment. The corresponding Java assembly language. The IJVM program in hexadecimal.
16 Compiling Java to IJVM (1) The stack after each instruction of Fig. 4-14(b).
17 Microinstructions and Notation All permitted operations. Any of the above operations may be extended by adding << 8 to them to shift the result left by 1 byte. For example, a common operation is H = MBR << 8
18 Implementation of IJVM Using the Mic-1 (1) The microprogram for the Mic-1
19 Implementation of IJVM Using the Mic-1 (2) The microprogram for the Mic-1
20 Implementation of IJVM Using the Mic-1 (3) The microprogram for the Mic-1
21 Implementation of IJVM Using the Mic-1 (4) The microprogram for the Mic-1
22 Implementation of IJVM Using the Mic-1 (5) The microprogram for the Mic-1
23 Implementation of IJVM Using the Mic-1 (6) The BIPUSH instruction format. g) h) ILOAD with a 1-byte index. WIDE ILOAD with a 2-byte index.
24 Implementation of IJVM Using the Mic-1 (7) The initial microinstruction sequence for ILOAD and WIDE ILOAD. The addresses are examples.
25 Implementation of IJVM Using the Mic-1 (8) The IINC instruction has two different operand fields.
26 Implementation of IJVM Using the Mic-1 (9) The situation at the start of various microinstructions. a) Main1. b) goto1. c) goto2. d) goto3. e) goto4.
27 Speed Versus Cost A. Reduce the number of clock cycles needed to execute an instruction. B. Simplify the organization so that the clock cycle can be shorter. C. Overlap the execution of instructions.
28 Merging the Interpreter Loop with the Microcode (1) Original microprogram sequence for executing POP.
29 Merging the Interpreter Loop with the Microcode (2) Enhanced microprogram sequence for executing POP.
30 A Three Bus Architecture (1) Mic-1 code for executing ILOAD.
31 A Three Bus Architecture (2) Three-bus code for executing ILOAD.
32 A Three Bus Architecture (3) A fetch unit for the Mic-1.
33 A Three Bus Architecture (4) A finite state machine for implementing the IFU.
34 A Three Bus Architecture (5) The data path for Mic-2.
35 A Pipelined Design: The Mic-3 (1) The microprogram for the Mic-2
36 A Pipelined Design: The Mic-3 (2) The microprogram for the Mic-2
37 A Pipelined Design: The Mic-3 (3) The microprogram for the Mic-2
38 A Pipelined Design: The Mic-3 (4) The microprogram for the Mic-2
39 Three Bus Architecture The three-bus data path used in the Mic-3.
40 Implementation of SWAP (1) The Mic-2 code for SWAP.
41 Implementation of SWAP (2) The implementation of SWAP on the Mic-3.
42 Pipeline Graphical illustration of how a pipeline works.
43 A Seven-Stage Pipeline: The Mic-4 (1) The main components of the Mic-4.
44 A Seven-Stage Pipeline: The Mic-4 (2) The Mic-4 pipeline.
45 Cache Memory A system with three levels of cache.
46 Direct-Mapped Caches (a) A direct-mapped cache. (b) A 32-bit virtual address.
47 Set-Associative Caches A four-way set-associative cache.
48 Branch Prediction (a) A program fragment. (b) Its translation to a generic assemblylanguage.
49 Dynamic Branch Prediction (1) (a) A 1-bit branch history. (b) A 2-bit branch history. (c) A mapping between branch instruction address and target address.
50 Dynamic Branch Prediction (2) A 2-bit finite-state machine for branch prediction.
51 Out-of-Order Execution and Register Renaming (1) A superscalar CPU with in-order issue and in-order completion.
52 Out-of-Order Execution and Register Renaming (2) A superscalar CPU with in-order issue and in-order completion.
53 Out-of-Order Execution and Register Renaming (3) Operation of a superscalar CPU with out-of-order issue and out of-order completion.
54 Speculative Execution a) b) A program fragment. The corresponding basic block graph.
55 Overview of the NetBurst Microarchitecture The block diagram of the Pentium 4.
56 The NetBurst Pipeline A simplified view of the Pentium 4 data path.
57 Overview of the UltraSPARC III Cu Microarchitecture The block diagram of the UltraSPARC III Cu.
58 UltraSPARC III Cu Pipeline A simplified representation of the UltraSPARC III Cu pipeline.
59 The Microarchitecture of the 8051 CPU The microarchitecture of the 8051.
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