Topics. Computer Organization CS Mic-1 Microinstructions. Control Store (ROM) Programming Teams

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Computer Organization CS -0 Mic- Microinstructions Dr. William H. Robinson November, 004 http://eecs.vanderbilt.edu/courses/cs/ Topics There is no one giant step that does it.

1 Computer Organization CS -0 Mic- Microinstructions Dr. William H. Robinson November, Topics There is no one giant step that does it. It's a lot of little steps. Peter A. Cohen (American Investment Banker) Administrative stuff Homework # posted Program # posted (Later today) Mic- Microinstructions Improving the Mic- Programming Teams Weblink from class schedule page Keep the same teams for all assignments Control Store (ROM) Team : Noor, Ted, Tamim Team : Michael, David F., Nikhil Team : Theodor, Brandon, Jon Team 4: Brett, Jeb, John W. Team 5: Dante, Clay, William Team 6: John L., Lauren, David R. Memory that holds the microprogram Contains 5 words, each a 6-bit microinstruction Each microinstruction specifies its successor Not executed in order stored in control store Accessing the microprogram MicroProgram Counter holds address for next microinstruction MicroInstruction Register holds the current microinstruction 4

Microinstruction Notation Could use the 6-bit words Cumbersome method Easier to abstract to pseudocode Things to be familiar with Register names & functions MAR/MDR & PC/MBR functions IJVM

H = LV MAR = MBRU + H; rd PC = PC + ; fetch H = MDR PC = PC + ; fetch MDR = MBR + H; wr; goto Main Figure 4-7 contains the Mic- microprogram 6 Assignment and ALU Operations Memory Access

2 Microinstruction Notation Could use the 6-bit words Cumbersome method Easier to abstract to pseudocode Things to be familiar with Register names & functions MAR/MDR & PC/MBR functions IJVM memory model 5 Microcode for a Mystery IJVM Instruction Each line is execution cycle! Several tasks are combined. H = LV MAR = MBRU + H; rd PC = PC + ; fetch H = MDR PC = PC + ; fetch MDR = MBR + H; wr; goto Main Figure 4-7 contains the Mic- microprogram 6 Assignment and ALU Operations Memory Access rd, wr Uses MAR/MDR to access constant pool, current local variable frame and current operand stack fetch Uses PC/MBR to access method area Initiated at the end of the cycle After the C bus is valid Data availability for rd and fetch At the end of the next cycle 7 8

3 Branching Unconditional goto label Can explicitly name a successor for unconditional branch Program Status Word ISA register containing status flags (p. 0) Conditional Use ALU flags Z and N Program Status Word Set according to the result of the ALU operation Ex: Z = TOS If (Z) goto L; else L If (N) goto L; else L N Set when the result is Negative Z Set when the result is Zero V Set when the result caused an overflow C Set when the result caused a Carry out of MSB P Set when the result had even Parity Multiway branch for next opcode goto (MBR OR value) 9 0 Next Address Opcode is the anchor for each IJVM instruction First microinstruction for each IJVM instruction loaded at that hexadecimal address in control store Microinstruction Notation Each microinstruction specifies its successor In microcode, next address is implicitly the next microinstruction Not necessarily at the next control store location Microassembler determines the remaining locations For branches, the condition can only differ in MSB Main loop does not reside at the first location because that is the opcode for NOP B field is source register Mem field for initiating memory operation C field sets 0,, or more destination registers ALU field determines the ALU operation JAM field determines the branching Addr field explicitly names the successor of the current microinstruction

4 Function of the Microprogram Microcode for a Mystery IJVM Instruction Contains a Main loop Fetches, decodes, and executes instructions from the program being interpreted Mic- Main loop Main PC = PC + ; fetch; goto (MBR) Increments the program counter Initiates a fetch to get the next opcode/operand Multiway branch to the current opcode H = LV MAR = MBRU + H; rd PC = PC + ; fetch H = MDR PC = PC + ; fetch MDR = MBR + H; wr; goto Main Microcode for IINC 4.constant Fall Spring Interstate November.end-constant.var w x y z.end-var.main BIPUSH 7 ISTORE x HALT.end-main IJVM Code Fragment PC = PC + ; fetch; goto (MBR) Main loop is executed Multiway branch to BIPUSH microinstruction sequence 5 6

5 SP = MAR = SP + PC = PC + ; fetch Stack Pointer and Memory Address Register updated Next byte is fetched into Memory Buffer Register Program Counter is updated Initiate a fetch operation MDR = TOS = MBR; wr; goto Main Operand is stored in Top Of Stack and Memory Data Register Next byte is fetched into Memory Buffer Register 00 Summary IJVM instructions are executed by a series of microinstructions that each take one cycle Microinstruction notation references the structures within the Mic- microarchitecture Memory operations (rd, fetch) are available at the end of the next cycle 9 0

Topics. Block Diagram of Mic-1 Microarchitecture. Review Sheet. Microarchitecture IJVM ISA

Topics. Block Diagram of Mic-1 Microarchitecture. Review Sheet. Microarchitecture IJVM ISA Topics Review Sheet Microarchitecture IJVM ISA 1 Block Diagram of Mic-1 Microarchitecture Datapath Part of CPU containing ALU, its inputs, and its outputs Purpose Implement the ISA level above it (macroarchitecture)