Wednesday, February 4, Chapter 4

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1 Wednesday, February 4, 2015 Topics for today Introduction to Computer Systems Static overview Operation Cycle Introduction to Pep/8 Features of the system Operational cycle Program trace Categories of instruction Example program Von Neumann bugs Chapter 4 Recall that we are looking at systems that use the stored program model of von Neumann. Warford (Fig. 4.1) presents an overview of a computer system having four main components: CPU (Central Processing Unit) Main memory Input Output connected by both control and data lines. An equally valid (better?) top-level model is: Address Data Control CPU Secondary Memory Input/ Output Main Memory So, for example, if the CPU wants to read the data in memory location 24, it puts the number 24 on the address lines issues a Read-from-Memory signal on the control lines The contents of memory location 24 are then sent along the data lines to the CPU. Comp 162 Notes Page 1 of 15 February 4, 2015

2 Similarly to store the number 99 into memory location 150 the CPU puts the number 99 on the data lines puts 150 on the address lines issues a Write-to-Memory signal on the control lines Looking at a CPU in more detail we can sub-divide it into two sections: Data Path Control. Data Path Control Unit Data Path The Data Path contains registers for local storage of data: the CPU can access these very quickly. A register is just an N-bit object. the Arithmetic and Logic Unit for performing operation on registers (we saw the ALU and its status bits earlier) The Control Unit The Control Unit sends control signals to the Data Path telling it what to do and when to do it. For example, certain control signals indicate which arithmetic or logical function the ALU should perform. The Control Unit gets feedback from the Data Path section, for example the values on the Status bits from the ALU. The Control unit typically contains a micromemory, clock and so on. We are not concerned with the functioning of the Control unit in this course; COMP 262 looks at how it works. Comp 162 Notes Page 2 of 15 February 4, 2015

3 The Data Path contains registers for storing data plus the Arithmetic and Logic Unit (ALU) for performing operations and appropriate connections between registers and the ALU. In the following diagram we identify registers that might exist (at least conceptually) in the Data Path. Address lines Data lines MAR MBR PC IR GP1 GPn Control lines ALU Status bits Comp 162 Notes Page 3 of 15 February 4, 2015

4 Abbreviation Register Name Purpose MAR Memory Address Register Terminator for address lines. Not normally directly accessible to programmers MBR Memory Buffer Register Terminator for data lines. Not normally directly accessible to programmers. PC Program Counter Holds address of next instruction to be executed. IR Instruction Register Holds the current instruction. Not normally directly accessible to programmers GP i General Purpose One or more registers for programmer use The size of some registers (MAR, MBR, PC) usually depend on properties of main memory: * The number of different memory addresses determines the size of the PC and the MAR because each of these registers holds a memory address. * The amount of data we can read from and write to memory at one time determines the size of the MBR because that is where the data is stored before/after a transfer. In Figure 4.2 Warford shows the registers accessible to programmers in his Pep/8 system. More on these later. So far we have just looked at the static structure of the machine. How does it run? Operation cycle Version 1.0 (generic) A top-level description of the CPU operation cycle is repeat { } fetch next instruction from memory decode it find out what kind of instruction it is execute it perform appropriate operations Comp 162 Notes Page 4 of 15 February 4, 2015

5 Operation cycle Version 2.0 (generic, more detail) The following pseudocode algorithm shows how the various registers interact (see also Fig. 4.30) Initialize PC to the address of the first instruction of the program repeat { Put Memory[PC] into IR PC = PC + 1 Decode the current instruction (in IR) what does it do? Execute the current instruction } until IR = "Halt" The PC has to be incremented after we fetch an instruction otherwise we would fetch the same instruction over and over again. Operation cycle Version 2.1 (generic, a little more detail) Knowing about the functions of the registers we can expand Put Memory{PC] into IR Initialize PC to the address of the first instruction repeat { Put PC into MAR Issue memory read signal; wait until read complete Put MBR into IR PC = PC + 1 Decode the current instruction (IR) Execute the current instruction } until IR = "Halt" When we have looked at the Pep/8 architecture we will devise an operation cycle specifically for the Pep/8 machine. Comp 162 Notes Page 5 of 15 February 4, 2015

6 Pep/8 (Warford's Virtual Machine Environment) Memory (see Fig 4.3??!) Memory is 64K bytes. Only about 2% of this is reserved for the operating system. Memory is byte-addressable so addresses are 16 bits long (64K = 2 16.) Addresses range from (decimal) which is 0..FFFF in hex A diagram of the memory (better than Fig 4.3 and Fig 4.4) is the following. Each addressable cell is an 8-bit byte FFFD FFFE FFFF The Pep/8 CPU (Fig 4.2) The Pep/8 CPU has a status register holding NZVC (Negative, Zero, overflow and Carry) bits from the ALU. (We have seen that these bits are set as a side-effect of ALU operations.) only two general purpose registers: o Register A (accumulator) o Register X (index). Each register is 16 bits long. Real computers will usually have many more general purpose registers. For many purposes the two registers have the same properties but it turns out that Register X has additional uses that we will see later. stack pointer (SP). The stack is in important run-time structure in the memory. The SP register holds the address of the item at the top of the stack. Comp 162 Notes Page 6 of 15 February 4, 2015

7 Pep/8 instructions Instructions are either 1 byte or 3 bytes long (this means the Instruction Register is 24 bits long to hold the longest possible instruction. The first (possibly only) byte of an instruction * will contain The Opcode (operation code) This indicates what type of operation the instruction performs. It varies in size from 4 bits to 8 bits. Opcodes can be thought of as a variable-length code; they must be unambiguous so that this byte can only be decoded one way by the CPU. * may contain (depending on the nature of the instruction) A 1-bit register number (r) to indicate if using register A or register X A 3-bit addressing mode (aaa) or a 1-bit addressing mode (a) (3-byte instructions only) this indicates how to use the following 2 bytes). A 3-bit number (nnn) used for various purposes A 2-bit number (nn) used for various purposes. The second and third bytes of an instruction (if present) combine to form a 16-bit number that is used in various ways that we will see later. See Figure 4.6 for a list of machine code instructions for Pep/8. Pep/8 programs Pep/8 programs always occupy locations 0, 1, 2, in the memory and the instruction at location 0 is always the first one executed when the program runs. The following is therefore a Pep/8- specific operation cycle (see also Fig. 4.31) Comp 162 Notes Page 7 of 15 February 4, 2015

8 Operation cycle Version 3.0 (Pep/8 specific) pc = 0 Repeat { firstbyte = memory[pc] pc = pc + 1 if (a 3-byte instruction) // determined by opcode bits { get next 2 bytes: mem[pc], mem[pc+1] pc = pc + 2 form two bytes into 16-bit integer (N) } action = function (opcode, register, mode, N) } until opcode=stop With this algorithm and the list of instructions in Figure 4.6 we can trace a program to see what it does. Example Suppose the first 8 bytes of the Pep/8 memory are as follows Address Contents (hex) 0 C A Here is how the program would run (note the updating of the PC) PC 0 Fetch byte 0 and update PC. In hex the byte is it is C0, in binary it is Decode the instruction. The opcode byte must match uniquely with one of the patterns in Fig 4.6. In this case the match is with 1110 r aaa Load register r from memory It is not a one-byte unary instruction so get the next two bytes (from addresses 1 and 2) and update the PC. These two bytes are the operand; in hex the operand is 0007 Comp 162 Notes Page 8 of 15 February 4, 2015

9 3 Execute the instruction. Register is A (r=0). Operand is aaa=000 The aaa bits being 000 indicates that the 0007 is the operand of the instruction (rather than, for example, the address of the operand). So this instruction loads the number 0007 into register A Register A Fetch byte 3 and update PC. In binary the byte fetched (1A) is Decode the instruction. It is unary "negate register" r 4 Execute the instruction. Register is A (r=0). So this instruction negates register A Register A F F F 9 4 Fetch byte 4 and update PC. In binary the byte fetched (70) is Decode the instruction. It is a 3-byte "add to register" 0111 r aaa It is not a unary instruction so we get bytes 5 and 6 (0003) and update the PC. 7 Execute the instruction. Register is A (r=0) Operand is 0003 aaa = 000 Operand is 0003 so Register A is now FFFC (FFF ) Register A F F F C Comp 162 Notes Page 9 of 15 February 4, 2015

10 7 Fetch byte 8 and update PC. In binary the byte fetched (00) is Decode the instruction. It is unary STOP 9 Execute the instruction stop the CPU Pep/8 users can enter either assembly code programs (discussed in Chapter 5) or programs in hexadecimal (Chapter 4). The former have to be assembled then loaded into the Pep/8 memory. The latter just need to be loaded. More on this later. The Pep/8 Instruction set Next: look at briefly at some of the instructions in the Pep/8 instruction set. There are 39 instructions in total. We can group them into 6 categories Category Number in this category Examples Stop 1 Stop Data movement 6 Load register from memory, store byte to memory Arithmetic/Logical 13 Add location to register, Negate register Input/Output 5 Output character, input decimal number Flow of Control 12 Branch if overflow Other 2 No operation Comp 162 Notes Page 10 of 15 February 4, 2015

11 Category 1: Stop/Halt instructions Every instruction set needs one instruction that stops the CPU. In Pep/8 the STOP instruction is opcode (Pep/8 is a virtual environment so when the Pep/8 program terminates, it just returns control to the user window.) is a good choice for the opcode for the STOP instruction. Many architectures use for the STOP/HALT instruction. This is because if the user forgets to include STOP in the program it will continue to execute memory locations but will probably soon encounter one containing zero and stop. Category 2: Data movement The user program (instructions and data) is in main memory but the circuits that perform arithmetic operations are in the CPU. They take inputs from registers and return restuls to registers. Thus we need instructions that move data between main memory and the CPU registers. In general, at the machine level, "load" = copy data from memory to a CPU register - see example program above "store" = copy data from a CPU register to memory. In each case the movement is only a copy operation like an assignment statement in a highlevel language - the source operand is left unchanged. Prior data in the destination location is overwritten. Computers like Pep/8 that have relatively few different instructions typically do not have instructions that move data from memory-to-memory (these are less common now anyway for efficiency reasons). There are only two Pep/8 instructions that move data from one register to another (MOVSPA and MOVFLGA) and neither is used much. Example data movement instructions. Suppose we have the following (hex) values in memory: Address Contents F 18 1C A 47 1B 32 Comp 162 Notes Page 11 of 15 February 4, 2015

12 and Register A containing 46 1A The instruction Load Register A from 18 results in Register A changing to 1C 55 Note: (1) Old data in Register A is overwritten (2) Pep/8 is a "big-endian" machine - in a multi-byte data object, such as the 16-bit word in the example above, the most significant part is stored in the lowest address. On a "little-endian" machine it is the other way round, Register A would be 551C. (3) In the Pep/8 system we can treat any pair of adjacent memory locations as a word; this is not necessarily true on all real computers. Pep/8 has instructions (such as the one above) for moving words (16-bit objects) and bytes (8-bit objects). Usually we deal with words because registers are 16 bits long. Loadbyte and storebyte are the instructions for moving bytes. They operate on the least significant half of a register leaving the most significant half unchanged. So if we follow the instruction above by Loadbyte Register A from 17 then Register A changes to 1C 5F Status bits - we will see later that many instructions affect the 4 status bits N,Z,V,C and that this is useful in creating "if" and "while" constructions. The "Load" instruction, for example, will set N if the number loaded is negative and set Z if the number loaded is zero. Category 3: Arithmetic and Logical Instructions ADD/SUB. Pep/8 has no multiply and divide instructions. If we have time later in the course we will look at register-based multiplication and division algorithms; we can do better than repeated addition/subtraction. ADD and SUB may set any of the status bits. AND/OR - logical operations. Doesn't make sense for them to affect V or C bits. SHIFT - in addition to Arithmetic Shift Right/Left (roughly equivalent to divide/multiply by 2) there are "rotate" instructions that perform circular shifts, i.e., move the bits without losing any - the bit that falls off one end goes in the other end. Comp 162 Notes Page 12 of 15 February 4, 2015

13 NOT/NEGATE - note the difference between these two. The former is a logical operation, the latter is arithmetic. The former gives you the one's complement, the latter gives you the two's complement. (Negating what number will set the V bit?) Category 4: Input/Output Input/output is actually quite complicated, even in Pep/8, but at the machine-code level there are simply two instructions: input a character output a character. These are the only input/output instructions provided at the machine level. At the assembly code level, there are three higher-order instructions: input a decimal number output a decimal number output a string We will see later how these are processed by the Operating System. Category 5: Flow of Control There are instructions that alter the flow of control so we are not limited to programs that begin at location 0 and proceed sequentially until a STOP instruction. Some of the instructions use the status bits to determine whether to transfer control to a particular location. There are also instructions that implement a simple function/subroutine mechanism. More on this when we get to Chapter 5. The number of instructions in this category could be reduced without affecting our ability to implement algorithms. Category 6: Other Sometimes it is useful to have an instruction that does nothing makes no change to memory, registers or status bits. We can use such an instruction to overwrite code and effectively delete that code without having to modify other instructions in the program. Pep/8 also allows us to modify the operating system to cause the NOP opcodes to do something more useful. Comp 162 Notes Page 13 of 15 February 4, 2015

14 In Fig is a simple program that outputs "Hi". What would happen if the programmer forgot to include a STOP instruction in this program, that is, if the memory were Location Contents Crashes after outputting Hi why? Answer: 48 is one of the few byte values that is not a valid opcode von Neumann "bugs" (p. 174 ) Because a program s instructions and data are stored in the same memory, it is possible to execute a data location as an instruction this is sometime done accidentally if we forget to include a STOP/HALT instruction in our program (see example above) or put it in the wrong place.. to treat an instruction as data. We may wish to do this deliberately see later. However, it is not considered good programming practice. Data as instruction In the following program, the programmer put STOP in the wrong place. The translation is lda 0xFFFF,I ; load all 1s anda 6,d ; now AND with 0400 (stored at location 6).word 0x0400 stop ; this should be before the data not after.end Comp 162 Notes Page 14 of 15 February 4, 2015

15 Location Contents 0 C0 1 FF 2 FF When the program runs It executes C0 FF FF ; loads register A with all 1 s Then ; ANDs with the contents of location 6 ( 0400) Then ; the data and the following byte is interpreted as the instruction BR 0 ; branch (jump) to location 0 so the program branches back to location 0 and loops forever. Instruction as data See Fig 4.36 where an ADD instruction is changed to a SUB instruction. Reading: Read up to p You can skim the step-by-step details of how particular instructions work. Next we will finish Chapter 4 and begin looking at assembly language in Chapter 5. Comp 162 Notes Page 15 of 15 February 4, 2015

Wednesday, September 13, Chapter 4

Wednesday, September 13, Chapter 4 Wednesday, September 13, 2017 Topics for today Introduction to Computer Systems Static overview Operation Cycle Introduction to Pep/9 Features of the system Operational cycle Program trace Categories of