SCRAM Introduction. Philipp Koehn. 19 February 2018
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1 SCRAM Introduction Philipp Koehn 19 February 2018
2 This eek 1 Fully work through a computer circuit assembly code Simple but Complete Random Access Machine (SCRAM) every instruction is 8 bit 4 bit for op-code: 9 different operations (of 16 possible) 4 bit for address: 16 bytes of memory Background reading on web page: "The SCRAM"
3 Operations 2 Operation Code Description HLT 0000 Halt, stop execution LDA 0001 Load value from memory into accumulator LDI 0010 Indirectly load value from memory into accumulator STA 0011 Store value from accumulator into memory STI 0100 Indirectly store value from accumulator into memory ADD 0101 Add value from memory to accumulator SUB 0110 Subtract value from memory from accumulator JPM 0111 Jump to specified address JPZ 1000 Jump to specified address if zero flag is set
4 Indirect Load? 3 LDA x loads the value from address x LDI x looks up the value at address x treats that value as an address loads the value at that address Indirect load = use of pointer variable
5 Instruction Encoding 4 Instruction Data LDA 5 Load contents from address 5 into memory
6 A Simple Program 5 Address Code Meaning op-code data operation data LDA ADD STA JMP DAT DAT 1 Note: DAT is not a real instruction Produces sequence of numbers: 0, 1, 2, 3, 4,..., 255, 0,...
7 6 components
8 Memory 7 4 bits to address memory 16 different values 16 byte address space e need to build circuitry to retrieve and store values
9 Registers 8 Accumulator (AC) can be directly accessed from logic units used to store the results of computations Program counter (PC) memory address of current instruction Instruction register (IR) contains current instruction breaks it down into operation code Memory registers memory access register (MAR): address to retrieve value memory buffer register (MBR): retrieved value
10 Arithmetic Logic Unit (ALU) 9 Can do addition and subtraction Operands operand 1: accumulator operand 2: adress specified in instruction result: accumulator Zero flag: Carry flag: result of operation is zero operation results in overflow / underflow
11 Program Counter 10 4 bit current memory address of instruction Typically increased by 1 during each instruction execution Can also be changed by jump instructions (JMP, JPZ)
12 Control Logic Unit 11 Decodes the op code Selects instruction logic Instruction logic: microprogram (sequence of register transfers) More detail on that in a bit...
13 Putting it All Together Memory Program Counter (PC) Memory access register (MAR) Instruction Register (IR) Memory buffer register (MBR) Accumulator (A) Control Logic Unit (CLU) Arithmetric Logic Unit (ALU)
14 13 memory
15 16x8 Bit RAM 14 A DI 16x8 RAM DO 16 byte of memory Inputs address (A) data in (DI) write flag () Output data out (DO)
16 Memory with its Registers 15 MAR A 16x8 RAM DI DO MBR Memory address register (MAR) Memory buffer register (MBR) Each of them has a write flag (there will be a few more of them...)
17 16 instruction fetch
18 Program Counter 17 PC INC MAR A DI 16x8 RAM DO MBR Program counter contains address of current instruction This address needs to be passed to MAR Program counter also needs an easy way to be incremented
19 Instruction Register 18 PC INC MAR A DI 16x8 RAM DO MBR IR Content of memory (MBR) is transferred to instruction register
20 Instruction Fetch 19 Program counter (PC) contains address of current instruction Step 1: Step 2: Step 3: Step 4: copy PC value to memory access register (MAR) retrieve address value into memory buffer register (MBR) copy MBR value into instruction register (IR) increase PC These copy instructions are triggered by write flags
21 MAR PC 20 PC INC MAR A DI 16x8 RAM DO MBR IR Copy PC value to memory access register (MAR)
22 MBR M 21 PC INC MAR A DI 16x8 RAM DO MBR IR Retrieve address value into memory buffer register (MBR)
23 IR MBR 22 PC INC MAR A DI 16x8 RAM DO MBR IR Copy MBR value into instruction register (IR)
24 PC PC PC INC MAR A DI 16x8 RAM DO MBR IR Increase PC
25 Micro Program 24 e can write these steps in a register transfer language Time Command t 0 MAR PC t 1 MBR M t 2 IR MBR t 3 PC PC + 1 Execution in time steps t n triggered by the clock
26 Parallel Execution 25 Increase of the program counter is independent from retrieving data from memory These steps can be parallized New micro program Time Command t 0 MAR PC t 1 MBR M, PC PC + 1 t 2 IR MBR
27 MBR M, PC PC PC INC MAR A DI 16x8 RAM DO MBR IR Parallel execution of memory retrieve and program counter increase
28 27 control logic unit
29 Control Logic Unit 28 PC INC MAR A DI 16x8 RAM DO MBR C IR D Decoder Instruction: op-code and data Q Control Logic Unit Control logic unit receives operation code Op-code is decoded into 9 different operations
30 Control Logic Unit 29 PC INC MAR A DI 16x8 RAM DO MBR C IR D Decoder Q Control Logic Unit INC NOT T CLEAR Time step needs to be increased or cleared to 0 after each micro command
31 Control Logic Unit 30 PC INC MAR A DI 16x8 RAM DO MBR C IR D Decoder Q Control Logic Unit T Decoder INC NOT T CLEAR Time step triggers one command line in control logic unit
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