S7-400H Instruction List

Transcription

1 41-5H PN/DP, 414-5H PN/DP, 416-5H PN/DP, 417-5H PN/DP 03/01 A5E

2 Copyright Siemens AG 01 All rights reserved The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG Industry Sector Postfach 4848, D-9037 Nürnberg Siemens Aktiengesellschaft Disclaimer of Liability We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed. Siemens AG 01 Subject to change without prior notice. A5E

3 Contents Applicability... 5 Address Identifier and Parameter Ranges... 6 Constants and Ranges... 9 Abbreviations Registers... 1 Examples of Addressing Examples of how to calculate the pointer Execution Times with Indirect Addressing Examples of Calculations... 1 List of Instructions... 3 Bit Logic Instructions...4 Bit Logic Instructions with Parenthetical Expressions...7 ORing of AND Instructions...9 Logic Instructions with Timers and Counters...30 Word Logic Instructions with the Contents of Accumulator Evaluating Conditions Using AND, OR and EXCLUSIVE OR...34 Edge-Triggered Instructions...37 Setting/Resetting Bit Addresses...38 Instructions Directly Affecting the RLO...40 Timer Instructions...41 Counter Instructions...44 Load Instructions...46 Load Instructions for Timers and Counters...5 Transfer Instructions...53 Load and Transfer Instructions for Address Registers...56 Load and Transfer Instructions for the Status Word...58 Load Instructions for DB Number and DB Length...59 Integer Math (16 Bits)...60 Integer Math (3 Bits)...6, 03/01, A5E

4 Floating-Point Math (3 Bits)...64 Square Root and Square Instructions (3 Bits)...66 Logarithmic Function (3 Bits)...67 Trigonometrical Functions (3 Bits)...68 Adding Constants...69 Adding Using Address Registers...70 Comparison Instructions (16-Bit Integers)...71 Comparison Instructions (3-Bit Integers)...7 Comparison Instructions (3-Bit Real Numbers)...73 Shift Instructions...74 Rotate Instructions...76 Accumulator Transfer Instructions, Incrementing and Decrementing...77 Program Display and Null Operation Instructions...78 Data Type Conversion Instructions...79 Forming the Ones and Twos Complements...8 Block Call Instructions...83 Block End Instructions...86 Exchanging Data Blocks...87 Jump Instructions...88 Instructions for the Master Control Relay (MCR)...93 Oganization Blocks (OB)...95 Function Blocks (FB) Functions (FC) and Data Blocks (DB) System Functions...10 System Function Blocks...10 Sublist of the System Status List (SSL) Index of Instructions , 03/01, A5E

5 Applicability This list of instructions applies to the s listed below. Name 41-5H PN/DP 414-5H PN/DP 416-5H PN/DP 417-5H PN/DP Order number 6ES7 41 5HK06 0AB0 6ES HM06 0AB0 6ES HS06 0AB0 6ES HT06 0AB0, 03/01, A5E

6 Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges Addr. ID Parameter Range 41-5H 414-5H 416-5H 417-5H Q 1) 0.0 to to to to Output (in PIQ) QB 1) 0 to 55 0 to 55 0 to to 103 Output byte (in PIQ) QW 1) 0 to 54 0 to 54 0 to 10 0 to 10 Output word (in PIQ) QD 1) 0 to 5 0 to 5 0 to to 100 Output double word (in PIQ) DBX 0.0 to to to to Data bit in DB DB 1 to to to to Data block DBB 0 to to to to Data byte in DB DBW 0 to to to to 6553 Data word in DB DBD 0 to to to to Data double word in DB DIX 0.0 to to to to Data bit in instance DB DI 1 to to to to Instance data block DIB 0 to to to to Data byte in instance DB DIW 0 to to to to 6553 Data word in instance DB DID 0 to to to to Data double word in instance DB Description 1) Default setting can be changed, see Technical Specifications, 03/01, A5E

7 Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges, continued Address Identifier and Parameter Ranges, continued Addr. ID Parameter Range 41-5H 414-5H 414-5H 417-5H I 1) 0.0 to to to to Input (in PII) IB 1) 0 to 55 0 to 55 0 to to 103 Input byte (in PII) IW 1) 0 to 54 0 to 54 0 to 10 0 to 10 Input word (in PII) ID 1) 0 to 5 0 to 5 0 to to 100 Input double word (in PII) L 1) 0.0 to to to to Local data LB 1) 0 to to to to 3767 Local data byte LW 1) 0 to to to to 3766 Local data word LD 1) 0 to to to to 3764 Local data double word M 0.0 to to to to Bit memory MB 0 to to to to Bit memory byte MW 0 to to to to 1638 Bit memory word MD 0 to to to to Bit memory double word Description 1) Default setting can be changed, see Technical Specifications, 03/01, A5E

8 Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges, continued Address Identifier and Parameter Ranges, continued Addr. ID Parameter Range 41-5H 414-5H 414-5H 417-5H Description PQB 0 to to to to Peripheral output byte (direct I/O access) PQW 0 to to to to 1638 Peripheral output word (direct I/O access) PQD 0 to to to to Peripheral output double word (direct I/O access) PIB 0 to to to to Peripheral input byte (direct I/O access) PIW 0 to to to to 1638 Peripheral input word (direct I/O access) PID 0 to to to to Peripheral input double word (direct I/O access) T 0 to to to to 047 Timer C 0 to to to to 047 Counter, 03/01, A5E

9 Constants and Ranges Constants and Ranges Constant Range Description B(b1,b) - Constant, or 4 bytes B(b1,b,b3,b4) D# Date - IEC date constant L# Integer - 3-bit integer constant P# Bit pointer - Pointer constant S5T# Time value - S7 time constant 1) T# TIme value - Time constant TOD# Time value - IEC time constant C# Count value - Counter constant (BCD code) #n - Binary constant B#16# W#16# DW#16# - Hexadecimal constant 1) For loading of S7 timers, 03/01, A5E

10 Abbreviations Abbreviations The following abbreviations and mnemonics are used in the Instruction List: Abbrev. Description Example k8 8-bit constant 3 0 to 55 k16 16-bit constant to k3 3-bit constant to i8 8-bit integer to + 17 i16 16-bit integer to i3 3-bit integer to m Pointer constant P#40.3 n Binary constant p Hexadecimal constant EA1 Label Symbolic jump address (max. 4 characters) DESTINATION a Byte address, 03/01, A5E

11 Abbreviations Abbreviations, continued Abbreviations, continued Abbrev. Description Example b Bit address c Address area I, Q, M, L, DBX, DIX d Address in: MD, DBD, DID or LD e Number in: MW, DBW, DIW or LW f Timer/counter No. g Address area IB, QB, PIB, PQB, MB, LB, DBB, DIB h Address area IW, QW, PIW, PQW, MW, LW, DBW, DIW i Address area ID, QD, PID, PQD, MD, LD, DBD, DID q Block No., 03/01, A5E

12 Registers Registers ACCU1 to ACCU4 (3 Bit) The accumulators are registers for processing bytes, words or double words. The address identifiers are loaded into the accumulators, where they are logically gated. The result of the logic Instr. (RLO) is in ACCU1 and can be transferred from there to a memory cell. The accumulators are 3 bits long. Accumulator designations: ACCU ACCUx (x = 1 to 4) Bit 0 to 31 ACCUx-L Bit 0 to 15 ACCUx-H Bit 16 to 31 ACCUx-LL Bit 0 to 7 ACCUx-LH Bit 8 to 15 ACCUx-HL Bit 16 to 3 ACCUx-HH Bit 4 to 31 Bit, 03/01, A5E

13 Registers Adress Registers AR1 and AR (3 Bit) The address registers contain the area-internal or area-crossing pointers for instructions using indirect addressing. The address registers are 3 bits long. Die The area-internal and/or area-crossing pointers have the following syntax: Area-internal pointer: bbb bbbbbbbb bbbbbxxx Area-crossing pointer: yyyyyyyy 00000bbb bbbbbbbb bbbbbxxx Legend: b Byte address x Bit number y Area identifier (see Examples of Addressing ), 03/01, A5E

14 Registers Status word (16 Bits) The status word bits are evaluated or set by the instructions. The status word is 16 bits long. Bit Assignment Description 0 /FC First check bit 1 RLO Result of logic Instr. STA Status 3 OR Or (AND before OR) 4 OS Stored overflow 5 OV Overflow 6 CC 0 Condition code 0 7 CC 1 Condition code 1 8 BR Binary result 9 to 15 Unassigned -, 03/01, A5E

15 Examples of Addressing Examples of Addressing Addressing Examples Immediate Addressing L + 7 Load 16-bit integer constant 7 into ACCU1 L L#-1 Load 3-bit integer constant -1 into ACCU1 L # Load binary constant into ACCU1 L DW#16#A0F0BCFD Load hexadecimal constant into ACCU1 L ENDE Load ASCII character into ACCU1 L T#500 ms Load time value into ACCU1 L C#100 Load count value into ACCU1 L B#(100,1) Load -byte constant L B#(100,1,50,8) Load 4-byte constant L P#10.0 Load area-internal pointer into ACCU1 L P#E0.6 Load area-crossing pointer into ACCU1 L -.5 Load real number into ACCU1 L D# Load date L TOD 13:0:33.15 Load time of day Direct Addressing1 A I 0.0 ANDing of input bit 0.0 L IB 1 Load input byte 1 into ACCU1 L IW 0 Load input word 0 into ACCU1 L ID 0 Load input double word 0 into ACCU1 Description, 03/01, A5E

16 Examples of Addressing Examples of Addressing, continued Examples of Addressing, continued Addressing Examples Description Indirect Addressing of Timers/Counters SP T [LW 8] Start timer; the timer number is in local data word 8 CU C [LW 10] Count upwards; the counter number is in local data word 10 Area-Internal Memory-Indirect Addressing A I [LD 1] AND Instr.: The address of the input is in local data double word 1 as pointer Example: L P#. T LD 1 A I [LD 1] A I [DBD 1] AND Instr.: The address of the input is in data double word 1 of the open DB as pointer A I [DID 1] AND Instr.: The address of the output is in data double word 1 of the open instance DB as pointer A I [MD 1] AND Instr.: The address of the output is in memory double word 1 as pointer Area-Internal Register-Indirect Addressing A I [AR1,P#1.] AND Instr.: The address of the input is calculated from the pointer value in AR 1 + P#1., 03/01, A5E

17 Examples of Addressing Examples of Addressing, continued Examples of Addressing, continued Addressing Examples Area-Internal Register-Indirect Addressing Description Area Coding Area identifier (binary) hex. P I/O area I Input area Q Output area M Bit memory area DB Data area DI Instance data area L Local data area VL Predecessor local data area (access to local data of invoking block) L B [AR1,P#8.0] Load byte into ACCU1: The address is calculated from the pointer value in AR 1 + P#8.0 A [AR1,P#3.3] AND Instr.: The address of the operand is calculated from the pointer value in AR 1 + P#3.3 Addressing Via Parameters A Parameter Addressing via parameters, 03/01, A5E

18 Examples of how to calculate the pointer Examples of Addressing, continued Examples of how to calculate the pointer Example for sum of bit addresses 7: LAR1 P#8. U E [AR1,P#10.] Result: Input 18.4 is addressed (by adding the byte and bit addresses) Example for sum of bit addresses >7: L P#10.5 LAR1 U E [AR1,P#10.7] Result: Input 1.4 is addressed (by adding the byte and bit addresses with carry over), 03/01, A5E

19 Execution Times with Indirect Addressing Examples of Addressing, continued Execution Times with Indirect Addressing When using indirect addresses statement consists of two parts: Part 1: Load the address of the instruction Part : Execute the instruction In other words, when working with indirect addresses, you must calculate the execution time of an instruction from these two parts. Calculating the Execution Time The total execution time is calculated as follows: Time required for loading the address + execution time of the instruction = Total execution time of the instruction The execution times listed in the chapter entitled List of Instructions apply to the execution times of the second part of an instruction, i.e. for the actual execution of an instruction. You must then add the time required for loading the address of the instruction to this execution time (see following Table)., 03/01, A5E

20 Execution Times with Indirect Addressing The execution time for loading the address of the instruction from the various areas is shown in the following table. Addresse is in... Bit memory area M Word Double word 41-5H 414-5H 416-5H 417-5H Data block DB/DX Word Double word Local data area L Word Double word AR1/AR (area-internal) 0.0 1) 0.0 1) 0.0 1) 0.0 1) AR1/AR (area-crossing) 0.0 1) 0.0 1) 0.0 1) 0.0 1) Parameter (word)... for: Timers Counters Block calls Parameter (double word)... for Bits, bytes, words and double words Address registers AR1/AR do not need to be loaded in separate cycles for addressing, 03/01, A5E

21 Examples of Calculations Examples of Calculations You will find a few examples here for calculating the execution times for the various methods of indirect addressing. Calculating the Execution Times for Area-Internal Memory-Indirect Addressing Example: A I [DBD 1] with 414 Step 1: Load the contents of DBD 1 (time required is listed in the table on page 0) Address is in... Bit memory area M Word Double word Data block DB/DX Double word Step : AND the input addressed in this way (execution time see page 4) Typical Direct Addressing indirecte Adressing Time for IE Total execution time ns + ns ns, 03/01, A5E

22 Examples of Calculations Execution Time for Area-Crossing Register-Indirect Addressing Example: U [AR1, P#3.1]... with I 1.0 in AR1 with Step: Load the contents of AR1, and increment them by the offset 3.1 (the time required is in the table on page 19) Address is in... : : AR1/AR (Area-crossing ) : :. Step: AND link of the input addressed this way (see page 4 for the execution time 4) Direct Addressing 13.5 : Indirect Addressing Time for AI 0 + Total execution time 0 ns ns 13.5 ns, 03/01, A5E

23 List of Instructions Examples of Addressing, continued This chapter contains the complete list of instructions for the S7-400H s. The descriptions have been kept as concise as possible. You will find a detailed functional description in the various STEP 7 reference manuals. Please note that, in the case of indirect addressing (examples see page 16), you must add the time required for loading the address of the particular instruction to the execution times listed (see page 19)., 03/01, A5E

24 Bit Logic Instructions Bit Logic Instructions All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RLO from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the /FC bit is set to zero Instr. Address ID Description U/UN I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR,m] [AR1,m] [AR,m] Parameter AND/AND-NOT Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR) 1) Area-crossing (AR1) 1) Area-crossing (AR) 1) Via parameter 1) Length in words 41-5H 414-5H 416-5H 417-5H 1 ) / 1 3) / / / / / / / / / / / / / / / / / / / / / / / / / ) 3) + I, Q, M, L / DB, DI With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

25 Bit Logic Instructions, continued Bit Logic Instructions, continued Instr. Address ID Description O/ON I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR,m] [AR1,m] [AR,m] Parameter OR/OR-NOT Input/output Bit memory Local data bit Data bit Instance data bit 1) Memory-indirect, area-internal Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR) 1) Area-crossing (AR1) 1) Area-crossing (AR) 1) Via parameter 1) Length in words 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / / / / / / Status word for: O, ON BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes Yes Instruction affects: Yes Yes 1 1) ) 3) + I, Q, M, L / DB, DI With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

26 Bit Logic Instructions, continued Bit Logic Instructions, continued Instr. Address ID Description X/XN E/A a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR,m] [AR1,m] [AR,m] Parameter EXKLUSIV-OR/ EXKLUSIV-OR-NOT Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal. 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR) 1) Area-crossing (AR1) 1) Area-crossing (AR) 1) Via parameter 1) Length in words 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / / / / / / Status word for: X, XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes Yes Instruction affects: Yes Yes 1 1) + I, Q, M, L / DB, DI Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

27 Bit Logic Instructions with Parenthetical Expressions List of Instructions Bit Logic Instructions with Parenthetical Expressions Saving the RLO and OR bits and the relevant function identifier (A, AN,...) to the nesting stack. Seven nesting levels are possible per block. After the right parenthesis, the logic operation indicated by the function identifier is performed on the saved RLO and the current RLO; the current OR is overwritten with the saved OR. Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H A( AND left parenthesis AN( AND NOT left parenthesis O( OR left parenthesis ON( OR NOT left parenthesis X( EXCLUSIVE OR left parenthesis XN( EXCLUSIVE OR NOT left parenthesis Status word for: A(, AN(, O(, ON(, X(, XN( BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Yes Yes Instruction affects: , 03/01, A5E

28 Bit Logic Instructions with Parenthetical Expressions, continued List of Instructions Bit Logic Instructions with Parenthetical Expressions, continued Instr. Address ID Description ) Right parenthesis, removing an entry from the nesting stack. Length in words 41-5H 414-5H 416-5H 417-5H Status word for: ) BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: Yes 1 Yes 1, 03/01, A5E

29 ORing of AND Instructions ORing of AND Instructions The ORing of AND instructions is implemented according to the rule: AND before OR O Instr. Address ID Description ORing of AND operations according to the rule: AND before OR Length in words 41-5H 414-5H 416-5H 417-5H Status word for: O BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes Yes Instruction affects: Yes 1 - Yes, 03/01, A5E

30 Logic Instructions with Timers and Counters Logic Instructions with Timers and Counters Examining the status of the addressed timer/counter and gating the result with the RLO according to the appropriate logic function. Instr. Address ID Description A/AN T f T [e] Z f Z [e] Timer para. Counter para. AND/AND NOT Timer Timer, memory-indirect addressing Counter Counter, memory-indirect addressing Timer/counter (addressing via parameter) Length in words 1 1) / 1 1) / Execution Time ns 41-5H 414-5H 416-5H 417-5H Status word for: A, AN BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Yes Yes Instruction affects: Yes Yes Yes 1 1) + With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

31 Logic Instructions with Timers and Counters, continued List of Instructions Logic Instructions with Timers and Counters, continued Instr. Address ID Description O/ON X/XN T f T [e] Z f Z [e] Timerpara. Zählerpara. OR/OR-NOT Timer Timer, memory-indirect addr. Counter Counter, memory-indirect addressing Timer/counter (addressing via parameter) EXCLUSIVE OR/EXCLUSIVE OR NOT Length in words 1 1) / 1 1) / Execution Time ns 41-5H 414-5H 416-5H 417-5H T f T [e] Z f Z [e] Timer para. Counter para. Timer Timer, memory-indirect addr. Counter Counter, mem.-indirect addr. EXCLUSIVE OR timer/counter (addressing via parameter) Status word for: O, ON, X, XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes Yes Instruction affects: Yes Yes 1 1) + With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

32 Word Logic Instructions with the Contents of Accumulator 1 List of Instructions Word Logic Instructions with the Contents of Accumulator 1 Gating the contents of ACCU1 and/or ACCU1-L with a word or double word according to the appropriate function. The word or double word is either specified in the instruction as an address or is in ACCU. The result is in ACCU1 and/or ACCU1-L. Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H AW AND ACCU-L AW W#16#p AND 16-bit constant OW OR ACCU-L OW W#16#p OR 16-bit constant XOW EXCLUSIVE OR ACCU-L XOW W#16#p EXCLUSIVE-OR 16-bit constant Status word for: AW, OW, XOW BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Instruction affects: - Yes , 03/01, A5E

33 Word Logic Instructions with the Contents of Accumulator 1, continued Word Logic Instructions with the Contents of Accumulator 1, continued Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H AD AND ACCU AD DW#16#p AND 3-bit constant OD OR ACCU OD DW#16#p OR 3-bit constant XOD EXCLUSIVE OR ACCU XOD DW#16#p EXCLUSIVE OR 3-bit constant Status word for: AD, OD, XOD BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Instruction affects: - Yes , 03/01, A5E

34 Evaluating Conditions Using AND, OR and EXCLUSIVE OR List of Instructions Evaluating Conditions Using AND, OR and EXCLUSIVE OR All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RL from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the FC bit is set to zero. Instr. Address ID Description A/AN O/ON X/XN AND/AND NOT OR/OR-NOT EXCLUSIVE OR/ EXCLUSIVE-OR-NOT ==0 Result=0 (CC1=0 and CC0=0) >0 Result>0 (CC1=1 and CC0=0) <0 Result<0 (CC1=0 and CC0=1) <>0 Result 0 ((CC1=0 and CC0=1) or (CC1=1 and CC0=0)) Length in words 41-5H 414-5H 416-5H 417-5H Status word for: A, AN, O, ON, X, XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: - Yes Yes - - Yes - Yes Yes Instruction affects: Yes Yes Yes 1, 03/01, A5E

35 Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Instr. Address ID Description A/AN O/ON X/XN <=0 Result>=0 ((CC1=1 and CC0=0) or (CC1=0 and CC0=0)) >=0 Result<=0 ((CC1=0 and CC0=1) or (CC1=0 and CC0=0)) Length in words 41-5H 414-5H 416-5H 417-5H Status word for: A, AN, O, ON, X, XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: - Yes Yes - - Yes - Yes Yes Instruction affects: Yes Yes Yes 1, 03/01, A5E

36 Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Instr. Address ID Description A/AN O/ON X/XN Length in words 41-5H 414-5H 416-5H 417-5H UO AND/AND-NOT OR/OR-NOT EXCLUSIVE-OR/ EXCLUSIVE-OR-NOT Unordered math instruction (CC1=1 and CC0=1) OS AND OS= BR AND BR= OV AND OV= Status word for: A, AN, O, ON, X, XN BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: - Yes Yes - - Yes - Yes Yes Instruction affects: Yes Yes Yes 1, 03/01, A5E

37 Edge-Triggered Instructions Edge-Triggered Instructions The current RLO is compared with the status of the instruction or edge bit memory. FP detects a change from 0 to 1 ; FN detects a change from 1 to 0. Instr. Address ID Description FP/FN I/Q a.b M a.b L a.b 1) DBX a.b DIX a.b c [d] ) c [AR1,m] ) c [AR,m] ) [AR1,m] ) [AR,m] ) Parameter ) The positive/negative edge is indicated by RLO = 1. The bit addressed in the instruction is the auxiliary edge bit memory. Length in words 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / + + / + + / + + / + + / + + / + Status word for: FP, FN BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: Yes Yes 1 1 Unnecessary if the bit being monitored is in the process image (local data of a block are only valid while the block is running). I, Q, M, L /DB, DI + Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

38 Setting/Resetting Bit Addresses Setting/Resetting Bit Addresses Assigning the value 1 or 0 to the addressed instruction when RLO = 1. The instructions can be dependent on the MCR (see page 4). S R Instr. Address ID Description I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR,m] [AR1,m] [AR,m] Parameter Set addressed bit to 1 Set addressed bit to 0 Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR) 1) Area-crossing (AR1) 1) Area-crossing (AR) 1) Via parameter 1) Length in words 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / + + / + + / + + / + + / + + / + Status word for: S, R BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: Yes ) 3) + I, Q, M, L / DB, DI With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

39 Setting/Resetting Bit Addresses, continued Setting/Resetting Bit Addresses, continued The RLO is written to the address of the instruction. The instructions can be dependent on the MCR (see page 93). = Instr. Address ID Description I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR,m] [AR1,m] [AR,m] Parameter Assign RLO to Input/output to Bit memory to Local data bit to DData bit to Instance data bit 1) Memory-indirect, area-internal Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR) 1) Area-crossing (AR1) 1) Area-crossing (AR) 1) Via parameter 1) Length in words 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / + + / + + / + + / + + / + + / + Status word for: = BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: Yes ) 3) + I, Q, M, L / DB, DI With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

40 Instructions Directly Affecting the RLO Instructions Directly Affecting the RLO The following instructions have a direct effect on the RLO. Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H CLR Set RLO to "0" Status word for: CLR BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Instruction affects: SET Set RLO to "1" Status word for: SET BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Instruction affects: NOT Negate RLO Status word for: NOT BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Yes - Instruction affects: Yes - SAVE Save RLO to the BR bit Status word for: SAVE BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: Yes , 03/01, A5E

41 Timer Instructions Timer Instructions Starting or resetting a timer. The time value must be in ACCU1-L. The instructions are triggered by an edge transition in the RLO; that is, when the status of the RLO has changed between two calls. SP SE SD Instr. Address ID Description T f T [e] Timerpara. T f T [e] Timerpara. T f T [e] Timer para. Start timer as pulse on edge change from 0 to 1 Start timer as extended pulse on edge change from 0 to 1 Start timer as ON delay on edge change from 0 to 1 Length in words 1 1) / H 414-5H 416-5H 417-5H ) / ) / Status word for: SP, SE, SD BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

42 Timer Instructions, continued Timer Instructions, continued SS Instr. Address ID Description T T f [e] Start timer as retentive ON delay on edge change from 0 to 1 Length in words 1 1) / H 414-5H 416-5H 417-5H SF Timer para. T f T [e] Timer para. Start timer as OFF delay on edge change from 0 to ) / Status word for: SS, SF BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: ) + With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

43 Timer Instructions, continued Timer Instructions, continued Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H FR T f Enable timer for restarting on edge 1 1) / T [e] change from 0 to 1 (reset edge bit memory for starting timer) Timer para R T f Reset timer 1 1) / T [e] Timer para Status word for: FR, R BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: ) + With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

44 Counter Instructions Counter Instructions The count value must be in ACCU1-L in the form of a BCD number (0-999). 3 Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H S Z f Presetting of counter on edge change 1 1) / Z [e] from 0 to Counter para R Z f Reset counter to 0 when RLO = 1 1 1) / Z [e] Counter para CU Z f Increment counter by 1 on edge 1 1) / Z [e] change from 0 to Counter para Status word for: S, R, CU BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: ) + With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

45 Counter Instructions, continued Counter Instructions, continued Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H CD Z f Decrement counter by 1 on edge 1 1) / Z [e] change from 0 to Counter para FR Z f Enable counter on edge change from 1 1) / Z [e] 0 to 1 (reset edge bit memory for up and down counting and setting the counter) Counter para Status word for: CD, FR BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes - Instruction affects: ) + With direct instruction addressing; Address area 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

46 Load Instructions Load Instructions Loading address identifiers into ACCU1. The contents of ACCU1 are first saved to ACCU. The status word is not affected. L Instr. Address ID Description EB a AB a PEB a MB a LB a DBB a DIB a g [d] g [AR1,m] g [AR,m] B[AR1,m] B[AR,m] Parameter Load... Input byte Output byte Peripheral input byte ( 1) ) Peripheral input byte () Bit memorybyte Local data byte Data byte Instance data byte... into ACCU1 Memory-indirect, area-internal. 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR) 4) Area-crossing (AR1) 4) Area-crossing (AR) 4) Via parameter 4) Length in words 1 ) / 1 ) / 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H ) 3) 4 + Plus acknowledgment time of the I/O module (> 1 µs), bus runtimes and synchronization time in mode With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 I, Q, P, M, L / DB, DI Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

47 Load Instructions, continued Load Instructions, continued If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled. L Instr. Address ID Description IW a QW a PIW a MW a LW a DBW a DIW a h [d] h [AR1,m] h [AR,m] W[AR1,m] W[AR,m] Parameter Load... Input word Output word Peripheral input word ( 1) ) Peripheral input word () Bit memory word Local data word Data word Instance data word... into ACCU1-L 4) Memory-indirect, area-internal Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR) 4) Area-crossing (AR1) 4) Area-crossing (AR) 4) Via parameter 4) Length in words 1 ) / 1 ) / 1 ) / 1 3) / Execution time in ns 41-5H 414-5H 416-5H 417-5H ) Plus acknowledgment time of the I/O module (> 1 µs), bus runtimes and synchronization time in mode With indirect instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 I, Q, P, M, L / DB, DI Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

48 Load Instructions, continued Load Instructions, continued the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled. L Instr. Address ID Description ID a QD a PID a MD a LD a DBD a DID a i [d] i [AR1,m] i [AR,m] D[AR1,m] D[AR,m] Parameter Load... Input double word Output double word Peripheral-Input double word ( 1) ) Peripheral-Input double word () Bit memory double word Lokaldaten double word Data double word Instance data double word... into ACCU1 4) Memory-indirect, area-internal Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR) 4) Area-crossing (AR1) 4) Area-crossing (AR) 4) Via parameter 4) Length in words 1 ) / 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / / / / / / ) 3) 4 + Plus acknowledgment time of the I/O module (> 1 µs), bus runtimes and synchronization time in mode With indirect instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 I, Q, P, M, L / DB, DI Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

49 Load Instructions, continued Load Instructions, continued L L L Instr. Address ID Description k8 k16 k3 Load... 8-bit constant into ACCU1-LL 16-bit constant into ACCU1-L 3-bit constant into ACCU1 Length in words H 414-5H 416-5H 417-5H Parameter Load constant into ACCU1 (from parameter) #n Load 16-bit binary constant into ACCU1-L Load 3-bit binary constant into ACCU B#16#p Load 8-bit-hexadecimal constant into ACCU1-L W#16#p Load 16-bit hexadecimal constant into ACCU1-L DW#16#p Load 3-bit hexadecimal constant into ACCU Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

50 Load Instructions, continued Load Instructions, continued Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H L x Load 1 character xx Load characters xxx Load 3 characters xxxx Load 4 characters L D# Zeitwert Load IEC date L S5T# Zeitwert Load S7 time constant (16 bits) L TOD# Load IEC time constant Zeitwert L T# Zeitwert Load 16-bit time constant Load 3-bit time constant L C# Zählwert Load counter constant (BCD code) L B# (b1, b) Load constant as byte (b1, b) B# (b1, b, b3, b4) Load constant as 4 bytes (b1, b, b3, b4) , 03/01, A5E

51 Load Instructions, continued Load Instructions, continued Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H L P# Bi tpointer Load bit pointer L L# Integer Load 3-bit integer constant number L Real number Load floating-point number , 03/01, A5E

52 Load Instructions for Timers and Counters Load Instructions for Timers and Counters Loading a time value or count value into ACCU1. The contents of ACCU1 are first saved to ACCU. The bits of the status word are not affected. L L LC LC Instr. Address ID Description T f T [e] Timer para. Z f Z [e] Counter para. T f T [e] Timer para. Z f Z [e] Counter para. Length in words Load time value 1 1) / Load time value (addressed via parameter) Load count value 1 1) / Load count value (addressed via parameter) Load time value in BCD 1 1) / Load time value in BCD (addressed via parameter) Load count value in BCD 1 1) / Load count value in BCD (addressed via parameter) 41-5H 414-5H 416-5H 417-5H ) + With direct instruction addressing; timer/counter no. 0 to 55 Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

53 Transfer Instructions Transfer Instructions Transferring the contents of ACCU1 to the addressed operand. Note that some instructions are affected by the MCR (see page 4). The status word is not affected. T Instr. Address ID Description IB a QB a PQB MB a LB a DBB a DIB a g [d] g [AR1,m] g [AR,m] B[AR1,m] B[AR,m] Parameter Transfer contents of ACCU1-LL to... input byte output byte peripheral output byte 1) bit memory byte local data byte data byte instance data byte Memory-indirect, area internal 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR) 4) Area-crossing (AR1) 4) Area-crossing (AR) 4) Via parameter 4) Length in words 1 ) / 1 ) / 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / / / / / / ) ) 3) 4 + Plus acknowledgment time of the I/O module (> 1 µs), bus runtimes and synchronization time in mode With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 I, Q, P, M, L / DB, DI Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

54 Transfer Instructions, continued Transfer Instructions, continued If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled. T Instr. Address ID Description Length in words IW a QW a PQW a MW a LW a DBW a DIW a h [d] h [AR1,m] h [AR,m] W[AR1,m] W[AR,m] Parameter Transfer contents of ACCU1-L to... Input word Output word peripheral output word 1) Bit memory word Local data word Data word Instance data word Memory-indirect, area internal 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR) 4) Area-crossing (AR1) 4) Area-crossing (AR) 4) Via parameter 4) 1 ) / 1 ) / 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / / / / /.5 + 1) ) 3) 4 + Plus acknowledgment time of the I/O module (> 1 µs), bus runtimes and synchronization time in mode With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 I, Q, P, M, L / DB, DI Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

55 Transfer Instructions, continued Transfer Instructions, continued If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled. T Instr. Address ID Description ID a QD a PQD a MD a LD a DBD a DID a T i [d] i [AR1,m] i [AR,m] D[AR1,m] D[AR,m] Parameter Transfer contents of ACCU1 to... Input double word Output double word Periph. output double word 1) Bit memory double word Local data double word Data double word Instance data double word Memory-indirect, area internal 4) Register-ind., area-internal (AR1) 4) Register-ind., area-internal (AR) 4) Area-crossing (AR1) 4) Area-crossing (AR) 4) Via parameter 4) Length in words 1 ) / 1 ) / 1 3) / 41-5H 414-5H 416-5H 417-5H / / / / / / / / / / / / / / / / / / / / / / /.5 + 1) ) 3) 4 + Plus acknowledgment time of the I/O module (> 1 µs), bus runtimes and synchronization time in mode With direct instruction addressing; Address area 0 to 17 With direct instruction addressing; Address area 0 to 55 I, Q, P, M, L / DB, DI Plus time required for loading the address of the instruction (see page 0), 03/01, A5E

56 Load and Transfer Instructions for Address Registers List of Instructions Load and Transfer Instructions for Address Registers Loading a double word from a memory area or register into address register 1 (AR1) or address register (AR). The status word is not affected. Instr. Address ID Description LAR1 LAR - AR DBD DID a m LD a MD a - DBD a DID a m LD a MD a Load contents from... ACCU1 Address register Data double word Instance data double word 3-bit constant as pointer Local data double word Bit memory double word... into AR1 Load contents from... ACCU1 Data double word Instance data double word 3-bit constant as pointer Local data double word Bit memory double word... into AR Length in words H 414-5H 416-5H 417-5H , 03/01, A5E

57 Load and Transfer Instructions for Address Registers, continued Load and Transfer Instructions for Address Registers, continued Transferring a double word from address register 1 (AR1) or address register (AR) to a memory area or register. The contents of ACCU1 are first saved to ACCU. The status word is not affected. Instr. Address ID Description TAR1 TAR CAR - AR DBD a DID a LD a MD a - DBD a DID a LD a MD a Transfer contents from AR1 in... ACCU1 Address register Data double word Instance data double word Local data double word Bit memory double word Transfer contents from AR in... ACCU1 Data double word Instance data double word Local data double word Bit memory double word Exchange the contents of AR1 and AR Length in words H 414-5H 416-5H 417-5H , 03/01, A5E

58 Load and Transfer Instructions for the Status Word Load and Transfer Instructions for the Status Word Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H L STW Load status word into ACCU Status word for: L BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Yes Yes Yes Yes Yes Yes Yes Yes Yes Instruction affects: Instr. Address ID Description T STW Transfer ACCU1 (bits 0 to 8) to the status word Length in words 41-5H 414-5H 416-5H 417-5H Status word for: T BR CC1 CC0 OV OS OR STA RLO /FC Instruction depends on: Instruction affects: Yes Yes Yes Yes Yes Yes Yes Yes Yes, 03/01, A5E

59 Load Instructions for DB Number and DB Length Load Instructions for DB Number and DB Length Loading the number/length of a data block into ACCU1. The old contents of ACCU1 are saved to ACCU. The status word is not affected. Instr. Address ID Description Length in words 41-5H 414-5H 416-5H 417-5H L DBNO Load number of data block L DINO Load number of instance data block L DBLG Load length of data block into byte L DILG Load length of instance data block into byte , 03/01, A5E