קורס SystemVerilog Essentials Simulation & Synthesis.. SystemVerilog

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1 קורס SystemVerilog Essentials Simulation & Synthesis תיאור הקורס קורסזהמספקאתכלהידעהתיאורטי והמעשילתכנוןרכיביםמתכנתיםבעזרתשפתהסטנדרט. SystemVerilog הקורס מעמיק מאוד ונוגע בכל אספקט של הסטנדרט במסגרת הנושאים הנדרשים בתעשייה. הקורסמשלב 50% תיאוריהו- 50% עבודהמעשיתבכלמפגש. המעבדותמכסותאתכלהחומר התאורטיומשלבות חשיבהותכנוןדיגיטאלימעשי. שפתSystemVerilog הינהשידרוגרצינילשפת Verilog וכוללת הרחבותמשמעותיותלתכנון אבסטרקטי, תוכניותבדיקה, APIs פורמליםומבוססישפת C. שפתSystemVerilog מגדירה, בנוסף, שכבותחדשותברובדהסימולציהשלשפת.Verilog הרחבותאלו מספקותיכולותמשמעותיות חדשותהןלמתכנןוהןלמהנדס הוריפיקציהוהארכיטקט, מאפשרותעבודתצוותטובהיותר וסדרבין אנשיםשוניםבפרוייקט. הקורסמניח שהמשתתףהינובעלידעוניסיוןבשפת.Verilog הקורס מתמקד בלימודמתודימעמיקשל הרחבותשפת VerilogSystem עלכללמרכיביה, משלב כתיבתתכניותבדיקה ושימושמעשיבכליסימולציה וסינתזה, ודגשעל צורתכתיבתקודלתכניות לסימולציהלעומתתכניותלסינתזה. הקורסכוללפרוייקט קטןמעשיהמשלבאתרובהחומרהנלמד. אורך הקורס 4 ימים בסיום הקורס מטרות שיושגו הכרת ההרחבותשלשפת SystemVerilog לשפתVerilog שימושבמרחבההגדרותשל SystemVerilog שימושב- Enumerated Type וב- User Defined שימושבמערכים,,Structures ו- Unions הרחבתהשימושבפונקציות,,Tasks ובלוקיםפרוצדורליים שימושבאופרטוריםחדשים ופקודותלולאהמורחבותבשפה כתיבתמכונותמצביםבשפת SystemVerilog בנייתהיררכיהבשפת SystemVerilog שימושבממשקישפת SystemVerilog

2 אוכלוסיית היעד מהנדסיחומרה אותוכנהבעליידעבשפתVerilog, הרוצים לשדרגאתיכולותיהםבעזרתשפת.SystemVerilog מהנדסימערכתהרוצים לשדרגאתהידעהמקצועישלהם. כלי פיתוח בקורס סימולטור HDL) (Modelsim or Active סינטיסייזר Pro) (Quartus II integrated synthesis, Precision or Synplify.1.2 תכנית הלימוד Day #1 Introduction to SystemVerilog o SystemVerilog history and revisions o Key SystemVerilog enhancements for hardware design SystemVerilog Language New Declarations o Package Package definition Referencing package contents o $unit Coding guidelines SystemVerilog identifier search rules Source code order Coding guidelines for importing packages into $unit o Declarations in unnamed statement blocks o Simulation time units and precision SystemVerilog Literal Values & Built-in Data Types o Enhanced literal value assignments o `define enhancements o Variables

3 Object types and data types 4-state variables 2-state variables Explicit and implicit variable and net data types o Using 2-state types in RTL models 2-satte type characteristics 2-state types versus 2-state simulation Using 2-state types with case statements o Relaxation of type rules o Signed and unsigned modifiers o Static and automatic variables Static and automatic variable initialization for automatic variables Guidelines for using static and automatic variables o Deterministic variable initialization Initialization determinism Initializing sequential logic asynchronous inputs o Type casting Static casting Dynamic casting o Constants SystemVerilog User-Defined & Enumerated Types o User-defined types Local typedef definitions Shared typedef definitions Naming convention for user-defined types o Enumerated types Enumerated type label sequences Enumerated type label scope Enumerated type values Base type of enumerated types Typed and anonymous enumerations Strong typing on enumerated type opertaions Casting expressions to enumerated types Special system task and methods for enumerated types Printing enumerated types

4 SystemVerilog Arrays, Structures, and Unions o Structures Structures declarations Assigning values to structures Packed and unpacked structures Passing structures through ports Passing structures as arguments to tasks and functions o Unions Unpacked unions Tagged unions Packed unions Using structures and unions o Arrays Unpacked arrays Packed arrays Using packed & unpacked arrays Initializing arrays at declaration Assigning values to arrays Copying arrays Copying arrays and structures using bit-stream casting Arrays of arrays Using user-defined types with arrays Passing arrays through ports and to tasks and functions Arrays of structures and unions Arrays in structures and unions o The foreach array looping construct o Array querying system functions o The $bits sizeof system function o Dynamic arrays, associative arrays, sparse arrays and strings

5 Day #2 SystemVerilog Procedural Blocks o Verilog general purpose always procedural block o SystemVerilog specialized procedural blocks Combinational logic procedural blocks Latched logic procedural blocks Sequential logic procedural blocks SystemVerilog Tasks & Functions o Implicit task and function statement grouping o Returning function values o Returning before end of tasks and functions o Void functions o Passing task/function arguments by name o Enhanced function formal arguments o Functions with no formal arguments o Default formal argument direction and type o Default formal argument values o Arrays, structures and unions as formal arguments o Passing argument values by reference instead of copy o Named task and function ends o Empty tasks and functions SystemVerilog Procedural Statement o New operators Increment and decrement operators Assignment operators Equality operators with don t care wildcards Set membership operator (inside) o Operand enhancements Operations on 2-state and 4-state types Type casting Size casting Sign casting o Enhanced for loops Local variables within for loop declarations Multiple for loop assignments Hierarchically referencing variables declared in for loops

6 o Bottom testing do while loop o The foreach array looping construct o New jump statements The continue statement The break statement The return statement o Enhanced block names o Statement labels o Enhanced case statements Unique case decisions Priority case statements Unique and priority versus parallel_case and full_case o Enhanced if else decisions Unique if else decisions Priority if decisions Day #3 SystemVerilog Finite State Machines Modeling o Representing state encoding with enumerated types o Reversed case statements with enumerated types o Enumerated types and unique case statements o Specifying unused state values o Assigning state values to enumerated type variables o Performing operations on enumerated type variables o Using 2-state types in FSM models o Synthesis guidelines SystemVerilog Design Hierarchy o Module prototypes Prototype and actual definition Avoiding port declaration redundancy o Named ending statements Named module ends

7 Named code block ends o Nested module declarations Nested module name visibility Instantiating nested modules Nested module name search rules o Simplified netlists of module instances Implicit.name port connections Implicit.* port connection o Net aliasing Alias rules Implicit net declarations Using aliases with.name and.* o Passing values through module ports All types can be passed through ports Module port restrictions in SystemVerilog o Reference ports Reference ports as shared variables o Enhanced port declarations Verilog-1995 port declarations Verilog-2001 port declarations SystemVerilog port declarations o Parameterized types SystemVerilog Interfaces o Interface concept Disadvantages of Verilog s module ports Advantages of SystemVerilog interfaces SystemVerilog interface contents Differences between modules and interfaces o Interface declarations Source code declaration order Global and local interface definitions o Using interfaces as module ports Explicitly named interface ports Generic interface ports o Instantiating and connecting interfaces o Referencing signals within an interface o Interface modports

8 o Using tasks and functions in interfaces Interface methods Importing interface methods for interface methods Exporting tasks and functions o Using procedural blocks in interfaces o Reconfigurable interfaces o Verification with interfaces Day #4 Behavioral & Transaction Level Modeling o Behavioral modeling o What is a transaction? o Transaction level modeling in SystemVerilog o Transaction level models via interfaces o Bus arbitration o Transactors, adapters, and bus functional models o More complex transactions Complete Design Modeled with SystemVerilog o Full small project that encapsulates all course material

SystemVerilog Essentials Simulation & Synthesis

SystemVerilog Essentials Simulation & Synthesis Course Description This course provides all necessary theoretical and practical know-how to design programmable logic devices using SystemVerilog standard