Verilog 1 - Fundamentals

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1 Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); Complex Digital Systems Arvind February 6, 2009 L02-1 Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); L02-2 1

Originally designers used breadboards for prototyping Solderless Breadboard Number of Gates in Design 10 7

2 Originally designers used breadboards for prototyping Solderless Breadboard Number of Gates in Design No symbolic execution or testing Printed circuit board tangentsoft.net/elec/breadboard.html home.cogeco.ca L02-3 HDLs enabled logic level simulation and testing Manual Gate Level Description Number of Gates in Design HDL = Hardware Description Language 10 L02-4 2

3 Designers began to use HDLs for higher level design Behavioral Algorithm Number of Gates in Design 10 7 Register Transfer Level Gate Level Manual HDL models offered precise & executable specification but the translation between the levels remained manual L HDLs led to tools for automatic translation Behavioral Algorithm Manual Register Transfer Level Logic Synthesis Gate Level Auto Place + Route HDLs: Verilog, VHDL Tools: Spice, ModelSim, DesignCompiler, Number of Gates in Design L

4 Raising the abstraction further Guarded Atomic Actions GAA Compiler Register Transfer Level Logic Synthesis Gate Level Auto Place + Route Bluespec and associated tools Number of Gates in Design L02-7 The current situation Behavioral Level Bluespec C, C++, SystemC Behavioral RTL Verilog, VHDL, SystemVerilog MATLAB Register Transfer Level Structural RTL Verilog, VHDL, SystemVerilog Logic Synthesis Simulators and other tools are available at all levels but not compilers from the behavioral level to RTL Gate Level L02-8 4

5 Common misconceptions The only behavioural languages are C, C++ RTL languages are necessarily lower-level than behavioral languages Yes- in the sense that C or SystemC is farther away from hardware No- in the sense that HDLs can incorporate the most advanced language ideas. Bluespec is a modern high-level language and at the same time can describe hardware to the same level of precision as RTL L02-9 Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); L

6 Bit-vector is the only data type in Verilog A bit can take on one of four values Value 0 1 X Z Meaning Logic zero Logic one Unknown logic value High impedance, floating An X bit might be a 0, 1, Z, or in transition. We can set bits to be X in situations where we don t care what the value is. This can help catch bugs and improve synthesis quality. L02-11 wire is used to denote a hardware net wire [15:0] instruction; wire [15:0] memory_req; wire [ 7:0] small_net; Absolutely no type safety when connecting nets! instruction memory_req instruction? small_net L

7 Bit literals 4 b10_11 Base format ( d,b,o,h ) Underscores are ignored Decimal number representing size in bits Binary literals 8 b0000_ b0xx0_1xx1 Hexadecimal literals 32 h0a34_def1 16 haxxx Decimal literals 32 d42 We ll learn how to actually assign literals to nets a little later L02-13 Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); L

8 A Verilog module has a name and a port list cout A B 4 4 adder 4 sum Ports must have a direction (or be bidirectional) and a bitwidth module adder( A, B, cout, sum ); input [3:0] A; input [3:0] B; output cout; output [3:0] sum; // HDL modeling of // adder functionality Note the semicolon at the of the port list! L02-15 Alternate syntax cout A B 4 4 adder 4 sum Traditional Verilog-1995 Syntax module adder( A, B, cout, sum ); input [3:0] A; input [3:0] B; output cout; output [3:0] sum; ANSI C Style Verilog-2001 Syntax module adder( input [3:0] A, input [3:0] B, output cout, output [3:0] sum ); L

9 A module can instantiate other modules A B adder FA FA FA FA cout S module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0(... ); FA fa1(... ); FA fa2(... ); FA fa3(... ); a b cin cout FA module FA( input a, b, cin output cout, sum ); // HDL modeling of 1 bit // full adder functionality L02-17 c Connecting modules A B adder FA FA FA FA cout S module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); Carry Chain L

10 Alternative syntax Connecting ports by ordered list FA fa0( A[0], B[0], 1 b0, c0, S[0] ); Connecting ports by name (compact) FA fa0(.a(a[0]),.b(b[0]),.cin(1 b0),.cout(c0),.sum(s[0]) ); Argument order does not matter when ports are connected by name FA fa0 (.a (A[0]),.cin (1 b0),.b (B[0]),.cout (c0),.sum (S[0]) ); Connecting ports by name yields clearer and less buggy code. L02-19 Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); L

11 A module s behavior can be described in many different ways but it should not matter from outside Example: mux4 L02-21 mux4: Gate-level structural Verilog module mux4(input a,b,c,d, input [1:0] sel, output out); wire [1:0] sel_b; not not0( sel_b[0], sel[0] ); not not1( sel_b[1], sel[1] ); wire n0, n1, n2, n3; b d a c sel[1]sel[0] and and0( n0, c, sel[1] ); and and1( n1, a, sel_b[1] ); and and2( n2, d, sel[1] ); and and3( n3, b, sel_b[1] ); wire x0, x1; nor nor0( x0, n0, n1 ); nor nor1( x1, n2, n3 ); wire y0, y1; or or0( y0, x0, sel[0] ); or or1( y1, x1, sel_b[0] ); nand nand0( out, y0, y1 ); out L

12 mux4: Using continuous assignments module mux4( input a, b, c, d input [1:0] sel, output out ); wire out, t0, t1; assign out = ~( (t0 sel[0]) & (t1 ~sel[0]) ); assign t1 = ~( (sel[1] & d) (~sel[1] & b) ); assign t0 = ~( (sel[1] & c) (~sel[1] & a) ); The order of these continuous assignment statements does not matter. They essentially happen in parallel! Language defined operators L02-23 mux4: Behavioral style // Four input multiplexer module mux4( input a, b, c, d input [1:0] sel, output out ); assign out = ( sel == 0 )? a : ( sel == 1 )? b : ( sel == 2 )? c : ( sel == 3 )? d : 1 bx; If input is undefined we want to propagate that information. L

13 mux4: Using always block module mux4( input a, b, c, d input [1:0] sel, output out ); reg out, t0, t1; Motivated by simulation a or b or c or d or sel ) t0 = ~( (sel[1] & c) (~sel[1] & a) ); t1 = ~( (sel[1] & d) (~sel[1] & b) ); out = ~( (t0 sel[0]) & (t1 ~sel[0]) ); The order of these procedural assignment statements DOES matter. They essentially happen sequentially! L02-25 Always blocks permit more advanced sequential idioms module mux4( input a,b,c,d input [1:0] sel, output out ); reg out; * ) if ( sel == 2 d0 ) out = a; else if ( sel == 2 d1 ) out = b else if ( sel == 2 d2 ) out = c else if ( sel == 2 d3 ) out = d else out = 1 bx; module mux4( input a,b,c,d input [1:0] sel, output out ); reg out; * ) case ( sel ) 2 d0 : out = a; 2 d1 : out = b; 2 d2 : out = c; 2 d3 : out = d; default : out = 1 bx; case Typically we will use always blocks only to describe sequential circuits L

14 What happens if the case statement is not complete? module mux3( input a, b, c input [1:0] sel, output out ); reg out; * ) case ( sel ) 2 d0 : out = a; 2 d1 : out = b; 2 d2 : out = c; case If sel = 3, mux will output the previous value! What have we created? L02-27 What happens if the case statement is not complete? module mux3( input a, b, c input [1:0] sel, output out ); reg out; * ) We CAN prevent creating state with a default case ( sel ) 2 d0 : out = a; statement 2 d1 : out = b; 2 d2 : out = c; default : out = 1 bx; case L

15 Parameterized mux4 module mux4 #( parameter WIDTH = 1 ) ( input[width-1:0] a, b, c, d input [1:0] sel, output[width-1:0] out ); wire [WIDTH-1:0] out, t0, t1; default value assign t0 = (sel[1]? c : a); assign t1 = (sel[1]? d : b); assign out = (sel[0]? t0: t1); Parameterization is a good practice for reusable modules Writing a muxn is challenging Instantiation Syntax mux4#(32) alu_mux (.a (op1),.b (op2),.c (op3),.d (op4),.sel (alu_mux_sel),.out (alu_mux_out) ); L02-29 Verilog Registers reg Wires are line names they do not represent storage and can be assigned only once Regs are imperative variables (as in C): nonblocking assignment r <= v can be assigned multiple times and holds values between assignments L

16 flip-flops module FF0 (input clk, input d, output reg q); posedge clk ) q <= d; next_x clk D Q X module FF (input clk, input d, input en, output reg q); posedge clk ) if ( en ) q <= d; next_x clk D Q X enable L02-31 flip-flops with reset posedge clk) if (~resetn) Q <= 0; else if ( enable ) Q <= D; synchronous reset posedge clk or negedge resetn) if (~resetn) Q <= 0; else if ( enable ) Q <= D; asynchronous reset next_x clk D Q X enable resetn What is the difference? L

17 Latches versus flip-flops module latch ( input clk, input d, output reg q ); clk or d ) if ( clk ) q <= d; module flipflop ( input clk, input d, output reg q ); posedge clk ) q <= d; Edge-triggered always block L02-33 Register module register#(parameter WIDTH = 1) ( input clk, input [WIDTH-1:0] d, input en, output [WIDTH-1:0] q ); posedge clk ) if (en) q <= d; L

18 Register in terms of Flipflops module register2 ( input clk, input [1:0] d, input en, output [1:0] q ); clk) if (en) q <= d; module register2 ( input clk, input [1:0] d, input en, output [1:0] q ); FF ff0 (.clk(clk),.d(d[0]),.en(en),.q(q[0])); FF ff1 (.clk(clk),.d(d[1]),.en(en),.q(q[1])); Do they behave the same? L02-35 yes Static Elaboration: Generate module register#(parameter WIDTH = 1) ( input clk, input [WIDTH-1:0] d, input en, output [WIDTH-1:0] q ); genvar i; generate for (i =0; i < WIDTH; i = i + 1) : rege genvars disappear after static elaboration Generated names will have rege[i]. prefix FF ff(.clk(clk),.d(d[i]),.en(en),.q(q[i])); generate L

19 Three abstraction levels for functional descriptions Behavioral Algorithm Register Transfer Level Gate Level Manual Logic Synthesis Auto Place + Route V V V Abstract algorithmic description Describes how data flows between state elements for each cycle Low-level netlist of primitive gates Next time Some examples L

Verilog 1 - Fundamentals

Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],