Index. 1=> implication operator > implication operator * See dot-starport connection

Transcription

1 Index Symbols! not operator != inequality operator 129!==not-identity operator 130!=?wildcard comparison 73 $assertoff 177 $assertvacuousott 191 $bitstoreal 46 $cast 93 $clog2 91 $finish 171 $readmembo 202 $readmemho 202 $realtobits 46 $signed 110 $unit declarations 15,24 $unsigned increment operator 112, 113, 115 += assignment operator 112 += assignment operators 115.* See dot-starport connection.name, See dot-name port connection.per_instance coverage option 186.randomize method 173, 175, 177, 181.sample method 185.sumarray method 119.sumwitht) arraymethod 121 :: scoperesolution operator. 27 ; null operation 140 <= See nonblocking assignment 62 = See blocking assignment 62 == equality operator 129 == identity operator 130 ==? wildcard comparison 73 -> blocking event trigger 131,132 -», nonblocking eventtrigger event control. 131, 49, 50, 53 { } concatenation operator 38, 206 lor operator 56 1=> implication operator > implication operator 188 ~ invertoperator 118 'timescale 195 '{ } assignment patternoperator 38, 206 '0 37 '1 37 'x 37 'z 37 Numerics 10typesof people , , 6 I-bit function return 148 A acknowledgments ix always 123 always_comb 51,53,85,95,97 always_ff 95,97,202 always_latch 51, 95, 97, 202 antecedent 188 array literals 38, 206 arraymethod operations , 121 arrayof objects 159 assert...else assertion pass statement 188 assertions.. 26, 79, 87, 89, 90, 155, 175,177, 188,189,190,192,193 assign 44,53,95,97,151 assignment operators assignment patterns 38, 206 assignment rules 35 assignments in expressions 99 asynchronous reset 60, 123 asynchronous set 60 automatic functions 22, 160, 161, 169

2 210 Verilog and SystemVeriiog Gotchas automatic package 24 automatic programs 24, 163 automatic tasks 22, 160, 161, 169 automatic variables 22, 147, 162, 164 B back-driven ports 43 begin end,wherenot to use 57, 58 binary integer 30 bit-select operation III blocking assignment ++ and-- operators assignment operators 112 correctusage 68 definition of 62 in clockdividers 65 to reset2-state models 83 to resetat timezero 126 boolean constraints 179 C case 31,76,77,79 casesensitivity 7 case statement 30 caset) inside 73 casex 72 casez 72 casting 92 casting, sign 110 ChrisSpear ix,6 clockdividers 64 clocking blocks 139 clock-to-q delay 62, 64, 66 codingguidelines 24,45 combinational logic49,52,56,57,61,62,66, 67,68,70,71,112, 116, 151 combinational nonblocking assign 66 compilation 41 compilation error8, 10, 11, 14, 17,20, 22, 25, 28,29,44,58,138,139,150,153, 154, 155, 159, 187 compilation warning 14 concatenation operator 38,206 concatenations 206 concurrent for loops 145 concurrent threads 164 conditional compilation 61, 204, 207,208 consequent 188 constructor 157, 158 context-determined operators.. 101, 105, 108 continuous assignment 44, 53, 95, 97, 151 coverage reports 182, 184, 186 covergroup argument direction 187 o decimal integer 30 decrement operator 112 dedication v default direction of task argument 158 disable 168 disable fork 166 DonMills vii dot-name portconnection II, 14,41 dot-star portconnection II, 14,41 dynamic variables, See automatic variables E Emacs 11,12,141,149 enumerated types 28, 84, 92 equality with4-statevalues 129 escaped identifiers 19,20 escaped names 19,20 eventdatatype 131, 134 exit simulation 171 explicitpackage import 28, 29 F FIFO 134 filling vectors 37 flip-flop... 20,60,62,64,82,83,124,202 floating point, See real types for loop 142, 144, 145, 147 foreach loop 142 forever loop 142 fork join 145, 167 fork join_any 172 fork join_none 164, 172 full case 74, 79 function return size 148 functional coverage 182 G get() method ' 134, 137 getcoveraget) method 182 get_inst_coverageo method 182 Golson, Steve ix, I gotcha! versus""' $assertoff disables randomization 177 $unitcompilation 49 I-bit implicit nets 13 all data in mailbox has samevalue 157 arrayliterals 38 arrayliterals versus concatenations 206 arrayof objects 159

3 Index 211 assert...else mismatch 192 assertion pass statement 188 assertions in procedural code assertions that cannotfail assignments in expressions 99 automatic variables 22 back-driven port 43 begin end in sequential logic 57 boolean constraints 179 casesensitivity 7 casezand casex 72 clockdividers 64 combinational assignment order 70 combinational nonblocking assign 66 concurrent for loops 145 context-determined operators 101 continuous assignment withdelay 151 coverage is 0% 184 coverage reportlumped together 186 coverage reports on bins 182 disable fork 166 disabling statement blocks 168 enumerated types 28 equality with4-statevalues 129 escaped names 19 eventtrigger races filling vectors 37 function return size 148 functions in combinational logic 49 hidden problems, 2-statelogic.. 88, 90, 92 hidden problems, 4-statelogic 86 implicit nets 10 incomplete decisions 74 increment operator infinite for loop 144 inputversus ref arguments literal integers 30, 32, 33, 35 localvariables 17 locked statemachines 84 mailboxes can storeany data type 137 nestedif else blocks 128 non re-entrant tasks 160 non-standard random generator 200 operation shortcircuiting 116 out-of-bounds arrayaccess 90 out-of-bounds enumerated types 92 overlapped decisions 77 package chaining 198 packages 27,28,29 part-select operation III port connections 39 premature simulation exit 171 random negative values 181 real typeson ports 46, 208 referencing loopvariable 147 resetat timezero resetting 2-state models 82 semaphores that don't wait 134 semicolons after fort) 142 semicolons afterif 140 sensitivity lists 52,56 sequential logic 54, 64 sequential logicblocking assignment 62 sequential logicresets 59 sequential logicset/reset 60 shared variables 94, 96, 164 signextension 33, 105 signedarithmetic 108 size extension 105 size mismatch in assignment. 35 statements in a class 153 taskdefaults withdefault values 150 triggering on clocking blocks 139 undetected randomization failure 175 unique casemisuse 79 unnamed blocks 25 usinginterfaces and classes 155 variable initialization 162 variables don't get randomized 173 variables in forked threads 164 zero extension 33 gotcha, definition of 3 gotcha, reasons for gotcha, summary of gotchas in book xv H handle 154,155,157,158,159,173 hard,non-standard keyword 204 hex integer 30 hidden problems, 2-statelogic 88, 90, 92 hidden problems, 4-statelogic 86 hierarchical paths... 19,20, 22, 23, 25, 27 I identifiers casesensitive 7 definition of 7 escaped 19 legal characters 19 IEEESystemVerilog standard 5 IEEEVerilog standard 5 if else 128 if else, in sequential logic 57 implication operator 188 implicit nets 13 import, explicit 28, 29

4 212 Verilog andsystemveriiog Gotchas import,package 28, 198 import, wildcard 28, 29, 198 imported package items 27 incomplete decisions 74 increment operator 112 inertial delay 152 initial 123 inside 73 interfaces 24, 96, 1SS J join_any 172 join_none 164, 172 L language-aware editor. 11,128,141,142,149 left extension, of literalvalue 34 lintcheckers.. 34, 38,44, 59,63, 77, 94, 149 literal integer, size mismatch 33, 35 literal integers 30, 32, 33, 35 localvariables 17,2S localparam 91 lockedsimulation 66, 14S lockedstatemachines 84 loosely typed 4,92, 101, 107 LRM,SystemVerilog 5 LRM, Verilog 5 M mailboxes 137, 157 memory models 202 method arguments 158 Mills,Don vii mismatch, literal valuesize 33, 35 multi-file compilation 15 multiple operations in one statement 115 N naming conventions 9, 24 negative values 181 negedge 54 nonblocking assignment correctusage 63 definition of 62 exception to using 64 incorrect usage 66 intra-assignment delay 152 to model transport delay 152 to resetat timezero 126 nonblocking eventtrigger 132 non-standard language extensions 204 o objecthandles, Seehandle 159 octalinteger 30 open-ended rangein assertions 193 operation shortcircuiting 116 or, in sensitivity lists 56 out-of-bounds arrayaccess 90 out-of-bounds enumerated types 92 p package automatic 24 package, wildcard import 28, 29, 198 packages 16,24,27,28,29,96 packages, chaining 198 parallel_case 74 parameter 91 part-select operation III portcoercion 43 portconnection rules 39 posedge 54 post-increment 113 pragmas, synthesis 74, 79 pre-increment 113 premature simulation exit 171 priority case 76 process synchronization using event types 131 usingmailboxes 137, 157 usingsemaphores 134 program automatic 24, 163 pure virtual 204 putt) method 134 R race conditions 60,62,64, 83, 112, 125, 127, 131 rand 173 randc 173 random number generator 200 randomization failure 175 randomize 173 real types 46,47, 208 real types on ports 46,208 redundant decision selection 77 re-entrant tasks 160 ref covergroup argument 187 ref task/function argument ISO, 158 reference for loopvariable 147 repeatloop 142 resetat timezero 123 resetting 2-state models reviewers ix

5 Index 213 RNG 200 rules, assignment statements 35 S scoperesolutionoperator 27 self-determined operators 101,105 semaphores 134 semicolons, after fort) 142 semicolons, after if 140 sensitivity lists arrays in 52 combinational logic 49 function calls 49 operations in 56 vectorsin separatefile compilation 15 sequential logic begin-end groups 57 blockingassignments in 62 resetting 59, 60 sensitivity list, vectorsin 54 shareddeclarations 15 sharedvariables 94, 96, 164 shift register 62 shortrealtypes 47,208 sign casting sign extension 33, 35, 36,40, 102, 105 signedarithmetic rules 108 signed literalintegers 32 signed types 181 signedness 32, 36, 107, 108, 110, III simulation lock up 66 single file compilation 15 size extension 105 solve before 204 Spear,Chris ix, 6 state machinelock up 84 statements, in a class 153 static functions 160 static tasks 160 static variables 162 SteveGolson ix, 1 structureliterals 38, 206 StuartSutherland vii, 6 sum array method 119 sum witht) array method 121 SUPERLOG 5 Sutherland, Stuart vii, 6 synchronization 131,134,137,157 synchronous reset 123 synthesis full_case pragmas 74,79 SystemVerilog Accellera3.0 standard 5 Accellera3.1 standard 5 Accellera3.la standard 5, 206, 208 bookson 6 definition of 3, 5 IEEE 1800standard 6 SystemVerilog Assertions87, 89, 90, 175,177, 188,189,190,192,193 T task and function arguments 150 time precision 195 time units 195 timeprecision 197 timeunit 197 transport delay 152 truncation assignments 35 function return 148 literal integers 33 operations 119 port connections 39, 144 try_getomethod 137 typed mailboxes U undeclared identifiers 7, 10, 13 uniquecase 31, 76, 77, 79 unnamed blocks 25, 26 unsigned literalintegers 32 unsigned types 181 uwire 44 V vacuous success 188, 191 Value ChangeDump file, See VCD var 47,208 var real 47,208 variableinitialization 162 variables, on ports 44 VeD 22,26 VERA 5 Verilog bookson 6 definition of 3, 5 IEEE 1364standard 6 LRM 5 VHDL 1,5,7 virtualinterface 155 W wait 133, 172 wait fork 172

6 214 Verilog and SystemVeriiog Gotchas whileloop 142 whitespace 19,20 wildcard comparison operator 73 wildcard package import 28,29,198 wire 13,39, 43 Z zeroextension 33, 35, 36, 40