Vidyalankar T.Y. Diploma : Sem. VI [CO/CD/CM] Advanced Microprocessor

Transcription

1 T.Y. Diploma : Sem. VI [CO/CD/CM] Advanced Microprocessor Time : 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any THREE of the following : [12] Q.1(a) (i) List all general purpose registers of and state their function [4] General Purpose Registers [Listing - 1 mark, Function - 3 marks] It consists of 4 general purpose registers EAX, EBX, ECX and EDX which are 32 bit registers. They can also be accessed as 16 bit registers AX, BX, CX, DX as well as 8 bit registers AH, AL, BH, BL, CH, CL, DH and DL. It also consists of index registers. They can be accessed as 32 bit registers SI and DI. It also consists of 3 pointers ESP (32 bit) or SP(16 bit) which points to the top of the stack, EBP (16 bit) or BP(16 bit) base pointer that is used for non-lifo access of stack and EIP (32 bit) or IP(16 bit) instruction pointer that points to the program i.e. the next instruction to be executed. Q.1(a) (ii) List any four salient features of [4] Features [Any Four - 1 mark each] i) 32 Bit Microprocessor 32 bit internal data paths, 32 Bit ALU, 32 Bit Register Set. ii) Operates on single supply voltage +5V DC. iii) 16, 20, 25 and 33 MHz clock frequencies. iv) Available as Pin PGA (Pin Grid Array) v) 32 Bit External Address. Bus 2 32 = 4 GB Memory Address Space. vi) Available in 2 Flavour SX 16 Bit Data Bus DX 32 Bit Data Bus vii) I/O operation with 16 Bit Addresses 2 16 = 64K location Input output Address Space. viii) Virtual Memory Management through segmentation and optional paging Allows 64 Virtual Address Space. ix) Supports Multitasking and protection. x) Supports external cache Memory upto 64 KB. xi) Very powerful Instruction Set. xii) 3 Modes of operation : REAL, PVAM (Protected Virtual Address Mode) and V 86 (Virtual 8086 Mode). Q.1(a) (iii)describe interrupt processing sequence in 86 microprocessor [4] Step 1: At the end of an instruction, interrupts are sampled and if enabled highest priority interrupts are recognised to be serviced. Step 2: The flag register (16 bit) is pushed onto the top of stack and stack pointer is decremented by 2. Step 3: The IF and TF flags in the flag register are reset. This disables any further interrupts. Step 4: The existing CS and IP are pushed on the top of the stack. First CS is pushed and SP is decremented by 2. Then IP is pushed and SP is further decremented by 2. Step 5: The Interrupt vector is captured and determined for the operation. (a) For NMI, it is 2 (b) For Exceptions, it is 0 4 (c) For software interrupts, it is supplied as a part of instruction itself. (d) In case of INTR, X86 processor generates 2 back to back Interrupt Acknowledge cycles. In the second cycle it is the responsibility of interrupting device to send interrupt vector on data bus D 0 D 7. 1

2 : T.Y. Diploma AMP 2 Step 6: Once the Interrupt vector is available if is multiplied by 4 and the generated address is referred to the Interrupt vector Table (IVT) Step 7: The Interrupt vector Table entry supplier new CS and IP values which are then loaded in the CS and IP registers. Step 8: As the CS and IP is then loaded with the new values next instruction is executed from CS : IP Therefore the Interrupt service Routine starts. Q.1(a) (iv) List of four salient features of Pentium Pro [4] Features of Pentium [Any Four - 1 mark each] 1) It is available as 273 pin Pin Grid Array (PGA) 2) It operates on +5V DC supply voltage/33v DC core and 5V DC input output voltage for Pentium MMX. 3) It is available in 2 flavours. Flavour Frequencies Pentium S 75, 90, 100, 120, 133, 150, 156, 180, 200 Pentium - MM X 166, 200, 233, 266 MHz 4) It is a 32-Bit Microprocessor or(32 Bit ALU, 32 Bit internal Registers, 32 Bit Data Paths) 5) It has 64 Bit External Data Bus. 6) It has 32 Bit Addresses 2 32 = 4GB Physical memory Address space. 7) It has input output space of 64K input output ports. 8) The virtual memory support is through segmentation (mandatory) and paging (optional) 64 Virtual space. 9) Supports Multitasking, Protection. 10) It is a superscalar processor with 2 Integer pipelines and 1 FPU. Q.1(b) Attempt any ONE of the following : [6] Q.1(b) (i) Draw and describe control register of micro processor. [6] [Diagram - 2 marks, Explanation - 4 marks] The has four 32 bit control registers. CR 0, CR 2, CR 3 to hold global machine status independent of executed task. The road and store instructions are available to access these registers. The control register CR 1 is reserved for use in future Intel processors. CR 0 Machine Control Register R T E M P S M P E MSW P G Paging

3 Prelim Question Paper Solution PG(Paging): The 31 st bit in CR 0 represents that the paging unit is enabled or disabled. If it is enabled or set, linear address is converted to the physical address & when it is disabled linear address is same as that of physical address. R(Reserved): The 4 th bit in CR 0 is reserved by intel. TS(Task Switiching): The 3 rd bit in CR 0 is automatically set whenever a task switch operation is performed. When one segment at one particular level can access segment present at another level processor is performing multiple tasks at that time this flag is set to me. EM(Emulate Prcocessor): The 2 nd bit in CR 0 is set when co processor software is present & when it is absent then this flag is set too. MP(Monitor Processor): The 1 st bit in CR 0 is set when coprocessor is present & when it is reset i.e. 0 then coprocessor is absent. PE(Protected Enable): The 0 th bit in CR 0 is set to 1, it indicates that the processor is working in protected mode. When it is reset, works in a real mode. CR 1 : It is a 32 bit control register used for Intel higher processor. CR 2 : Page Fault Linear Address. It is a 32 bit register which stores the linear address of last page fault. The error codes are pushed into the stack of the page cache. CR 3 : Page Directory Base Address Linear address of page fault Page Directory Base Address This is a 32 bit control register which stores page directory base address. Only upper 20 bits are utilized for generation of page directory base address, because lower 12 bits will be common, because of 4KB page size. Q.1(b) (ii) Describe the address generation process in real addressing mode of micro [6] processor. [4 marks] In the real mode 8036 works as a fast 8036 works as fast 8036 with 32 bit registers and data types. In the real mode default operand sized is 16 bit but 32 bit operands and addressing modes may be used with the help of override prefixes. After reset the starts from the memory location FFFFFFFOH under the real address mode. The segment size in real mode is 64k, hence the 32 bit effective address must be less then OOOOFFFFFH. 3

4 : T.Y. Diploma AMP In real mode, the can address at athe most 1MB of physical memory using address lines A 0 A 19. Paging unit is disabled in the real address mode. Hence real address is same as physical address. To form a physical address, segment register contents (16 bits) are shifted left by four positions & then added to 16 bit offset address. The segments in real mode can be read, written or executed i.e. no protection is available. [2 marks] Physical address formation in Real mode Real mode Q.2 Attempt any TWO of the following : [16] Q.2(a) Draw and explain GDT and LDT in processor. [8] [4 marks] 4

5 Prelim Question Paper Solution Global Descriptor tables (GDT) contains descriptors which are available to all of the tasks in a system. GDT can contain any type of segment descriptor except descriptor for servicing interrupts. Generally GDT contains code and data segments used by the operating system and task state segments, and descriptors for the LDT in a system. Local descriptor table (LDT) contain descriptors which are associated with given task. Each task has a separate LDT. The LDT may contain only code, stock, data, task gate and call rate descriptors. LDTs provide a mechanism for isolating a given task s code and data segments from the rest of operating system. A segment cannot be accessed by a task if its segment descriptor does not exist in either the current LDT or GDT. This provides both isolation and protection for a task s segments, while still allowing global data to be shared among tasks. The LDT requires a selector, refers to a LDT descriptor in the GDT. Q.2(b) Draw and describe the internal architecture of micro processor. [8] The internal architecture of consist of following units [4 marks] Central Processing Unit (CPU) Memory Management Unit (MMU) Bus Interface Unit (BIU) The central processing unit is further divided into two parts. Instruction Unit Execution Unit The instruction unit decodes the opcode bytes receive form the 16 byte instruction code queue & arranges them into 3 instruction decoded instruction queue. After decoding them they are transferred to control section for deriving necessary control signals. The execution unit has eight general purpose & eight special purpose registers which are used for handling data or calculating offset addresses. Memory Management unit consist of Segmentation Unit Paging Unit Segmentation Unit allows the use of two address comperents i.e. segment & offset segmentation unit allows a maximum size of 4 GB. The segmentation unit provides a four level of protection mechanism for protecting and isolating the systems code and data from application program. The limit and attribute PLA cheaks segment limits and attributes at segment level to avoid invalid accesses to code and data. Paging unit organizes the physical memory in terms of pages of 4 kbytes size. Each segment is divided into pages. It converts linear address into physical address. The control and attribute PLA checks the privileges at page level. Bus control unit has a prieritizer to resolver the priority of various bus requests. This controls the access of bus. The address driver drives the bus enable & address signals A 0 A 31. The pipeline and dynamic bus sizing units handle the related control signals. The 5

6 : T.Y. Diploma AMP data buffer interface the internal data bus with the system bus. [4 marks] Q.2(c) Describe virtual 8086 mode of microprocessor with suitable diagram. [8] [5 marks] The intel DX allows the execution of 8086 application programs in both real mode and in the virtual 8086 mode. Onece enters the protected mode form the real mode it can t return back to the real mode without are set operation. So we can execute 8086 programs while in protected mode. In the virtual mode 8086 can address 1mbytes of physical memory within 4 GB of address space. In this mode, the paging mechanism and protection capabilities are available at the service of programmers. In virtual memory paging unit allows only 256 pages, each of 4 kbytes. Each pages may be located anywhere within the maximum 4GB of physical memory. The virtual 8086 mode executes all programs at the privilege level 3. [3 marks] 6

7 Prelim Question Paper Solution Q.3 Attempt any FOUR of the following: [16] Q.3(a) Compare Pentium and Pentium pro (any 4 points) [4] [1 mark each] Pentium Pentium Pro 1) Does not support MMX Supports MMX 2) 5 stage pipelining 14 stage pipelining 3) More more consumption Less power consumption 4) 8KB each of code and data cache 16 KB of code and data cache 5) Does not support speculative execution Speculative execution 6) Single BTB Multiple BTB Q.3(b) List of features of RISC processor [4] [1 mark each] i) Simple Instruction set: In a RISC machine, the instruction set contains simple, basic constructions from which more complex instructions can be composed. ii) Same length instruction: Each instruction is of the same length, so that it may be fetched in a single operation. iii) Single machine cycle instruction: Most instruction complete in one machine cycle, which allows the processor to handle several instructions at the same time. 7

8 : T.Y. Diploma AMP iv) Pipelining: Massive pipelining is embedded in RISC processor. v) Very few addressing modes and formats: It has very less number of addressing mode and it supports few formats. vi) Large number of registers: The RISC design philosophy generally incorporates a layer number of register to percent in large amounts of interactions with memory. vii) Load and store architecture: In this all memory access takes place using load and store type of operations. Q.3(c) Draw labelled format of flag register. [4] [4 marks] PE = 1 VM = 0 (E flags) REA PVA V 86 PE = 0 VM = 0 (E flags) Q.3(d) Compare DOS and BIOS in terrupt. [4] [1 mark each] DOS in terrupts BIOS in terrupts i) It is a collection of proudure to perform Its function to setup hardware, load and start services such as formatting DISK, an operating system portioning DISK, reading working files ii) It contains system function such as file record management, memory management It contains default resident hardware driver for, CON, printer, AUX etc. etc. iii) User friendly Complex iv) Speed is slow Speed is high v) eg. int 21H, 22H, 23H eg. INT 10H, 12, H, 13H. Q.3(e) List any four features of sun ultra SPARC [4] [1 mark each] i) 14 stage non stalling pipeline. ii) Six execution units including two for integer, two for floating point, one for load/store and one for address generation unit. iii) It contains 32 KB L1 instruction cache, 64 KB L1 dara cache, 2KB prefetch cache and 2 KB write cache and 1MB on chip L2 cache iv) It supports instruction for multimedia. v) It stores multibyte numbers using Big endian format. vi) Supports pipelined floating point processor. Q.4(a) Attempt any THREE of the following : [12] Q.4(a) (i) State the function of following function of microprocessor [4] 1) Bε0 -Bε 3 2) D/C 3) BS 16 1) Bε0 -Bε 3 [2 marks each] BE 0 # = to BE 3 #: The four byte enable line are used for enabling four banks. Using these four enable signal lines the cpu may transfer 1byte/2bytes/3bytes/4bytes of data simultaneously. 8

9 Prelim Question Paper Solution 2) D/C The data/control output pin distinguishes between a data transfer cycle from a machine control cycle. 3) BS 16 Byte Enable Signal Data bus Signals BE D c D y 0 BE 1 D 8 D 15 BE 2 D 16 D 23 BE 3 D 24 D 31 The bus size 16 input pin allows the interfacing of 16 bit devices with the 32 bit wide data bus. Q.4(a) (ii) Describe dedicated in interrupts of X86 processor [4] [Explanation - 4 marks] Interrupt vector 0 corresponds to an exception which I caused by Divide by 0 condition encountered in the ALU of X86 processor. INT 0 is automatically called. Interrupt vector 1 is a debug exception that would be caused after the execution of each instruction int eh program. Therefore the program is said to be single stepping. The single stepping is enabled by setting Trap flag = 1. If TF = 0 single stepping exception (INTI) is not performed. Interrupt vector 2 is Hardware interrupt NMI NMI is high level triggered high priority non maskable interrupt. Interrupt Vector 3 is breakpoint. This is also a debug exception. Breakpoints can be introduced for debugging by inserting INT3 breakpoint instruction in the user programs. Interrupt Vector 4 is caused by overflow. Whenever ALU detects an overflow condition it sets Overflow flag (OF) INT4 or overflow exception can be called by executing INTO instruction. Q.4(a) (iii)state deference between com and exe [4] [1 mark each].com.exe 1) Maximum size of a program is 64 k minus No limit for program size 256 bytes for PSP (program segment Prefix) 2) Entry point for com program is PSP: 0100H Entry point is defined by END directive 3) Subroutine calls are always NEAR Subroutine calls are FAR or NEAR 4) Maximum size of com file is depend upon Maximum size of file is a size of program size of program plus header. 5).Com is machine code before execution.exe is a program after execution 6) Stack size is 64k minus 256 bytes for PSP Stack size is defined in a program with and size of executable code and data STACK directive. 9

10 : T.Y. Diploma AMP Q.4(b) Attempt any ONE of the following: [6] Q.4(b) (i) Compare RISC and CISC processor [6] [1 mark each] RISC CISC 1) Reduce instruction set computer Complex instruction set computer 2) Fast Processing slow as compare to RISC 3) Fixed instruction size Variable Instruction size 4) One machine cycle 2 10 machine cycle 5) Micro coding not required Micro coding required. 6) Sixe is small Size is big 7) Cost is less Cost is more. Q.4(b) (ii) Describe superscalar execution of Pentium processor with suitable diagram. [6] [Diagram and Explanation - 3 marks, each] Super Scalar Processing in Pentium Pentium Pipeline Stages PF = Prefcteh (Instruction Perfecting) D1 = Decode stage 1 (Branch prediction/pairing) D2 = Decode stage 2 (Control signal Generation) Ex = Execute (instruction Execution) WB = Write Back (Operand writing Back to Reg/mem) Superscalar Execution t 1 t 2 t 3 t 4 t 5 t 6 t 7 I 1 PF U D1 U D2 U EX U WB U U I 2 PF V D1 V D2 V EX V WB V V I 3 PF U D1 U D2 U EX U WB U U I 4 PF V D1 V D2 V EX V WB V V I 5 PF U D1 U D2 U EX V WB V U I 6 PF V D1 V D2 V EX V WB V V In Pentium processor, there are 2 integer pipelines. They are capable of executing instructions simultaneously as shown in the pipeline stage diagram for superscalar execution in Pentium, we can observe that at a time 2 instructions are being processes. When first 2 instructions I 1 and I 2 move on to decode 1 (D1), next 2 instructions I 3 and I 4 are prefetched simultaneously and when I 1 and I 2 move on to Decode 2 (D 2 ), I 3 and I 4 get decoded in D 1 simultaneously and at the same time I 5 and I 6 are fetched. If the instructions are pairable, they go down the U and V pipeline to get simultaneously executed. If the instructions are not pairable only 1 instruction is executed in U pipe and Pentium tries for subsequent instruction pairing. As the Pentium is capable of executing instructions simultaneously in more than one pipeline (U and V), if is called as the superscalar architecture processor. Such execution is called as superscalar exaction of instructions. 10

11 Prelim Question Paper Solution Q.5 Attempt any TWO of the following : [16] Q.5(a) Draw the architecture of Pentium processor and list features of Pentium [8] [Diagram 4 marks] Features of Pentium [Any Four - 1 mark each] 1. It is available as 273 pin Pin Grid Array (PGA) 2. It operates on +5V DC supply voltage/33v DC core and 5V DC input output voltage for Pentium MMX. 3. It is available in 2 flavours. Flavour Frequencies Pentium S 75, 90, 100, 120, 133, 150, 156, 180, 200 Pentium - MMX 166, 200, 233, 266 MHz 4. It is a 32-Bit Microprocessor or(32 Bit ALU, 32 Bit internal Registers, 32 Bit Data Paths) 5. It has 64 Bit External Data Bus. 6. It has 32 Bit Addresses 2 32 = 4GB Physical memory Address space. 7. It has input output space of 64K input output ports. 8. The virtual memory support is through segmentation (mandatory) and paging (optional) 64 Virtual space. 9. Supports Multitasking, Protection. 10. It is a superscalar processor with 2 Integer pipelines and 1 FPU. Q.5(b) List and explain any 4 file processing functions. [8] i) Function 3 ch To create a file. [1 list and explanation 1 mark] Input : AH = 3 ch DS: DS = Pointer to an ASCllZ string CX = Attribute of the file Output: AX = error codes if carry flag is set 16 bit handle if carry flag not set 11

12 : T.Y. Diploma AMP 12 ii) Function 3Dh To open a file Opens the specified file Input : AH = 3Dh DS: DX = Pointer to as ASCII path name AL = Access and sharing modes mov al, 0 ; read mov al, 1 ; write mov al, 2 ; read/write Output: AX = error codes if carry flag is set 16 bit handle if carry flag not set. iii) Function 3EH To close a file. Input: AH = 3EH BX = File handle Output: AX = error code if carry flag is set none if carry flag not set iv) Function 40H write to file Input: AH= 40H BX = file handle CX = number of bytes to wirte DS: DX = contain data to be write Output: AX= no. of bytes actually written if carry flag not set error code when carry flag is set Q.5(c) Describe following terms related to Pentium processor [8] (i) Branch Prediction [4] [4 marks] Branch prediction logic of Pentium logic of Pentium operates with a special cache of branch addresses that keeps track of 64 most recently taken branches. The branch table that keeps this information is called as 'Branch Target Buffer (BTB). It stores the source address (the address at which branch instruction appears). Target address (the address to which the branch would take place) and the branch history state bits. The branches are predated to be taken or not taken in D1 stage of pipeline. If the current state is ST (strongly taken) or WT (Weakly Taken), the branch is predicted to be taken. If the current state is WNT (Weakly Not Taken) or SNT (Strongly Not Taken) the branch is predicted not to be taken. If the branch is predicted not to be taken, prefetching continues in the same buffer source address onwards. If the branch is predicted to be taken the perfected buffer is switched and prefetching is done on target address onwards. In the execution stage (Ex), the branch is actually and if the branch is actually not taken, the state bits are downgraded. If the prediction is correct, pipeline runs smoothly. If the prediction is wrong, U pipeline incurs 3 clocks and V pipeline insures 4 clocks penalty. Branch predication logic enhances the performance of Pentium as it minimizes the pipeline problem. Q.5(c) (ii) Floating point popeline [4] The Floating point pipeline of Pentium have 8 stages. The stages are : [4 marks] PF Prefetch D1 Decode stage 1 D2 Decode stage 2 EX Execute load operands X1 FP Execution stage 1

13 Prelim Question Paper Solution X2 FP Execution stage 2 WF Write FP operands (Round/Normalize) ER Error Reporting Pentium Superscalar D2 EX WB PF D1 D2 EX WB The 8 stages in Floating point pipeline can be explained as : i) Prefetch (PF): In this stage, the operands are prefetched from the code cache into the prefetch buffers. This stage is common with U and V integer pipelines. ii) Decode Stage 1 (D1) : This stage decodes the instruction performs instruction pairing check and branch predictions. This stage is also common with U and V integer pipelines. iii) Decode stage 2(D2) : In this stage, the floating point unit generates the control signals for execution. It also generates operand addresses. iv) Execute (EX) : In this stage, FPU loads the data operands necessary for execution. v) Execute stage 1(X1) : In this stage, FPU execution begins. For addition, subtraction Mantisa shifting is carried out. For multiplication and Derision, the mantisa is multiplied or divided. For Floating point data transfers, the transfers are executed. vi) Float point Execute stage 2 (X 2 ) : For floating point mantisa addition and superscalar is carried out. For floating point multiple and dir exponent address and is carried out. For Data transfers, this stage is bypass. vii) WF (Write Floating Operands) : In this stage, the results are normalised. If necessary rounding off. viii)er (Error Reporting) : In this stage, floating point errors and exceptions are reported as numerical errors. Q.6 Attempt any FOUR of the following : [16] Q.6(a) List any four difference between real addressing mode and PVAM of [4] [1 marks each] Real Mode Protected Mode 1) It uses 20 address lines It uses 32 bit address lines 2) It access only 1MB memory It access only 4 GB memory 3) Segmentation is used Paging is used 4) Protection is not available Protection is available. 5) Sector is not required in address generation. Sector is required in address generation D2 EX X1 X2 WF ER 13

14 : T.Y. Diploma AMP Q.6(b) Explain Test and Debug register of [4] [Test register - 2 marks, Debug register - 2 marks] Debug registers provides a set of eight debug registers for hardware debugging. Debug registers DR 0 DR 3 specify the four linear breakpoint address. The two registers DR 4 and DR 5 are intel reserved. The DR 6 and DR 7 hold the breakpoint status and breakpoint control information. Test Registers Two registers are used for page cacheing called as test control and test status registers. DR 6 is a command test register and TR 7 is the data register which contains the data of the Translation look aside buffer. Fig shows debug and Test registers. 31 Debug Registers 0 Linear Breakpoint Address 0 DR 0 Linear Breakpoint Address 1 DR 1 Linear Breakpoint Address 2 DR 2 Linear Breakpoint Address 3 DR 3 Intel Reserved DR 4 Intel Reserved DR 5 Breakpoint Status DR 6 Breakpoint control DR 7 3k Test Registor (for page cache) 0 Test control TR 6 Test status TR 7 Q.6(c) Describe TLB in with suitable diagram. [4] [Diagram 2 marks explanation 2 marks] Paging is one of the memory management techniques used for virtual memory multitasking operating system. The paging mechanism provides an effective technique to manage the physical memory for for multitasking systems. The paging unit of uses a two level table mechanism to convert the linear address provided by segmentation unit into physical addresses. The paging unit handles every taks in terms of three components namely page directory, Page tables and the page itself (page frame) Fig shows how paging mechanism works. In that CR 3 is used as page directory physical base address register to store the physical starting address of the page directory. The lower 12 bits of CR 3 are always zero to align the page size (2 12 4k) 14

15 Prelim Question Paper Solution Each directory entry is of four bytes thus total of 1024 entries are allowed in directory. Page directory entry points to page tables. The following fig shows a directory entry Page Table Address OS O O D A O O U R P RESERVED S W Each page table is of 4 bytes in size and may contain a maximum of 1024 entries. Page table contain starting address of page & other statistical information about the page Page Table Address OS O O D A O O U R P RESERVED S W The upper 20 bit page frame address is combined with lower 12 bits of linear address The page tables can be shared between tasks The P bit in directory and table indicates the entry can be used in address translation. A bit indicates the entry can be used in address translation. A bit indicates, page has been accessed. D bit (Dirty bit) is set before a write operation to the page is carried out. The OS reserved bits are used by operating system software. The v/s (user/supervisor) and R/W (Read/write) bit are used to provide protection. U/S R/W Permitted For level 3 Permitted for levels 2,1 or None Read/write 0 1 None Read/write 1 0 Read Only Read/write 1 1 Read write Read/write Q.6(d) Describe enabling and disabling of paging in 8086 [4] When is brought out of reset, it ffirst executes in real mode. To use paging the processor must be executing in protected mode. To enable paging follow these steps. i) Set up the page directory & page tables in memory with the describe values. ii) Load CR 3 with the base address of page directory. Loading CR 3 also invalidates any information stored in T LB. iii) Execute a Mov CRO, EAX instruction where bit 31 i.e. PG bit of CRO is set to 1 and other bits are unchanged. The instruction sequence in which the transition to paging will occur must have its linear address mapped to its physical address iv) The instruction prefect queue should be flushed PG R TS E M MP PE 15

16 : T.Y. Diploma AMP Once paging is turned on, all linear address are converted to physical address. The address translation information is then automatically cached into TLB each time the h/w performs a page translation from the tables in memory. When disabling paging following steps should be follow. i) A mov CRO, EAX to invalidate TLB entries. ii) Mov CR 3, EAX to invalidate TLB entries. After paging is disabled the linear address ae same as physical address. PG bit of CRO when set to zero disable paging while enabling paging this PG bit set to 1. Q.6(e) Describe IVT of 86 processor with suitable diagram. [Diagram 2 marks, explanation 2 marks] IVT Contains 256 interrupt vector entries. Each interrupt vector entry is 4 Bytes in size & stores the 16 Bit values to be loaded in CS and TP to start Interrupt service Routine (ISR). Interrupt Vector Table (IVT) in the X86 Memory 003FFH 003FCH 0000BH 00008H 00007H 00004H 00003H 00000H CSH CSL IP H IP L CS H CS L IP H IP L CS H CS L IP H IP L CS H CS L IP H IP L Interrupt Vector 2 Interrupt Vector 1 Interrup t Vector 16

17 Prelim Question Paper Solution Interrupt Vectors Vector Details no. 0 Divide by 0 AU Exception 1 Single stepping 2 NMI Hardware Pin 3 Break point 4 Overflow ALU Exception 5 to 31 Reserved by Intel for future use 32 to 255 Available to User (User Defined) In X86 Real Mode, interrupts are responded in a standard pattern as shown in the flowchart. The interrupts are sampled at the end of an instruction and therefore before recognising any interrupt X86 processor complete the instruction on hand. The interrupt has occurred does not guaranty that it will be serviced. If the IF flag is O, the interrupt structure of 8086 is disabled (with the exception of NMI which cannot be disabled or masked). If IF = 1, the interrupts are in enabled condition. Therefore even when that interrupt is detected it would be serviced only if the interrupts are enabled. The sequence of operations in Real Mode of X86 processor that takes place for responding the interrupt that is recognised to be serviced. 17