NATIONAL UNIVERSITY OF SINGAPORE

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1 NATIONAL UNIVERSITY OF SINGAPORE SCHOOL OF COMPUTING EXAMINATION FOR Semester 1 AY2013/14 CS2100 COMPUTER ORGANISATION ANSWER SCRIPT Nov 2013 Time allowed: 2 hours Caveat on the grading scheme: I have given a sample grading Your scheme Matriculation in the yellow Number: boxes. However you will be surprise how varied DRAFT the actual ANSWERS answers you guys give. It is not possible for me to forsee all possible student answers. As such, the stated grading schemes for each question are mere guidelines. I will need to exercise discretion on the actual grading itself. You must write you answers to the questions in the appropriate space provided. Any writing outside the given space will not be considered during marking. Begin on the next page. Q1 Q2 Q3 Q4 Q5 Q6 Total Score /100 ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 1 of 15

2 Answer for Question 1a: Present State Next State Flip-Flop A Flip-Flop B Flip-Flop C A B C A B C J A K A J B K B J C K C X 1 X 0 X X X X X X X X X X X X 1 0 X X X X X X X X X X X 0 X 1 0 X X X X X X X X X X X 1 1 X 0 X X X X X X X X X X Full marks: 10 Filling in the table correctly: 3 mark Six K-maps: 1 mark each Getting circuit correct: 1 marks J A = B B 0 X X 1 A X X X X K A = B B X X X X A 0 X X 1 J B = 1 B 1 X X X A X X X 1 K B = 1 B X X X 1 A 1 X X X J C = 0 B 0 X X 0 A 0 X X 0 K C = 0 B X X X X A 0 X X X ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 2 of 15

3 Answer for Question 1b: Full marks: 5 Getting A correct: 2 mark Getting B correct: 3 marks ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 3 of 15

4 Answer for Question 2a: 0x44e13800 Full marks: 3 Final answer correct: 2 marks Working: 1 mark Answer for Question 2b: This is a bad idea because there is only 23 bits of significance in the IEEE single precision floating point numbers. So, for example, while the integer 0x x1 is 0x in integer, in floating point, 0x is represented by the IEEE single precision number 0x4b When we add 1 (or 1.0) to this number, we still get 0x4b Full marks: 3 Hitting the nail on the precision issue: 2 marks A good example: 1 mark Answer for Question 2c: 0x47a8cabf is This is x 2 ( ) or x x3f86b723 is This is x 2 ( ) or Shifting the smaller number to align the binary point, we have Guard bit = 1 Round bit = 0 Sticky bit = 1 Full marks: 3 1 mark for each bit (subject to correctness of working) No working provided or working wrong: 1 mark ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 4 of 15

5 Answer for Question 2d: Performing the addition, we get Rounding to nearest, we get the result of: x or 0x47A8CB46 Full marks: 6 Performing the addition correctly: 3 marks (Partial marks for partially correct answer all will depend on my estimation of how many percent is the answer correct.) Rounding correctly done: 1 mark Final answer in hex correct: 2 marks Final answer not presented in hex: 1 marks ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 5 of 15

6 Answer for Question 3a: ori $a2, $s3, 0xFEED Full marks: 3 Partial marks for partially correct answer all will depend on my estimation of how many percent is the answer correct. Answer for Question 3b: xor $t2, $s1, $a1 is equivalent to and $at, $s1, $a1 # s1 AND a1 or $t2, $s1, $a1 # s1 OR a1 nor $at, $at, $at # NOT(s1 AND a1) and $t2, $t2, $at (s 1 + a 1 ) (s 1 a 1 ) = (s 1 + a 1 ) (s 1 + a 1 ) = s 1 (s 1 + a 1 ) + a 1 (s 1 + a 1 ) = s 1 s 1 + s 1 a 1 + a 1 s 1 + a 1 a 1 = 0 + s 1 a 1 + a 1 s = s 1 a 1 + a 1 s 1 = s 1 a 1 Full marks: 5 Partial marks for partially correct answer all will depend on my estimation of how badly wrong is your answer. ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 6 of 15

7 Answer for Question 3c: FINDMIN: slt $t0, $a1, $0 # Make sure N > 0 bne $t0, $0, OUT # if not, get out add $t0, $a0, $a1 # Address of ARR[N] lw $v0, -1($t0) # Get ARR[N-1] - make it the current min addi $t0, $t0, -1 # Advance index to ARR[N-1] LOOP: beq $t0, $a0, OUT # Will terminate when we reached ARR[0] lw $t1, -1($t0) # Get ARR[i-1] slt $t0, $v0, $t1 # current min < ARR[N-1]? bne $t0, $0, NEXT # if so, go to next element addi $v0, $t1, 0 # otherwise, update current min NEXT: addi $t0, $t0, -1 # decrement address j LOOP OUT: jr $ra # Current min already in return value $v0 Full marks: 12 Partial marks for partially correct answer all will depend on my estimation of how badly wrong is your answer. ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 7 of 15

8 Answer for Question 4a: The instruction is beq $t5, $a1, 0x1481 Signal Value Read reg 1 Read reg 2 Write reg RegDst 0xD 0x5 X / 0x2 X RegWrite 0 ALUSrc 0 Branch 1 Address 0 ALUOp 0x2 MemWrite 0 MemRead 0 MemtoReg ❶ ❷ X 0x x6208 Full marks: 5 For each incorrect entry that is not a don t-care in the answer, 0.5 marks, subjected to a minimum total mark of 0. ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 8 of 15

9 Answer for Question 4b: The shift instructions are R-format instructions. However, in the existing datapath, the shift amount is not extracted. In order to support the shift instructions, we will need: 1. The shift amount field to be extracted and passed directly into the ALU. 2. Shifters have to be added to the ALU. 3. ALU control must decode shift instructions and issue the appropriate instructions to the ALU to perform shifting. 4. All other data path is as per R-format instructions. Full marks: 5 Each of these 4 points: 1 mark each How well the answer is written up: 1 mark Answer for Question 4c: lui is a I-format instructions. Under the current datapath, RS and the immediate is passed into the ALU. RT is also handled correctly for writing. So in order to support the lui instructions: 1. Shifters have to be added to the ALU. 2. ALU control should be modified to instruct the ALU s shifter to shift the immediate by 16 bits. 3. The rest of the processing is handled as per I-format instructions. Full marks: 5 Points 1 and 3: 1 mark each Point 2: 2 marks How well the answer is written up: 1 mark ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 9 of 15

10 Answer for Question 5a: Clock Cycle ❶ ❷ ❸ ❹ ❺ i i i No. The situation is not correctly handled. While a NOP was inserted as the load-use hazard was detected, when the load finishes accessing memory, the current hardware only forwards into the ALU as RT. But for a sw instruction, the ALU uses RS and the immediate to compute the address and discards the RT. Instead the incorrect RT read from the register file by the sw instruction is written into memory. Full marks: 4 Filling up the table correctly: 2 marks Identifying the issue in the handling: 2 marks ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 10 of 15

11 Answer for Question 5b(i): The existing load-use hazard mechanism will insert a NOP, and the forwarding needs to be done as above. Full marks: 4 Identifying the forwarding path correctly: 2 marks Explaining the solution: 2 marks ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 11 of 15

12 Answer for Question 5b(ii): The changes are: 1. A multiplexor must be added at point 1. This over-rides the value read by the sw from the register file. 2. A new forwarding rule must be added: if (ID/EX.MemWrite = 1) # i.e., a sw in EX and (MEM/WB.MemRead = 1) # i.e., a lw in WB and (ID/EX.RegisterRt = MEM/WB.RegisterRt) then forward via point 1. Note that this will require the MemRead command to be passed along to the WB stage. Note that the NOP insertion is unavoidable even though it seems like it is possible to forward from the WB stage back to the MEM stage. When the lw is in the EX stage, the sw is still being decoded and hence there is no way of telling if it is a lw-sw situation or any other load-use situation. Full marks: 4 Identifying the multiplexor to be added and where it is to be added: 1 mark The forwarding rule: 2 marks Detail of description: 1 mark Answer for Question 5c: 0 = Not taken, 1 = Taken Initial State Loop 00 BR 00 Iteration 0 (PC at CONT) Loop 00 BR 01 Iteration 1 (PC at CONT) Loop 00 BR 00 Iteration 2 (PC at CONT) Loop 00 BR 01 ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 12 of 15

13 Iteration 3 (PC at CONT) Loop 00 BR 00 Iteration 98 (PC at CONT) Loop 00 BR 01 Iteration 99 (PC at CONT) Loop 00 BR 00 PC at OUT Loop 01 BR 00 Full marks: 4 Each of the entries before the last two: 0.5 mark each Last two entries: 1 mark each ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 13 of 15

14 Answer for Question 6a: Byte offset = 4 bits Index = 10 bits Tag = 18 bits Each way will need 1 valid bit, 1 dirty bit, 18 bits tag, 4x32 = 128 bits data. Total = 148 bits of storage. Each set has 4 ways, totaling 4 * 148 = 592 bits. There are 1024 sets. So the total storage needed to implement the cache is 1024 *592 bits = 606,208 bits. Full marks: 3 Getting the number of bits for each field correct: 1 mark Getting the total for each set correct: 1 mark Getting the total correct: 1 mark Answer for Question 6b: M[0x80104A3B] Index Valid Tag Word1 Word x x80104A38 0x80104A3C Hit Miss M[0x ] Index Valid Tag Word1 Word x x80104A38 0x80104A3C 1 1 0x x x Hit Miss ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 14 of 15

15 M[0x80104A9B] Index Valid Tag Word1 Word x x80104A38 0x80104A3C 1 1 0x x x x x80104A98 0x80104A9C 3 Hit Miss M[0x ] Index Valid Tag Word1 Word x x80104A38 0x80104A3C 1 1 0x x x x x80104A98 0x80104A9C 3 1 0x x x C Hit Miss M[0x80104A38] Index Valid Tag Word1 Word x x80104A38 0x80104A3C 1 1 0x x x x x80104A98 0x80104A9C 3 1 0x x x C Hit Miss M[0x A] Index Valid Tag Word1 Word x x80104A38 0x80104A3C 1 1 0xE3103 0x x C 2 1 0x x80104A98 0x80104A9C 3 1 0x x x C Hit Miss Full marks: 12 Two marks for each reference. For each reference, correctly identifying hit or miss is 0.5 mark, the rest is for getting the hexadecimal entry correct. End of Answer Sheet ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 15 of 15