The Processor: Datapath & Control

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1 Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control

2 Processor Design Step 3 Assemble Datapath Meeting Requirements Build the data path by adding up the components required to execute each instruction We need to consider: Register transfer requirements Instruction fetch operands and execute operation We are going to consider one instruction format at a time and then combine what we have after each step -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 2

3 Processor Design Step 3-a Instruction Fetch Unit Common to all instruction types Actions taken: Fetch the instruction from Memory: mem[pc] Update program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- branch address PC 4 Adder Address Instruction Memory -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 3

4 Consider R-Type instructions R-Format Instructions: Arithmetic instructions Logic instructions Main actions: 2 registers Perform an ALU operation Write result to destination op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 0 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 4

5 R-Type: What do we need? To read data from a register we need 2-inputs to register file specifying register to be read 2-outputs from register file will carry the values read Remember output is always available to whatever register# given, therefore no control signal is needed To write data to a register we need 1-input to register file with register# to write into 1-data input will carry the data to be written Write control signal that enables data to be written -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 5

6 Datapath for R-Format Instructions Main components: R ead register 1 R ead register 2 Write register Write data R ead data 1 Register file R ead data 2 R egwrite ALU Operation 3 ALU Z ero A L U result -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 6

7 R-Type Datapath Datapath for Add & Subtract Instructions R[rd] R[rs] ± R[rt] Example: add rd, rs, rt The register selection lines come from register fields Control signals are from the control logic after decoding the instruction Opcode + funct -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 7

8 Now, consider the I-Type Load & Store R[rt] Mem[R[rs] + SignExt[imm16]] R[rt] Mem[R[rs] + SignExt[imm16]] Main actions: Sign-extend offset Add to contents of base register to calculate address Load from or store into the calculated address We need a sign-extend unit for offset CS 21 op rs rt/rd? offset 6 bits 5 bits 5 bits 16 bits sign-extended 16-bits 16 bits 16 CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 8 11 offset 16 bits 0 0

9 Datapath for I-Format instructions: Immediate arithmetic operations R[rt] R[rs] op SignExt[imm16] Main actions: Sign extend immediate operand Perform operation Store result We need a sign-extend unit for immediate operand op rs rt/rd? offset 6 bits 5 bits 5 bits 16 bits sign-extended 16-bits 16 bits offset 16 bits 0 0 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 9

10 Datapath for I-Format instructions: Immediate logical operations R[rt] R[rs] op ZeroExt[imm16] Main actions: Zero extend immediate operand Perform operation Store result We need a zero-extend unit for immediate operand op rs rt/rd? immediate 31 6 bits 5 bits 5 bits bits immediate 16 bits 16 bits CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 10

11 Load - The Details Use offset in 16 immediate operand bits Value read from memory must be written into register file R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 lw $t1, offset($t2) #$t2 = Base register op rs rt immediate 6 bits 5 bits 5 bits 16 bit -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 11

12 Store- The Details Use offset in 16 immediate operand bits Value to be stored read from register file Mem[ R[rs] + SignExt[imm16] ] <- R[rt] Example: sw rt, rs, imm16 sw $t1, offset($t2) #$t2 = Base register op rs rt immediate 6 bits 5 bits 5 bits 16 bit -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 12

13 Load & Store- What do we need? Actions: Register access Memory address calculation /Write from memory Write into register (for load) What do we need? Sign-extend unit Data memory unit to read/ or write Both write & read control signals -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 13

14 Implementation of Load & Store Instruction register 1 register 2 Wrte register Wrte data RegWrite data 1 Register File data 2 3 Z ero ALU ALU resut ALU Operation Wr it e data MemW rite Address R ead Data data Memory 16 Sign 32 extend MemR ead -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 14

15 Combining Datapath components A single datapath can be assembled From previous datapaths by adding multiplexors One MUX at ALU input to read Either data bus Or sign extended word One at the data input to the register file that Takes the data from ALU Or from data memory -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 15

16 Putting it all Together Instruction register 1 data 1 register 2 Registers Write data 2 register Write data RegWrite Sign extend ALUSrc M ux 3 ALU operation Zero ALU ALU result Address Write data MemWrite MemtoReg Data memory data Mem M ux -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 16

17 Combining Datapath components Add in the instruction fetch Add 4 PC address Instruction Instruction memory register 1 register 2 Write register Write data RegWrite Registers data 1 data 2 16 Sign 32 extend ALUSrc M ux 3 ALU operation Zero ALU ALU result Address Write data Mem MemWrite MemtoReg data Data memory M ux -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 17

18 Datapath for Branching (I-Format) Datapath For Branch Instructions (I-Format) beq $t1, $t2, offset Steps: Compute branch target address Compare register contents Determine next instruction based on comparison In MIPS, branches are delayed Instruction following the branch is always executed Independent of the branch condition If branch condition is true, backtrack Helps in speeding up (See pipelining) -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 18

19 Branching- The details Step1: Compute branch target address Branch target address = PC + sign-extended offset field HW needed: sign-extension unit Adder Notes: Offset could be positive or negative Offset field is Word offset Shift offset left 2 bits (multiply by 4) to get byte offset Branch offset based on instruction following branch i.e from PC +4 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 19

20 Branching- The details Step2: Compare register contents Hardware needed: Register file to get register contents ALU to perform comparison By subtraction -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 20

21 Branching- The details Step3: Determine next instruction Depends on the result of comparison If condition is true: Branch is taken If condition is false Branch is not taken Hardware needed: ALU: Zero signal from ALU if the result is zero indicating the condition is true -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 21

22 Branching- The details Step 4: Modify instruction fetch datapath If branch is taken PC Branch target address If branch not taken PC PC +4 Hardware needed Adder -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 22

23 The Branching Datapath PC +4 from instruction datapath Instruction 5 5 Reg1 Reg2 Write Reg Write data Register File Data1 Data2 Shift left 2 3 ALU Add Sum ALU Control Zero Branch target To branch control logic RegWrite Sign 16 extend 32 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 23

24 Finally, the J-type j target Unconditional jump 2 target Requires no comparison Target is Word target 6 bits 26 bits Target needs shifting 2 bits to the left Original target 26 bits Target after shifting 28 bits Target need to be loaded into PC The lower 28 bits of PC are replaced with target Hardware needed: Concatenating 00 unit -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 24

25 The Combined Datapath 1 clock cycle for each operation Load/store, ALU operations, Branches PC Src PC 4 address Add Instruction Instruction memory register 1 register 2 Write register Write data R egwrite 16 Registers data 1 data 2 Sign extend 32 Shift left 2 ALUSrc M ux Add ALU result 3 ALU operation Z ero ALU ALU result M u x A ddress Write data Mem M em W rite MemtoReg data Data memory M ux -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 25

26 Critical Path for Load Total time needed = PC s change time + Instruction Memory s Access Time + Register File s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 26

27 Assemble Control Logic Control Unit Analyze implementation of each instruction to determine setting of control points Inst Memory Address Instruction<31:0> <21:25> Op Fun Rt <21:25> Rs <16:20> Rd <0:15> <11:15> Imm16 Control npc_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Equal DATA PATH -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 27

28 What control signals do we need? Register selection: Rs, Rt, Rd and Imed16 hardwired into datapath Operation selection: npc_sel: 0 => PC < PC + 4; 1 => PC < PC SignExt(Im16) 00 Extension 16-bit control ExtOp: zero, sign ALU data source Register or immediate address ALUsrc: 0 => regb; 1 => immed -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 28

29 What control signals do we need? ALU Operation selection (control) ALUctr: add, sub, or Memory Write: MemWr MemtoReg: 1 => Mem RegDst: 0 => rt ; 1 => rd RegWr: write dest register -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 29

30 Control Signals for each instruction inst Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 ALUsrc=RegB, ALUctrl= add, RegDst=rd, RegWr, npc_sel= +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 ALUsrc=RegB, ALUctr= sub, RegDst=rd, RegWr, npc_sel= +4 ORi R[rt] < R[rs] + zero_ext(imm16); PC < PC + 4 ALUsrc=Im, Extop= Z, ALUctr= or, RegDst=rt, RegWr, npc_sel= +4 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 30

31 Control Signals for each instruction inst Register Transfer LOAD R[rt] < MEM[ R[rs] + sign_ext(imm16)]; PC < PC + 4 ALUsrc = Im, Extop = Sn, ALUctr = add, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 STORE MEM[ R[rs] + sign_ext(imm16)] < R[rs]; PC < PC + 4 ALUsrc=Im, Extop= Sn, ALUctr= add, MemWr, npc_sel= +4 BEQ if (R[rs]== R[rt]) then PC< PC+sign_ext(Imm16)] 00 else PC < PC + 4 npc_sel = EQUAL, ALUctr = sub -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 31

32 Assemble each signal npc_sel <= if (OP==BEQ) then EQUAL else 0 ALUsrc <= if (OP== ) then regb else immed ALUctr <= if (OP== ) then funct elseif (OP==ORi) then OR elseif (OP==BEQ) then SUB else ADD -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 32

33 Assemble each signal ExtOp <= if (OP == ORi) then zero else sign MemWr <= (OP == Store) MemtoReg <= (OP == Load) RegWr: <= if ((OP== Store) (OP==BEQ)) then 0 else 1 RegDst: <= if ((OP==Load) (OP==ORi)) then 0 else 1 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 33

34 Datapath with Control Unit PCSrc Add M ux 1 PC 4 address Instruction (31-0) Instruction memory Instruction [25 21] Instruction [20 16] Instruction [15 11] M ux 1 0 RegDst Instruction [15 0] RegWrite reg1 reg2 Write reg Write data Register file data1 data2 16 Sign 32 extend Shift left 2 ALUSrc M ux 1 0 ALU Control Add ALU result ALU Zero ALU result 0 MemWrite Address Write data Data memory Mem data MemReg M ux 1 0 Instruction [5 0] ALUOp -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 34

35 Summary 5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 35

36 Summary MIPS makes it easier Instructions are all the same size Source registers are always in same place in the instruction Immediate operands are the same size & in the same location Operations are always on either register contents or immediate operands Single cycle datapath => CPI=1 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 36

37 The Control Unit Functions: Instruction code Control Unit Control Signals Select operations to be performed (ALU, read/write, etc.) Control data flow (multiplexor inputs) Major components: ALU control Operation based on instruction type and function code Other controls Input: Information comes from the 32 bits of the instruction Output: Control signals -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 37

38 Quick review: MIPS Instruction Formats R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 0 I-type op rs rt immediate 6 bits 5 bits 5 bits 16 bits 0 J-type op target address 6 bits 26 bits 0 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 38

39 ALU Control ALU has 3 control inputs Allows 8-combinations Only 5 combinations are used. The rest could be used as don t-care in minimization 000 AND 001 OR 010 add 110 subtract 111 set-on-less-than -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 39

40 ALU Control Remember: ALU is needed for all instruction categories lw/sw(i-format): Compute memory address Arithmetic/logic(R-Format): Arithmetic / logic operation Branch(beq)(I-Format): Subtract registers We need to find ALU control signals from the information in the instruction Instruction AND OR ADD SUB SLL Op-field Functfield0x 0x24 0x25 0x20 0x22 0x2a Funct- Binary ALU Control CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 40

41 ALU Control ALU performs one of 5 instructions based on instruction class ALUOp: A 2-bit input control used with the funct field Determines 3-bit combination to control the ALU 6-bit funct feld 2-bit ALUOp input 00 Add(for load & store) 01 Subtract (for beq) ALUOp Control 10 Depends on code in funct field 3-bit ALU operation 000 and 001 or 010 add 110 sub 111 slt -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 41

42 How ALU control bits are set (ALUOp = 00 or 01 ) Depend on op field & not on funct field (ALUOp code = 10 ) Depend on funct field to set the ALU control input 1 2 Instruction Opcode Instruction operation Desired ALU action ALU control input ALUOp Funct field lw 00 load word XXXXXX add 010 sw 00 store word XXXXXX add 010 Branch equal 01 branch equal XXXXXX subtract 110 R-type 10 add add 010 R-type 10 subtract subtract 110 R-type 10 AND and 000 R-type 10 OR or 001 R-type 10 set on less than set on less than CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 42

43 ALU Control Multiple level of decoding is used 1. The main control unit generates the ALUOp bits 2. ALUOp bits are used as input to ALU control 3. ALU control generates the actual signal to ALU unit Why use multiple levels? Reduce size of main control unit Increase speed of control unit -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 43

44 ALU Control: Truth Table ALUOp Funct field Operation Instruction ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0 0 0 X X X X X X 010 lw/sw X 1 X X X X X X 110 beq 1 X X X add 1 X X X sub 1 X X X and 1 X X X or 1 X X X sll 8-input lines, 3 output lines Actual table size should be 2 8 = (256) Only relevant combinations are listed Details in (Appendix C2, p. C4) F5 & F4 are always don t cares F3-F0 only are considered -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 44

45 ALU Control: Logic Circuit Details in Appendix C2, p. C4 Based on funct code & ALUOp ALUOp 2 ALUOp0 ALU Control Circuit Diagram F3 ALUOp1 Operation2 ALU operation (Control signals) F (5 0) F2 Operation1 3 5 F1 Operation0 F0 -CS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers (Augmented 1998 Morgan & Modified Kaufmann by M.Malaty Publishers ( and Augmented M. Beers) & Modified by M.Malaty) 45

COMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath

COMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The