ZedBoard Tutorial. EEL 4720/5721 Reconfigurable Computing
|
|
- Gabriel Warner
- 5 years ago
- Views:
Transcription
1 Introduction: In this lab, you will be learning how to create a custom peripheral in the programmable logic on the ZedBoard and how to communicate with that peripheral from software running on the ARM processor. UPDATE: You will be working in groups of 2 on this project. Unless you are an EDGE student or have special permission from the instructor, you must work in a group of 2. Note that those in the overflow section are not EDGE students, and must work in a group of 2. Please only submit once per group. Part 1 Base project and peripheral tutorials 1) See the pdf links on the lab website. Step through these examples yourself until you have the resulting bitfile. Note that some of the steps are no longer needed, so I advise you to do the tutorial yourself and then watch the lecture where I repeat the process to see what steps I skip. Make sure to select the ZedBoard when creating the project. 2) Find the generated bitfile in: project_path\project_name.runs\impl_1 Note that project_path is the path of your Vivado project. Project_name is the name of that project. The bitfile will be called block_diagram_name_wrapper.bit, which is likely design_1_wrapper.bit if you accepted the defaults values when creating your block diagram. Rename the bitfile to part1.bit. Place it in the same directory as the provided C++ code for part1 and transfer the directory to your account on reconfig.ece.ufl.edu. See the class s for instructions on how to do this. 3) From reconfig.ece.ufl.edu (i.e., using an ssh client like putty), compile the code using make. Make sure there are no errors or warnings. 4) Run your code on a ZedBoard using: zed_schedule.py./zed_app part1.bit zed_schedule is a scheduling script that connects to the board server and finds an available board. If a board is available, the script copies your current directory to the selected board and then runs the specified executable (e.g.,./zed_app). This application takes the name of the bitfile as a command line input, so make sure to include part1.bit. 5) Verify there are no errors. The output should look similar to this: Starting job "./zed_app part1.bit" on board : Application completed successfully! 1
2 6) Take a screenshot of the software output. 7) Find and save the IP directory for your peripheral. This directory should have a component.xml file, in addition to various other directories (e.g., src, hdl, drivers, example_designs, etc.). Its location depends on the path of the IP repository that was specified when you created the peripheral. 8) Submission requirements: IP directory, screenshot of software output, and part1.bit. See submission instructions at the end of the document for details. Part 2 Create your own custom peripheral In part 2, you will be using what you learned in part 1 to create a new peripheral. 1) Start a new project for the ZedBoard, following the same steps you did in part 1. 2) Create a new AXI peripheral called part2. On the Add Interfaces dialog box, select 8 registers instead of the 4 registers you used in part 1. 3) Download the provided entity peripheral_test.vhd. Instantiate this entity within the AXI peripheral code (part2_v1_0_s00_axi.vhd) in a similar way as the multiplier in part 1. Registers 0-3 should connect to inputs 0-3. Registers 4-7 should connect to outputs 0-3. For the generic width, use a value of 32 bits to match the width of the registers. 4) Modify the AXI peripheral code to prevent registers 4-7 from having multiple sources by commenting out every assignment to those registers. This modification is required because in the generated code the AXI bus writes to all the registers. We only want peripheral_test to write to registers 4-7, so we have to remove the generated code that writes to these registers. After these modifications, you are actually removing registers 4-7 and are just reusing those signals to act as wires. If you want, you could rename the signals to be more accurate, but this is not required. 5) Fill in the default architecture for peripheral_test.vhd with the following functionality. You can use either signed or unsigned for the arithmetic; the output is identical for these operations: out0 = in0 * in1 out1 = in0 + in1 out2 = in2 - in3 out3 = in2 xor in3 (ignore overflow by only using the lower width bits) 6) Create a testbench peripheral_test_tb.vhd that demonstrates the correctness of peripheral_test. You do not need a simulation screenshot. It is up to you do determine the thoroughness of the testbench. 7) Synthesize the IP to make sure there are no errors. 8) Package your peripheral IP and connect it the Zynq in the block diagram (see tutorials in part 1). 9) Generate a bitfile. 2
3 10) Find the bitfile and rename it to part2.bit. Copy it into the directory with the provided C++ code for part2. 11) Transfer the directory with the C++ code and the bitfile to reconfig.ece.ufl.edu. 12) From reconfig.ece.ufl.edu (i.e., using an ssh client like putty), compile the code using make. 13) Run your code on a ZedBoard using: zed_schedule.py./zed_app part2.bit At this point, there should be no errors for out0 and out1. If there are errors, your peripheral is not working. IMPORTANT: out2 and output3 should be incorrect at this step. 14) Open main.cpp and find the code that transfers in0 and in1 to the ZedBoard. Extend the code to write in2 and in3 to the board. Make sure to use the correct AXI address (see the enum at the top of the file). 15) Find the code that reads results from out0 and out1. Add the code that replicates this process for out2 and out3. 16) Recompile using make. 17) Rerun the code on the ZedBoard. If there are still errors, there is either a problem with your peripheral or with the C++ code you added. Debug until there no errors. 18) Take a screenshot of the working execution (or of the errors that you received if you don t have it working). e.g.: Out0 Errors: 0 Out1 Errors: 0 Out2 Errors: 0 Out3 Errors: 0 Total Errors: 0 Application completed successfully! 19) Find and save the IP directory for part2_peripheral. 20) Submission requirements: IP directory, screenshot of software output, C++ code, part2.bit, peripheral_test.vhd, peripheral_test_tb.vhd, and part2_v1_0_s00_axi.vhd. See submission instructions at the end of the document for details. 3
4 SUBMISSION INSTRUCTIONS (One submission per group) Create a directory called lab2. Inside this directory, create a part1 and part 2 directory. Include a brief readme.txt file in the lab2 directory that specifies the members of the group, any other relevant information that the grader might need (e.g., if one of the parts doesn t work, crashes, doesn t compile, etc.). The submitted directory structure should look like this: lab2/ readme.txt part1/ screenshot part1_1.0/ part1.bit part2/ screenshot part2_1.0/ sw/ hdl/ main.cpp Board.h Board.cpp Makefile part2.bit peripheral_test.vhd peripheral_test_tb.vhd part2_v1_0_s00_axi.vhd // IP core from repository, ok if different name // DON T FORGET // IP core from repository, should have this name // DON T FORGET Zip the entire lab2 directory and submit the lab2.zip file. Extra Credit: In peripheral_test_tb.vhd, create a testbench that exhaustively tests all possible input combinations for an instance of peripheral_test with a width of 4 bits. Because there are 4 inputs, a width of 4 corresponds to 2^16 = 64k possible combinations. NOTE: Larger widths will take an extremely long time, so do not try this. Common Problems: If you make a mistake in the IP core, you can t directly edit the code from within your project. This occurs because Vivado copies a read-only version of the IP core into your project. If you need to edit it, right click the core in the block diagram and select Edit in IP Packager. This will open a separate project for the IP core. From the IP project, modify the code, re-package the IP after any changes, and then refresh the IP within your original project. This process will get 4
5 very annoying, so make sure you have thoroughly tested your IP core code in simulation before packing it to use with the Zynq. There actually is a way to edit the read-only copy of the core, but I don t recommend that yet. I ll explain how for later labs. Unless you make modifications to the code that are not explained in the instructions, you will receive a few synthesis warnings for your peripheral. E.g.: [Synth ] design part2_v1_0 has unconnected port s00_axi_awprot[1] [Synth ] Sequential element (\part2_v1_0_s00_axi_inst/axi_awaddr_reg[0] ) is unused and will be removed from module part2_v1_0. Although for future labs I would encourage you to get rid of all wanings, these warnings will not cause any problems for this lab. 5
EE183 LAB TUTORIAL. Introduction. Projects. Design Entry
EE183 LAB TUTORIAL Introduction You will be using several CAD tools to implement your designs in EE183. The purpose of this lab tutorial is to introduce you to the tools that you will be using, Xilinx
More informationQuartus II Tutorial. September 10, 2014 Quartus II Version 14.0
Quartus II Tutorial September 10, 2014 Quartus II Version 14.0 This tutorial will walk you through the process of developing circuit designs within Quartus II, simulating with Modelsim, and downloading
More informationAdding Custom IP to the System
Lab Workbook Introduction This lab guides you through the process of creating and adding a custom peripheral to a processor system by using the Vivado IP Packager. You will create an AXI4Lite interface
More informationEECE.2160: ECE Application Programming
Spring 2018 Programming Assignment #10: Instruction Decoding and File I/O Due Wednesday, 5/9/18, 11:59:59 PM (Extra credit ( 4 pts on final average), no late submissions or resubmissions) 1. Introduction
More informationECE5775 High-Level Digital Design Automation, Fall 2018 School of Electrical Computer Engineering, Cornell University
ECE5775 High-Level Digital Design Automation, Fall 2018 School of Electrical Computer Engineering, Cornell University Lab 4: Binarized Convolutional Neural Networks Due Wednesday, October 31, 2018, 11:59pm
More information1. Introduction EE108A. Lab 1: Combinational Logic: Extension of the Tic Tac Toe Game
EE108A Lab 1: Combinational Logic: Extension of the Tic Tac Toe Game 1. Introduction Objective This lab is designed to familiarize you with the process of designing, verifying, and implementing a combinational
More informationLab 4: Convolutional Neural Networks Due Friday, November 3, 2017, 11:59pm
ECE5775 High-Level Digital Design Automation, Fall 2017 School of Electrical Computer Engineering, Cornell University Lab 4: Convolutional Neural Networks Due Friday, November 3, 2017, 11:59pm 1 Introduction
More informationCreating a Processor System Lab
Lab Workbook Introduction This lab introduces a design flow to generate a IP-XACT adapter from a design using Vivado HLS and using the generated IP-XACT adapter in a processor system using IP Integrator
More informationELEC 4200 Lab#0 Tutorial
1 ELEC 4200 Lab#0 Tutorial Objectives(1) In this Lab exercise, we will design and implement a 2-to-1 multiplexer (MUX), using Xilinx Vivado tools to create a VHDL model of the design, verify the model,
More informationQuartus II Version 14.0 Tutorial Created September 10, 2014; Last Updated January 9, 2017
Quartus II Version 14.0 Tutorial Created September 10, 2014; Last Updated January 9, 2017 This tutorial will walk you through the process of developing circuit designs within Quartus II, simulating with
More informationLED display manager documentation
LED display manager documentation Clément Foucher (homepage) Clement.Foucher@laas.fr LAASCNRS Laboratoire d'analyse et d'architecture des systèmes Version 1.0 This work is licensed under the Creative Commons
More informationQuartus II Tutorial. September 10, 2014 Quartus II Version 14.0
Quartus II Tutorial September 10, 2014 Quartus II Version 14.0 This tutorial will walk you through the process of developing circuit designs within Quartus II, simulating with Modelsim, and downloading
More informationLab 1: FPGA Physical Layout
Lab 1: FPGA Physical Layout University of California, Berkeley Department of Electrical Engineering and Computer Sciences EECS150 Components and Design Techniques for Digital Systems John Wawrzynek, James
More informationLab 0 Introduction to the MSP430F5529 Launchpad-based Lab Board and Code Composer Studio
ECE2049 Embedded Computing in Engineering Design Lab 0 Introduction to the MSP430F5529 Launchpad-based Lab Board and Code Composer Studio In this lab, you will be introduced to the Code Composer Studio
More informationE85: Digital Design and Computer Engineering Lab 2: FPGA Tools and Combinatorial Logic Design
E85: Digital Design and Computer Engineering Lab 2: FPGA Tools and Combinatorial Logic Design Objective The purpose of this lab is to learn to use Field Programmable Gate Array (FPGA) tools to simulate
More informationXilinx ChipScope ICON/VIO/ILA Tutorial
Xilinx ChipScope ICON/VIO/ILA Tutorial The Xilinx ChipScope tools package has several modules that you can add to your Verilog design to capture input and output directly from the FPGA hardware. These
More informationBuilding an Embedded Processor System on a Xilinx Zync FPGA (Profiling): A Tutorial
Building an Embedded Processor System on a Xilinx Zync FPGA (Profiling): A Tutorial Embedded Processor Hardware Design October 6 t h 2017. VIVADO TUTORIAL 1 Table of Contents Requirements... 3 Part 1:
More informationDigital Design and Computer Architecture
Digital Design and Computer Architecture Introduction Lab 4: Thunderbird Turn Signal In this lab, you will design a finite state machine in SystemVerilog to control the taillights of a 1965 Ford Thunderbird
More informationUsing VoiceThread with Canvas
Using VoiceThread with Canvas VoiceThread is a learning tool that can be used to enhance student engagement and online presence. With VoiceThread, instructors and/or students can create, share, and comment
More informationUniversity of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA
1 University of California, Davis Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Winter Quarter 2018 Lab 1: Implementing Combinational Logic in the MAX10 FPGA Objective: This
More informationECE 362 Experiment 3: General Purpose I/O
ECE 362 Experiment 3: General Purpose I/O 1.0 Introduction In this experiment, you will learn how to attach simple input devices (pushbuttons) and simple output devices (LEDs) to an STM32 development board.
More informationTutorial on Simulation using Aldec Active-HDL Ver 1.0
Tutorial on Simulation using Aldec Active-HDL Ver 1.0 by Shashi Karanam Introduction Active- HDL is an integrated environment designed for development of VHDL designs. The core of the system is a VHDL
More informationEEL 4783: HDL in Digital System Design
EEL 4783: HDL in Digital System Design Lecture 9: Coding for Synthesis (cont.) Prof. Mingjie Lin 1 Code Principles Use blocking assignments to model combinatorial logic. Use nonblocking assignments to
More informationExporting a Course. This tutorial will explain how to export a course in Blackboard and the difference between exporting and archiving.
Blackboard Tutorial Exporting a Course This tutorial will explain how to export a course in Blackboard and the difference between exporting and archiving. Exporting vs. Archiving The Export/Archive course
More informationGUIDE Development tools for Windows(10) installation... 2
GUIDE Development tools for Windows(10) installation... 2 C\C++ compiler and CMake installation... 2 Mingw download... 2 Mingw installation... 3 Adding Mingw compilers folder to PATH variable... 7 CMake
More informationLab Exercise 4 System on chip Implementation of a system on chip system on the Zynq
Lab Exercise 4 System on chip Implementation of a system on chip system on the Zynq INF3430/INF4431 Autumn 2016 Version 1.2/06.09.2016 This lab exercise consists of 4 parts, where part 4 is compulsory
More informationLab 1 Implementing a Simon Says Game
ECE2049 Embedded Computing in Engineering Design Lab 1 Implementing a Simon Says Game In the late 1970s and early 1980s, one of the first and most popular electronic games was Simon by Milton Bradley.
More informationJava Program Structure and Eclipse. Overview. Eclipse Projects and Project Structure. COMP 210: Object-Oriented Programming Lecture Notes 1
COMP 210: Object-Oriented Programming Lecture Notes 1 Java Program Structure and Eclipse Robert Utterback In these notes we talk about the basic structure of Java-based OOP programs and how to setup and
More informationJEE2600 INTRODUCTION TO DIGITAL LOGIC AND COMPUTER DESIGN. ModelSim Tutorial. Prepared by: Phil Beck 9/8/2008. Voter Function
JEE2600 INTRODUCTION TO DIGITAL LOGIC AND COMPUTER DESIGN ModelSim Tutorial Prepared by: Phil Beck 9/8/2008 Vote 1 Vote 2 Voter Function Pass Vote 3 Pass is only a 1 when two or more of the Vote inputs
More informationCreating a base Zynq design with Vivado IPI
Creating a base Zynq design with Vivado IPI 2013.2 based on: http://www.zedboard.org/zh-hant/node/1454 http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1 Dr. Heinz Rongen Forschungszentrum Jülich
More informationCS2630: Computer Organization Project 2, part 1 Register file and ALU for MIPS processor Due July 25, 2017, 11:59pm
CS2630: Computer Organization Project 2, part 1 Register file and ALU for MIPS processor Due July 25, 2017, 11:59pm Goals for this assignment Apply knowledge of combinational logic and sequential logic
More informationEECS150 Lab Lecture 5 Introduction to the Project
EECS150 Lab Lecture 5 Introduction to the Project Ian Juch Electrical Engineering and Computer Sciences University of California, Berkeley 9/28/2012 1 Note on Lab4 You should augment the testbenches we
More informationVerilog Simulation Mapping
1 Motivation UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 4 Verilog Simulation Mapping In this lab you will learn how to use
More informationA short introduction to SystemVerilog. For those who know VHDL We aim for synthesis
A short introduction to SystemVerilog For those who know VHDL We aim for synthesis 1 Verilog & SystemVerilog 1984 Verilog invented, C-like syntax First standard Verilog 95 Extra features Verilog 2001 A
More informationDigital Design and Computer Architecture Harris and Harris, J. Spjut Elsevier, 2007
Digital Design and Computer Architecture Harris and Harris, J. Spjut Elsevier, 2007 Lab 8: MIPS ARM Assembly Language Programming Introduction In this lab, you will learn to write ARM assembly language
More informationAssignment 01 Computer Architecture Lab ECSE
Assignment 01 Computer Architecture Lab ECSE 487-001 Date due: September 22, 2006, Trottier Assignment Box by 14:30 1 Introduction The purpose of this assignment is to re-familiarize the student with VHDL
More informationVerilog Lab. 2 s Complement Add/Sub Unit
Verilog Lab. 2 s Complement Add/Sub Unit TA: Chihhao Chao chihhao@access.ee.ntu.edu.tw Lecture note ver.1 by Chih-hao Chao Lecture Note on Verilog, Course #90132300, EE, NTU, C.H. Chao Introduction In
More informationEITF35 - Introduction to Structured VLSI Design (Fall 2017) Course projects
1 EITF35 - Introduction to Structured VLSI Design (Fall 2017) Course projects v.1.0.0 1 Introduction This document describes the course projects provided in EITF35 Introduction to Structured VLSI Design
More informationECE 4305 Computer Architecture Lab #1
ECE 4305 Computer Architecture Lab #1 The objective of this lab is for students to familiarize with the FPGA prototyping system board (Nexys-2) and the Xilinx software development environment that will
More informationECE 449, Fall 2017 Computer Simulation for Digital Logic Project Instruction
ECE 449, Fall 2017 Computer Simulation for Digital Logic Project Instruction 1 Summary We present in this document the project instruction for ECE 449 including the grading policy. Our goal is to build
More information1-D Time-Domain Convolution. for (i=0; i < outputsize; i++) { y[i] = 0; for (j=0; j < kernelsize; j++) { y[i] += x[i - j] * h[j]; } }
Introduction: Convolution is a common operation in digital signal processing. In this project, you will be creating a custom circuit implemented on the Nallatech board that exploits a significant amount
More informationProject #1: Tracing, System Calls, and Processes
Project #1: Tracing, System Calls, and Processes Objectives In this project, you will learn about system calls, process control and several different techniques for tracing and instrumenting process behaviors.
More informationProject 2: 3D transforms and Cameras
Project : D transforms and Cameras 50pts See schedule on website for the due date and time. The purpose of this assignment is to gain an understanding of how D transforms and viewing works in OpenGL with
More informationLab 1 - Zynq RTL Design Flow
NTU GIEE, MULTIMEDIA SYSTEM-ON-CHIP DESIGN Lab 1 - Zynq RTL Design Flow Pin-Hung Kuo May 11, 2018 1 INTRODUCTION In this lab, we are going to build a simple Zynq system on ZedBoard. This system works as
More informationVivado Design Suite Tutorial. Designing with IP
Vivado Design Suite Tutorial Designing with IP Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
More informationUsing Project Navigator
UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Overview Xilinx Project Navigator is an Integrated Development Environment for digital
More informationNIOS CPU Based Embedded Computer System on Programmable Chip
NIOS CPU Based Embedded Computer System on Programmable Chip 1 Lab Objectives EE8205: Embedded Computer Systems NIOS-II SoPC: PART-I This lab has been constructed to introduce the development of dedicated
More informationCom S 227 Assignment Submission HOWTO
Com S 227 Assignment Submission HOWTO This document provides detailed instructions on: 1. How to submit an assignment via Canvas and check it 3. How to examine the contents of a zip file 3. How to create
More informationAssignment Tutorial.
Assignment Tutorial rudolf.lam@mail.mcgill.ca What we are looking at today Overview Demo Why Motivation for this lecture on assignment How The way the assignment is run What The components of the assignment
More informationCopyright 2014 Xilinx
IP Integrator and Embedded System Design Flow Zynq Vivado 2014.2 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able
More informationIntroduction to MATLAB
Introduction to MATLAB This note will introduce you to MATLAB for the purposes of this course. Most of the emphasis is on how to set up MATLAB on your computer. The purposes of this supplement are two.
More informationProject 1 for CMPS 181: Implementing a Paged File Manager
Project 1 for CMPS 181: Implementing a Paged File Manager Deadline: Sunday, April 23, 2017, 11:59 pm, on Canvas. Introduction In project 1, you will implement a very simple paged file (PF) manager. It
More informationLab 4: Shell Scripting
Lab 4: Shell Scripting Nathan Jarus June 12, 2017 Introduction This lab will give you some experience writing shell scripts. You will need to sign in to https://git.mst.edu and git clone the repository
More informationSpartan-6 LX9 MicroBoard Embedded Tutorial. Tutorial 1 Creating an AXI-based Embedded System
Spartan-6 LX9 MicroBoard Embedded Tutorial Tutorial 1 Creating an AXI-based Embedded System Version 13.1.01 Revision History Version Description Date 13.1.01 Initial release for EDK 13.1 5/15/2011 Table
More informationECSE-323 Digital System Design. Lab #1 Using the Altera Quartus II Software Fall 2008
1 ECSE-323 Digital System Design Lab #1 Using the Altera Quartus II Software Fall 2008 2 Introduction. In this lab you will learn the basics of the Altera Quartus II FPGA design software through following
More informationOPERATING SYSTEMS ASSIGNMENT 4 XV6 file system
OPERATING SYSTEMS ASSIGNMENT 4 XV6 file system Introduction In most systems the main weakness of the file system stems from the data access time, which is much longer than accessing the memory. For certain
More informationLab 2 Implementing Combinational Logic in VHDL. Advanced Testbenches.
Task 1 (30%) Lab 2 Implementing Combinational Logic in VHDL. Advanced Testbenches. Draw a block diagram of the combinational circuit described by the given below pseudocode. Inputs: A: 8-bit unsigned integer
More informationLecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration
TKT-1426 Digital design for FPGA, 6cp Fall 2011 http://www.tkt.cs.tut.fi/kurssit/1426/ Tampere University of Technology Department of Computer Systems Waqar Hussain Lecture Contents Lecture 1: Introduction
More informationProgramming Assignments
ELEC 486/586, Summer 2017 1 Programming Assignments 1 General Information 1.1 Software Requirements Detailed specifications are typically provided for the software to be developed for each assignment problem.
More informationENCE 3241 Data Lab. 60 points Due February 19, 2010, by 11:59 PM
0 Introduction ENCE 3241 Data Lab 60 points Due February 19, 2010, by 11:59 PM The purpose of this assignment is for you to become more familiar with bit-level representations and manipulations. You ll
More informationQuick Start Guide ZedboardOLED Display Controller IP v1.0
Quick Start Guide Introduction This document provides instructions to quickly add, connect and use the ZedboardOLED v1.0 IP core. A test application running on an ARM processor system is used to communicate
More informationIntegrating LogiCORE SEM IP in Zynq UltraScale+ Devices
XAPP1298 (v1.0.2) February 27, 2017 Application Note: Zynq UltraScale+ Devices Integrating LogiCORE SEM IP in Zynq UltraScale+ Devices Author: Michael Welter Summary This application note outlines how
More informationVivado Walkthrough ECGR Fall 2015
ECGR 2181 - Vivado Walkthrough 1 Vivado Walkthrough ECGR 2181 - Fall 2015 Intro In this walkthrough we re going to go through the process of creating a project, adding sources, writing vhdl, simulating
More informationLab 1: CORDIC Design Due Friday, September 8, 2017, 11:59pm
ECE5775 High-Level Digital Design Automation, Fall 2017 School of Electrical Computer Engineering, Cornell University Lab 1: CORDIC Design Due Friday, September 8, 2017, 11:59pm 1 Introduction COordinate
More information2 nd Year Laboratory. Experiment: FPGA Design with Verilog. Department of Electrical & Electronic Engineering. Imperial College London.
Department of Electrical & Electronic Engineering 2 nd Year Laboratory Experiment: FPGA Design with Verilog Objectives By the end of this experiment, you should know: How to design digital circuits using
More informationMotor Control: Model-Based Design from Concept to Implementation on heterogeneous SoC FPGAs Alexander Schreiber, MathWorks
Motor Control: Model-Based Design from Concept to Implementation on heterogeneous SoC FPGAs Alexander Schreiber, MathWorks 2014 The MathWorks, Inc. 1 Some components of a production application Production
More informationAssignment 1. ECSE-487 Computer archecture Lab. Due date: September 21, 2007, Trottier Assignment Box by 14:30
Assignment 1 ECSE-487 Computer archecture Lab Due date: September 21, 2007, Trottier Assignment Box by 14:30 1 Introduction The purpose of this assignment is to re-familiarize the student with VHDL and
More informationCSE 591: Advanced Hardware Design and Verification (2012 Spring) LAB #0
Lab 0: Tutorial on Xilinx Project Navigator & ALDEC s Active-HDL Simulator CSE 591: Advanced Hardware Design and Verification Assigned: 01/05/2011 Due: 01/19/2011 Table of Contents 1 Overview... 2 1.1
More informationCS2630: Computer Organization Project 2, part 1 Register file and ALU for MIPS processor
CS2630: Computer Organization Project 2, part 1 Register file and ALU for MIPS processor Goals for this assignment Apply knowledge of combinational logic and sequential logic to build two major components
More informationLinux Tutorial #1. Introduction. Login to a remote Linux machine. Using vim to create and edit C++ programs
Linux Tutorial #1 Introduction The Linux operating system is now over 20 years old, and is widely used in industry and universities because it is fast, flexible and free. Because Linux is open source,
More informationUse Vivado to build an Embedded System
Introduction This lab guides you through the process of using Vivado to create a simple ARM Cortex-A9 based processor design targeting the ZedBoard development board. You will use Vivado to create the
More informationUsing Verplex Conformal LEC for Formal Verification of Design Functionality
Using Verplex Conformal LEC for Formal Verification of Design Functionality January 2003, ver. 1.0 Application Note 296 Introduction The Altera Quartus II software, version 2.2, easily interfaces with
More informationThe print queue was too long. The print queue is always too long shortly before assignments are due. Print your documentation
Chapter 1 CS488/688 F17 Assignment Format I take off marks for anything... A CS488 TA Assignments are due at the beginning of lecture on the due date specified. More precisely, all the files in your assignment
More informationDigital Design LU. Lab Exercise 1
Digital Design LU Lab Exercise 1 Jakob Lechner, Thomas Polzer {lechner, tpolzer}@ecs.tuwien.ac.at Department of Computer Engineering University of Technology Vienna Vienna, October 4, 2010 1 Overview 1
More informationEECS 470 Lab 1 Assignment
Note: The lab should be completed individually. EECS 470 Lab 1 Assignment The lab must be checked off by a GSI before lab on Thursday, 13 th September, 2018. 1 Linux Introduction and Setup The work in
More information: Distributed Systems Principles and Paradigms Assignment 1 Multithreaded Dictionary Server
433 652: Distributed Systems Principles and Paradigms Assignment 1 Multithreaded Dictionary Server Problem Description Using a client server architecture, design and implement a multi threaded server that
More informationEmbedded System Design and Modeling EE382N.23, Fall 2015
Embedded System Design and Modeling EE382N.23, Fall 2015 Lab #3 Exploration Part (a) due: November 11, 2015 (11:59pm) Part (b) due: November 18, 2015 (11:59pm) Part (c)+(d) due: November 25, 2015 (11:59pm)
More informationECE2029: Introduction to Digital Circuit Design. Lab 2 Implementing Combinational Functional Blocks
ECE2029: Introduction to Digital Circuit Design Lab 2 Implementing Combinational Functional Blocks Objective: In this lab exercise you will simulate, test, and download various digital circuits which implement
More informationCPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND:
CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Getting familiar with DE2 board installation, properties, usage.
More informationAssignment Submission HOWTO
Assignment Submission HOWTO This document provides detailed instructions on: 1. How to submit an assignment via Blackboard 2. How to create a zip file and check its contents 3. How to make file extensions
More informationDesign Space Exploration: Implementing a Convolution Filter
Design Space Exploration: Implementing a Convolution Filter CS250 Laboratory 3 (Version 101012) Written by Rimas Avizienis (2012) Overview This goal of this assignment is to give you some experience doing
More informationTP : System on Chip (SoC) 1
TP : System on Chip (SoC) 1 Goals : -Discover the VIVADO environment and SDK tool from Xilinx -Programming of the Software part of a SoC -Control of hardware peripheral using software running on the ARM
More informationAdvanced module: Video en/decoder on Virtex 5
Advanced module: Video en/decoder on Virtex 5 Content 1. Advanced module: Video en/decoder on Virtex 5... 2 1.1. Introduction to the lab environment... 3 1.1.1. Remote control... 4 1.2. Getting started
More informationAssignment 1: Plz Tell Me My Password
Assignment 1: Plz Tell Me My Password Part I Due: 11:59 pm, September 23, 2013 Part II Due : 11:59 pm, September 27, 2013 1 Introduction The objective of this assignment is to gain experience in: socket
More informationVerilog Lab. Two s Complement Add/Sub Unit. TA: Xin-Yu Shi
Verilog Lab. Two s Complement Add/Sub Unit TA: Xin-Yu Shi genius@access.ee.ntu.edu.tw Introduction In previous lecture, what you have learned : Complete representation for binary negative number Arithmetic
More informationCMPSCI 187 / Spring 2015 Sorting Kata
Due on Thursday, April 30, 8:30 a.m Marc Liberatore and John Ridgway Morrill I N375 Section 01 @ 10:00 Section 02 @ 08:30 1 Contents Overview 3 Learning Goals.................................................
More informationENGR 5865 DIGITAL SYSTEMS
ENGR 5865 DIGITAL SYSTEMS ModelSim Tutorial Manual January 22, 2007 Introduction ModelSim is a CAD tool widely used in the industry for hardware design. This document describes how to edit/add, compile
More informationProject 1a: Hello World!
Project 1a: Hello World! 1. Download cse465.zip from the web page. Unzip this using 7-Zip (not the Windows Utility it doesn t unzip files starting with a period) to your h:\ drive or wherever your CEC
More information143a, Spring 2018 Discussion Week 4 Programming Assignment. Jia Chen 27 Apr 2018
143a, Spring 2018 Discussion Week 4 Programming Assignment Jia Chen 27 Apr 2018 Setting up Linux environment Setting up Linux environment For Ubuntu or other Linux distribution users sudo apt-get update
More informationVivado Design Suite Tutorial
Vivado Design Suite Tutorial Designing IP Subsystems Using IP Integrator Revision History Date Version Revision 11/19/2014 2014.4 Validated with this release. 10/01/2014 2014.3 Validated with this release.
More informationCMPSCI 187 / Spring 2015 Postfix Expression Evaluator
CMPSCI 187 / Spring 2015 Postfix Expression Evaluator Due on Thursday, 05 March, 8:30 a.m. Marc Liberatore and John Ridgway Morrill I N375 Section 01 @ 10:00 Section 02 @ 08:30 1 CMPSCI 187 / Spring 2015
More informationLab 1 Implementing a Simon Says Game
ECE2049 Embedded Computing in Engineering Design Lab 1 Implementing a Simon Says Game In the late 1970s and early 1980s, one of the first and most popular electronic games was Simon by Milton Bradley.
More informationVivado Tutorial. Introduction. Objectives. Procedure. Lab Workbook. Vivado Tutorial
Lab Workbook Introduction This tutorial guides you through the design flow using Xilinx Vivado software to create a simple digital circuit using Verilog HDL. A typical design flow consists of creating
More informationECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado
ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Prof. Sunil P Khatri (Lab exercise created and tested by Ramu Endluri, He Zhou, Andrew Douglass
More informationExperiment 3 Introduction to Verilog Programming using Quartus II software Prepared by: Eng. Shatha Awawdeh, Eng.Eman Abu_Zaitoun
Experiment 3 Introduction to Verilog Programming using Quartus II software Prepared by: Eng. Shatha Awawdeh, Eng.Eman Abu_Zaitoun Introduction: Verilog HDL is a hardware description language used to design
More informationASSIGNMENT TWO: PHONE BOOK
ASSIGNMENT TWO: PHONE BOOK ADVANCED PROGRAMMING TECHNIQUES SEMESTER 1, 2017 SUMMARY In this assignment, you will use your C programming skills to create a phone book. The phone book loads its entries from
More informationVerilog Design Entry, Synthesis, and Behavioral Simulation
------------------------------------------------------------- PURPOSE - This lab will present a brief overview of a typical design flow and then will start to walk you through some typical tasks and familiarize
More informationNIOS CPU Based Embedded Computer System on Programmable Chip
1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based
More informationLaboratory Exercise #6 Introduction to Logic Simulation and Verilog
Laboratory Exercise #6 Introduction to Logic Simulation and Verilog ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University 2 Laboratory Exercise
More informationTUTORIAL #2 HIERARCHICAL DESIGNS AND TEST FIXTURES
Introduction to Active-HDL TUTORIAL #2 HIERARCHICAL DESIGNS AND TEST FIXTURES This tutorial will use the 1-bit full adder you designed in Tutorial #1 to construct larger adders. This will introduce the
More information