Intelligent Interconnect for Autonomous Vehicle SoCs. Sam Wong / Chi Peng, NetSpeed Systems

Transcription

1 Intelligent Interconnect for Autonomous Vehicle SoCs Sam Wong / Chi Peng, NetSpeed Systems

2 Challenges Facing Autonomous Vehicles Exploding Performance Requirements Real-Time Processing of Sensors Ultra-High Safety & Reliability Fail Human Operational: Driver is Fallback Transition of Responsibility Fail Safe: Machine is Fallback Machines No active assistance system Early warning systems Feet-Off Traffic Control, Auto-Parking Hands-Off Awareness for take over Eyes-Off General Awareness Mind-Off No-Driver 0:Driver Only 1: Assistance 2: Semi- Automation 3: High Automation 4: Full Automation 5: Autonomous Source: BMW, Audi, Intel Corp Copyright 2017 NetSpeed Systems 2

3 Translating System-Level Requirements > SoC Level Exploding Performance Requirements Rise of heterogeneous architectures & right-sized compute Cache coherency & End-to-end QoS of critical importance Real-Time Sensor Processing Different IPs with differing requirements Ensuring communication happens without any deadlocks Ultra-High Safety & Reliability Pressure to comply to industry standards ISO Functional Safety Performance Area Tradeoffs Copyright 2017 NetSpeed Systems 3

4 Autonomous Driving: Use Case Compute Flow Image Acquisition Feature Extraction Feature Processing Pattern Recognition Feedback and Action Noise removal Pixel processing Image pyramids Optical flow Edge detection Gradient detection Segmentation & filtering Object tracking Object detection Feature reduction Feature classification Augmentation Computation & processing Feedback loop Avoidance signalling Source: Extreme Tech, Google, Arm Copyright 2017 NetSpeed Systems 4

5 Need For Heterogeneous Computing Image Acquisition Noise removal Pixel processing Image pyramids Smaller amounts of data Highly structured data Complex computation/item Lots of data Simple computation/item Massive parallelism Feature Extraction Optical flow Edge detection Gradient detection CPU DSP (Xtensa) GPU, ISP Feature Processing Segmentation & filtering Object tracking Object detection Feedback loop Noise removal Segmentation & filtering Feature reduction Noise removal Pixel processing Image pyramids Pattern Recognition Feature reduction Feature classification Augmentation Computation & processing Feature classification Edge detection Object tracking Feedback and Action Computation & processing Feedback loop Avoidance signalling Gradient detection Avoidance signalling Augmentation Object detection Optical flow Source: Extreme Tech, Google, Arm Copyright 2017 NetSpeed Systems 5

6 Challenges With Heterogeneous Computing Smaller amounts of data Highly structured data Complex computation/item Lots of data Simple computation/item Massive parallelism Cache Coherency Ensure every compute engine has uniform view of system memory CPU DSP (Xtensa) GPU, ISP System-Level QoS BW-Hogs, Latency-sensitive & Real-time engines need seamless access to memory A72 A72 CPU A72 Accel A72 A72 A72 Local $ GPU Local $ End-to-End Functional Safety Underlying architecture should be resilient & tolerant to random & systematic errors Interconnect Memory Source: Extreme Tech, Google, ARM Copyright 2017 NetSpeed Systems 6

7 Next-Gen Autonomous SoC Architecture Details Trace JTAG Flash DDR USB RIGHT SIZED COMPUTING UART Ethernet CPU Platform A72 A72 CPU A72 A72 A72 CPU A72 CPU M7 Vision Platform Video Encode GPU Video Decode System Ctrl Security Safety Power CSI CSI Single & multi-threaded compute engines Differing access patterns, spatial/temporal locality and performance requirements SEAMLESS CACHE COHERENCY Zipwire GMAC AVB CAN-FD CAN-FD Imaging Platform ISP Camera Camera Camera Camera Image Cognition SoC Interconnect Deep Learning/ Accelerators Camer Camer Camer Camer Camer a Camer Camer a a Camer a Camer Camer Xtensa a a Xtensaa Engines a a a Engines Trace DMA Timers Sensors M/L BIST CSI CSI I2C Uniform shared view of system memory Interprocessor communications lead to network and protocol level deadlocks ROBUST ARCHITECTURE Dynamically changing workloads Handle changing use cases/sw needs Highest level of fault tolerance Low Full High Coherency Latency priority Compute Dynamic Pattern IO Coherent Recognition Real time/isochronous High Non-Coherent BW Video Low Streams Priority Copyright 2017 NetSpeed Systems 7

8 Existing Approaches Fall Short Manual, Hand-optimized Hard, Fixed Point Designs Hand-optimized sub systems Key Elements Are Afterthoughts Fixed topology with limited configurability Coherency through tiled structures and regular connection patterns Divide and conquer approach: Separate coherent, non-coherent Deadlock prone designs QoS schemes are patched, built on top of existing infrastructure Functional safety features is added-on instead of being architected in the solution Copyright 2017 NetSpeed Systems 8

9 NetSpeed Technology: Intelligent Interconnect Architecture NetSpeed Platform Specify Customize Generate IP Blocks RTL Machine Learning Interconnect Construction IP Connectivity SoC Workloads PPA, FuSa Reqs Floorplan Info Test benches FMEDA, Safety Man IPXACT PD Constraints Design spec Scalable Coherency & SoC-Level QoS Design Cockpit for PPA & FuSa Tradeoffs Copyright 2017 NetSpeed Systems 9

10 Machine Learning Based Interconnect Construction NetSpeed Platform Results Performance, Area, FuSa SoC Specifications Workloads, SoC Use Cases IP Blocks, Compute Engines Turing NetSpeed Machine Learning Engine Predictive Models Orion Physically-Aware Interconnect Gemini Cache-Coherent Interconnect Crux High Performance Interconnect Pegasus: Last-Level Cache Copyright 2017 NetSpeed Systems 10

11 Bridge Scalable Cache Coherent Interconnect SoC Management FuSa Trace & Debug Power Mgmt CSI CSI CSI CSI CPU Configurable Cache Coherency Scalable coherency solution: Modular & programmable Sensor-hub Eth Tr DMA CPU In-built directory support Specialized IO-Coherency accelerator SH2 UART I2C CAN-FD ISP Decode/ Encode Interconnect Bridge Bridge Cache Coherency GPU Multi-Level Caching Options Last-level cache, L3 $ > Higher bandwidth > Reduce critical latency Agent Interfaces Routers Config Bus IOCB IOCB IOCB CCC (With Dir) IOCB IOCB DVM Programmable allocation policies Machine Learning / Accelerator Last Last Level Level Cache Cache Last Last Level Level Cache Cache / L3 $ Bridge Bridge Bridge Bridge DDR DDR DDR DDR Scalable Solution 64 cache coherent cluster; 250 IO coherent IPs Seamless connection with DDR, HBM memories In-built deadlock detection and avoidance NetSpeed Gemini Components Copyright 2017 NetSpeed Systems 11

12 Bridge Scalable Cache Coherent Interconnect: Built-In Deadlock Avoidance SoC Management FuSa Trace & Debug Power Mgmt CSI CSI CSI CSI CPU Sensor-hub Eth Tr DMA CPU SH2 UART I2C CAN-FD ISP Decode/ Encode Interconnect Bridge Bridge Cache Coherency GPU Agent Interfaces Routers Config Bus IOCB IOCB IOCB CCC (With Dir) IOCB IOCB DVM Machine Learning / Accelerator Last Last Level Level Cache Cache Last Last Level Level Cache Cache / L3 $ Bridge Bridge Bridge Bridge DDR DDR DDR DDR Built-In Deadlock Detection & Avoidance Formal methods and graph theory algorithms User-driven traffic dependencies Handles complex topologies and routing NetSpeed Gemini Components Copyright 2017 NetSpeed Systems 12

13 Bridge Advanced SoC-Level QoS Schemes SoC Management FuSa Sensor-hub Eth Trace & Debug Tr Power Mgmt DMA CSI CSI CSI CSI CPU CPU Dynamic QoS Control 16 Traffic Classes & 64 Virtual Channels with Dynamic priority Low-latency QoS control for Isochronous traffic flows SH2 UART I2C CAN-FD ISP Decode/ Encode Interconnect Bridge Bridge Cache Coherency GPU End-to-End QoS Improved, lower-latency flow-control with memory scheduler Agent Interfaces Routers Config Bus IOCB IOCB IOCB CCC (With Dir) IOCB IOCB DVM Non head-of-line blocking schemes with guaranteed delivery Last Last Level Level Cache Last Level Cache Last Level Cache Cache / L3 $ Runtime Programmability Machine Learning / Accelerator Bridge Bridge Bridge Bridge DDR DDR DDR DDR Runtime programmable weighted BW allocation Adaptive control to DVFS modes without software intervention NetSpeed Gemini Components Copyright 2017 NetSpeed Systems 13

14 Functional Safety: ISO ASIL-D FuSa Architected In With Top-Down Approach Initiator Initiator(s) Bridge Router Bridge Target FuSa features considered first class citizens from Day #1 Interplays cleanly with coherency and ISO standard End-to-end protection, logic redundancy & timeouts End-to-end User ECC/Parity ECC/Parity Interconnect ECC/Parity ECC/Parity Unprecedented Configurability Fine grained FuSa feature control for low area overhead Hop-to-Hop ECC/Parity Design cockpit for Performance vs. FuSa vs. area tradeoffs Rapid analysis and convergence Port Check Initiator Timeout Error Detection & Correction Logic Duplication, Redundant Routes Interconnect Timeouts Fault Tolerance & Resilience Target Timeouts Timeouts ASIL-D Ready First & Only Coherent Interconnect IP Detailed FMEDA analysis & reporting for any configuration Comprehensive Safety Manual & Safety Report Copyright 2017 NetSpeed Systems 14

15 Design Cockpit: Balancing Performance vs. Area vs. FuSa NetSpeed Design Cockpit Step 1: Specify IP Blocks & Connectivity PPA Requirements Functional Safety Goals SoC Workloads Step 2: Customize Design Exploration: PPA, FuSa Tradeoffs Step 3: Generate Design Synthesizable, Partitionable RTL Verification Checkers, Monitors, Scoreboards Physical Design DEF, SDC, Clk Skew Mgmt, PD Scripts SoC Integration IPXACT, CPF/UPF, Arch Manual Functional Safety FMEDA, Safety Manual Copyright 2017 NetSpeed Systems 15

16 Customer Case Study Customer Tier #1 Automotive manufacturer and Tier #1 ADAS company Architecture and frontend design by customer Back-end by 3 rd party ASIC vendor Challenge Many clusters of CPUs and proprietary accelerators requiring high-bandwidth, low latency, distributed coherent interconnect. No other solution in the market has Robust Real-time QoS support Reliability and safety features for ADAS market Solution Scalable Gemini performance far exceeds competing interconnect capabilities User-controlled automation with integrated performance analysis allows architect to tune Bandwidth/latency/area tradeoffs for specific traffic flows Functional safety architected into interconnect, configured on a per-traffic-flow granularity Copyright 2017 NetSpeed Systems 16

17 Customer Case Study Performance Coherency Configurable Coherency Latency 30% lower Bandwidth 20% saturation FuSa ASIL-D Design Time Timing closure First time timing clean through P&R Wires Reduced congestion seen during layout Buffers Automatically inserted by physical aware flow Gemini is the only configurable Coherency solution that meets my performance needs Lead Fabric Architect Other Customizable Functional safety levels tailored to traffic flow Start-Finish > 9 months Copyright 2017 NetSpeed Systems 17

18 NetSpeed Technology: Choice of Next-Gen Application Leaders #1, #2 Artificial Intelligence Machine Learning Hyperscale Computing In Top 3 In Top 3 Virtual Reality Augmented Reality Real-time Security Analytics In Top 3 The NetSpeed Difference Delivering Intelligent Interconnect technologies to silicon Advanced Machine Learning algorithms to optimize SoC designs #1, #2 Autonomous Vehicles IOT Big Data In Top 5 Innovative team with a proven track record of silicon execution Adopted By Industry Leaders NetSpeed Systems Copyright 2017 NetSpeed Systems 18

19 Summary HETEROGENEOUS ARCHITECTURES REALTIME SENSOR PROCESSING SAFETY & RELIABILITY Cache coherency critical for delivering high performance Complex IP interactions needing sophisticated QoS schemes Functional Safety needs to be architected, not added-on NETSPEED TECHNOLOGY NETSPEED TECHNOLOGY NETSPEED TECHNOLOGY Scalable coherency solution with uniform view of system memory Advanced QoS schemes with traffic isolation & BW allocation ASIL-D Ready: Robust safety mechanisms architected in IP Copyright 2017 NetSpeed Systems 19

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