High Performance Memory in FPGAs

Transcription

1 High Performance Memory in FPGAs

2 Industry Trends and Customer Challenges Packet Processing & Transport > 400G OTN Software Defined Networks Video Over IP Network Function Virtualization Wireless LTE Advanced Early 5G Cloud-RAN Heterogeneous Wireless Networks Video and Vision 8K/4K Resolution Augmented Reality Immersive Display Video Analytics Cloud and Data Center Acceleration Software Defined Data Center Big Data Public and Private Cloud Industrial lot Machine to Machine Industry 40 Embedded Vision Sensory Fusion Cyber-Physical 1 Performance & Power Scalability 2 System Integration & Intelligence 3 Security, Safety & Reliability Page 2

3 FPGA as System Enabler Security AES-GCM mode, greater key protection, more authentication schemes Co-Optimized 27x18 X DSP Wider multipliers, fewer blocks per function SSI Technology Virtual monolithic die Block RAM Block RAM Hardened data cascading Improved power, performance DDR4 Memory I/O 30% higher data rates 20% lower power Transceivers 125G low speed grade 16G & 28G backplane 33G chip-to-chip Integrated IP 100G Ethernet MAC 150G Interlaken PCI Express Gen3 Page 3

4 System Cost 3D-on-3D: Another Industry First Monolithic 3D IC Lower System Cost Higher Integration High-end Low and Mid-range Integration First 3D Transistors on 3 rd Generation 3D ICs 3D Transistors: Non-linear improvement in performance/watt over planar transistors 3D IC: Non-linear improvements in integration & bandwidth/watt over monolithic ICs Page 4

5 ASIC/CPU MPSoC ASIC/CPU MPSoC I/O Serial Link Core Vector Clocking Package Supply Rails Features 6x 2400 Mbps DDR4 (Xeon Phi) 32 PCIe + 3 QPI (Xeon 7) 36 PCIe Known pipeline and worst case power vector Single trunk clock Mostly < 10 > 10 Limited features for specific applications 5x 2667 Mbps DDR4 OR 9x 2400 Mbps DDR Gbps GTY Transceivers Dependent on customer design Multiple trunk clocks; Highly configurable clocking Packed with features to cover variable customer needs (DSP, Networking IP and etc) Virtex 3D FinFET on 3 rd Gen 3D IC 3D IC Kintex Memory & BW Enhanced FPGA Zynq All Programmable MPSoC Software N/A Programmable Circuit Page 5

6 FPGA Memory System Overview Verification & Test * Pre-Si Verification * System bring up & Validation IO Clocking Overall System Memory Performance PHY * Architecture * Physical Design * SW PCB & DRAM * Customer Boards * Memory Vendor Memory Controller * Soft IP core * SW integration Signal and Power Integrity Package Design

7 Memory is a System Level Optimization Challenge PLL Data Package IO Memory Interface Power Grid Network DLL System level tradeoff and optimization DLL DRAM Board Trace Customer System Page 7

8 Critical Path DOE Optimization/Simulation Silicon Package Board > 30 variables Multi Million Simulations ~ 1000 DOE Fast Convergence High Coverage 171ps@1E ps@1E-14 Before After Page 8

9 Packaging A Headache or Opportunity for Innovation and Product Differentiation? Cu-pillar BOT and ETS Panel/Wafer level 3D Wafer level fan-out Cu-wire 3D TSV Flip Chip CSP CSPs Flip Chip PoP Cavity Down BGAs SiP Flip Chip BGAs Pb-free/Cu pillar bump Active Stacking PBGAs Flip Chip BGAs EU bump Homogeneous SSIT QFPs Until 1990 Flip Chip BGAs High Pb/EU bump Multi Chip Module 25D: SOC + HBM Photonics IOs Surface Mount Leadframe 1 st Generation BGAs 2 nd Generation BGAs: Flip Chip 3 rd Generation: WL, 25D, 3D 3D & Photonics Integration

10 Nanometer to Meter and khz to 33 Gbps Transistor (nm) Package (mm) Memory Connectors Board (meter/inch) VR Component Page 10

11 Physical Layout/Stack-up Example um/mm sub-um mil/inch Page 11

12 FPGA Package Technology Impact 1404 HPIO pins

13 System Memory Channel Design FPGA Page 13

14 Power Delivery System Overview VID Sense Page 14

15 Power Delivery Result Robust Timing Integrity Quiet Noise Timing Integrity Page 15

16 FPGA Platform Memory Validation Arch PHY+IO+Fabric Software + Tools 3D + 3D Package SI/PI DDR4 System Validation

17 System Validation DIMM 4 DRAMs 5 DRAMs 9 DRAMs FPGA

18 DDR4 Memory Write 32 Gbps Write Data Eye Capture Probes Attachment

19 Challenges

20 Q & A