HEAT (Hardware enabled Algorithmic tester) for 2.5D HBM Solution

Transcription

1 HEAT (Hardware enabled Algorithmic tester) for 2.5D HBM Solution Kunal Varshney, Open-Silicon Ganesh Venkatkrishnan, Open-Silicon Pankaj Prajapati, Open-Silicon May 9, 9,

2 Agenda High Bandwidth Memory (HBM) Basics Chip Introduction & Motivation Challenges HEAT Features Conclusion 2

3 JEDEC standard Understanding HBM DRAM embedded in ASIC Package (Stacked Memory Dies) Backed by AMD, SK-Hynix, Samsung, nvidia 2.5D Interposer based ASIC implementation Initial adoption expected in GPU & HPC markets, now followed by Networking HBM Gen2 JEDEC specifications: 8 Gb per DRAM die 2 Gbps/pin (DDR) 4/8 High stack for 4GB/8GB density 256 GB/s total bandwidth 3 3

4 Understanding HBM From Memory Vendor Developed at Open-Silicon 4 4

5 Chip Introduction & Motivation HBM Test Chip Technology node : 16nm FF from TSMC 2.5D Interposer technology HBM Memory : SK-Hynix Key Motivation: On-chip Silicon Validation of in-house HBM capabilities HBM Protocol Controller HBM PHY D2D IOs 5 5

6 Chip Block Diagram Package Logic Die JTAG 5 TAPSEL_EN Padring.v HEAT Jtag_2_csr(C) Controller CSR i/f hbm_top.v HBM PHY HBM reset to memory Clock/Reset Signals Clk_CNTRL/ DEBUG GPIO Tap Controller Jtag_2_uif AUTO AUTO AUTO BIST AUTO BIST BIST BIST UIF 0 UIF 1 UIF 2 UIF 3 HBM Controller IO PADS IEEE 1500 HBM D2D Channel 0 HBM D2D Channel 1 HBM Memory DIE Reset De-assertion clk_reset_ctrl.v PLL Reset Chatter Soc reset HBM_clk Reset De-assertion PLL DFT Speed Test Module/ IO DA

7 Challenges At speed Functional Testing (1Ghz) At speed Traffic Generation ( mimicking system traffic) Single cycle data integrity check Performance Measurement Power aware Design Minimal Package IO Count Fall-back chip booting options Functional Debug User Interface Debug Testing Logic die before Assembly 7 7

8 HEAT Architecture 8 8

9 Functional Testing Traffic generation Galois LFSRs used Modes of operation: BW: WWWW.. BR: RRRRR... RAW: WRWRWR. WWRRWWRR. Control on DATA/ADDR Constant, INC/DEC by N, Random, W0, W1, CB Scenarios: Memory sweep, Bank Switching, Max Latency, Max BW etc. Data Integrity Wr_data stored in 16 deep CAM. ID used as addr of CAM Single cycle data comparator when rd response is received. 9 9

10 Challenges At speed Functional Testing (1Ghz) At speed Traffic Generation ( mimicking system traffic) Single cycle data integrity check Performance Measurement Power aware Design Minimal Package IO Count Fall-back chip booting options Functional Debug User Interface Debug Testing Logic die before Assembly 10 10

11 Performance Measurement Latency: Min latency with transaction details Max latency with transaction details Avg Latency Bandwidth: Total number of clks taken by a sequence. Configurable Timeout Value and Timeout status. Byte wise Granularity in LFSR to reduce Power consumption 11 11

12 Challenges At speed Functional Testing (1Ghz) At speed Traffic Generation ( mimicking system traffic) Single cycle data integrity check Performance Measurement Power aware Design Minimal Package IO Count Fall-back chip booting options Functional Debug User Interface Debug Testing Logic die before Assembly 12 12

13 Package IO Count Test Chip : Limited Package IO availability JTAG Selected as i/f for Programming the HEAT Functional JTAG and DFT JTAG Muxed Functional IO Muxing. Same IO used as i/p during chip reset and o/p after chip reset Inputs from board used for fall-back chip booting options

14 Challenges At speed Functional Testing (1Ghz) At speed Traffic Generation ( mimicking system traffic) Single cycle data integrity check Performance Measurement Power aware Design Minimal Package IO Count Fall-back chip booting options Functional Debug User Interface Debug Testing Logic die before Assembly 14 14

15 Functional Debug Number of UIF read/write errors received Number of Data Mismatch errors with Expected data and actual data received on UIF Info of first failed transaction Directed Mode Single or upto 4 transactions (read or write) User can create it s own transaction Bitwise Data masking to pin-point single bit errors in data stream Option of stop/continue on error

16 Challenges At speed Functional Testing (1Ghz) At speed Traffic Generation ( mimicking system traffic) Single cycle data integrity check Performance Measurement Power aware Design Minimal Package IO Count Fall-back chip booting options Functional Debug User Interface Debug Testing Logic die before Assembly 16 16

17 User Interface Debug Bus Monitor design Monitors HEAT engine output and UIF Bus Helpful in Debugging on-chip failures Multiple mode of operations Bus Capture Transaction recorder Error recorder 17 17

18 Challenges At speed Functional Testing (1Ghz) At speed Traffic Generation ( mimicking system traffic) Single cycle data integrity check Performance Measurement Power aware Design Minimal Package IO Count Fall-back chip booting options Functional Debug User Interface Debug Testing Logic die before Assembly 18 18

19 Testing Logic Die before Assembly Loopback Handles for testing without memory Point of Loopback :» Core Side Loopback (before D2D IO)» IO loopback (Loopback using D2D IO) Loopback Transaction generation:» UIF level Loopback» DFI-i (input of PHY) level Address loopback» DFI-i (input of PHY) level Data loopback 19 19

20 Conclusion At speed Functional Testing (1Ghz) At speed Traffic Generation ( mimicking system traffic) Single cycle data integrity check Performance Measurement Power aware Design Minimal Package IO Count Fall-back chip booting options Functional Debug User Interface Debug Testing Logic die before Assembly 20 20