description/ordering information

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1 Operate From 1.65 V to 3.6 V Specified From 40 C to 85 C, 40 C to 125 C, and 55 C to 125 C Inputs Accept Voltages to 5.5 V Max t pd of 4.1 ns at 3.3 V Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25 C SN54LVC08A...J OR W PACKAGE SN74LVC08A... D, DB, NS, OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND description/ordering information SCAS283O JANUARY 1993 REVISED FEBRUARY 2004 Typical V OHV (Output V OH Undershoot) >2 V at V CC = 3.3 V, T A = 25 C Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD V Human-Body Model (A1-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) The SN54LVC08A quadruple 2-input positive-and gate is designed for 2.7-V to 3.6-V V CC operation, and the SN74LVC08A quadruple 2-input positive-and gate is designed for 1.65-V to 3.6-V V CC operation. The LVC08A devices perform the Boolean function Y A BorY A B in positive logic. TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER 40 C to 85 C QFN RGY Reel of 1000 SN74LVC08ARGYR LC08A 40 C to 125 C V CC 4B 4A 4Y 3B 3A 3Y SN74LVC08A... RGY PACKAGE (TOP VIEW) 1B 1Y 2A 2B 2Y A Tube of 50 SN74LVC08AD SOIC D Reel of 2500 SN74LVC08ADR LVC08A Reel of 250 SN74LVC08ADT SOP NS Reel of 2000 SN74LVC08ANSR LVC08A SSOP DB Reel of 2000 SN74LVC08ADBR LC08A Tube of 90 SN74LVC08APW TSSOP PW Reel of 2000 SN74LVC08APWR LC08A Reel of GND SN74LVC08APWT TOP-SIDE MARKING CDIP J Tube of 25 SNJ54LVC08AJ SNJ54LVC08AJ 55 C to 125 C CFP W Tube of 150 SNJ54LVC08AW SNJ54LVC08AW SN54LVC08A... FK PACKAGE (TOP VIEW) LCCC FK Tube of 55 SNJ54LVC08AFK SNJ54LVC08AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at CC 3Y V B 4A 4Y 3B 3A 1Y NC 2A NC 2B 1B 1A NC 2Y GND NC V CC 4B 3Y 3A NC No internal connection 4A NC 4Y NC 3B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated 1

2 SCAS283O JANUARY 1993 REVISED FEBRUARY 2004 description/ordering information (continued) Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. FUNCTION TABLE (each gate) INPUTS OUTPUT A B Y H H H L X L X L L logic diagram, each gate (positive logic) A B Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 6.5 V Input voltage range, V I (see Note 1) V to 6.5 V Output voltage range, V O (see Notes 1 and 2) V to V CC V Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0) ma Continuous output current, I O ±50 ma Continuous current through V CC or GND ±100 ma Package thermal impedance, θ JA (see Note 3): D package C/W (see Note 3): DB package C/W (see Note 3): NS package C/W (see Note 3): PW package C/W (see Note 4): RGY package C/W Storage temperature range, T stg C to 150 C Power dissipation, P tot (T A = 40 C to 125 C) (see Notes 5 and 6) mw Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD For the D package: above 70 C, the value of Ptot derates linearly with 8 mw/k. For the DB, NS, and PW packages: above 60 C, the value of Ptot derates linearly with 5.5 mw/k. 2

3 SCAS283O JANUARY 1993 REVISED FEBRUARY 2004 recommended operating conditions (see Note 7) VCC Supply voltage SN54LVC08A 55 TO 125 C MIN MAX Operating Data retention only 1.5 VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V VI Input voltage V VO Output voltage 0 VCC V IOH IOL High-level output current Low-level output current VCC = 2.7 V VCC = 3 V VCC = 2.7 V 12 VCC = 3 V 24 t/ v Input transition rise or fall rate 8 ns/v NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions (see Note 7) VCC VIH VIL Supply voltage High-level input voltage Low-level input voltage SN74LVC08A UNIT V ma ma TA = 25 C 40 TO 85 C 40 TO 125 C UNIT MIN MAX MIN MAX MIN MAX Operating Data retention only VCC = 1.65 V to 1.95 V 0.65 VCC 0.65 VCC 0.65 VCC VCC = 2.3 V to 2.7 V V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V 0.35 VCC 0.35 VCC 0.35 VCC VCC = 2.3 V to 2.7 V V VCC = 2.7 V to 3.6 V VI Input voltage V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH IOL VCC = 1.65 V High-level output VCC = 2.3 V current VCC = 2.7 V VCC = 3 V VCC = 1.65 V Low-level output VCC = 2.3 V current VCC = 2.7 V VCC = 3 V t/ v Input transition rise or fall rate ns/v NOTE 7: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. V ma ma 3

4 SCAS283O JANUARY 1993 REVISED FEBRUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVC08A PARAMETER TEST CONDITIONS VCC 55 TO 125 C UNIT MIN TYP MAX IOH = 100 µa 2.7 V to 3.6 V VCC 0.2 VOH IOH = 12 ma 2.7 V V 2.4 IOH = 24 ma 3 V 2.2 IOL = 100 µa 2.7 V to 3.6 V 0.2 VOL IOL = 12 ma 2.7 V 0.4 V IOL = 24 ma 3 V 0.55 II VI = 5.5 V or GND 3.6 V ±5 µa ICC VI = VCC or GND, IO = V 10 µa ICC One input at VCC 0.6 V, Other inputs at VCC or GND V 2.7 V to 3.6 V 500 µa Ci VI = VCC or GND 3.3 V 5 pf TA = 25 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74LVC08A PARAMETER TEST CONDITIONS VCC TA = 25 C 40 TO 85 C 40 TO 125 C UNIT MIN TYP MAX MIN MAX MIN MAX VOH IOH = 100 µa 1.65 V to 3.6 V VCC 0.2 VCC 0.2 VCC 0.3 IOH = 4 ma 1.65 V IOH = 8 ma 2.3 V IOH = 12 ma 2.7 V V IOH = 24 ma 3 V IOL = 100 µa 1.65 V to 3.6 V IOL = 4 ma 1.65 V VOL IOL = 8 ma 2.3 V V IOL = 12 ma 2.7 V IOL = 24 ma 3 V II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 µa ICC VI = VCC or GND, IO = V µa ICC One input at VCC 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V µa Ci VI = VCC or GND 3.3 V 5 pf V 4

5 SCAS283O JANUARY 1993 REVISED FEBRUARY 2004 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM TO PARAMETER (INPUT) (OUTPUT) tpd A or B Y SN54LVC08A VCC 55 TO 125 C UNIT MIN MAX 2.7 V V ± 0.3 V ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B Y SN74LVC08A VCC TA = 25 C 40 TO 85 C 40 TO 125 C UNIT MIN TYP MAX MIN MAX MIN MAX 1.8 V ± 0.15 V V ± 0.2 V V V ± 0.3 V tsk(o) 3.3 V ± 0.3 V ns ns operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS VCC TYP UNIT 1.8 V 7 Cpd Power dissipation capacitance per gate f = 10 MHz 2.5 V 9.8 pf 3.3 V 10 5

6 SCAS283O JANUARY 1993 REVISED FEBRUARY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL (see Note A) RL RL S1 VLOAD Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh S1 Open VLOAD GND LOAD CIRCUIT VCC VI INPUTS tr/tf VLOAD CL RL V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 VCC/2 1.5 V 1.5 V 2 VCC 2 VCC 6 V 6 V 30 pf 30 pf 50 pf 50 pf 1 kω 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI tw Timing Input 0 V VI tsu th Input 0 V Data Input VI 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input VI 0 V Output Control VI 0 V Output tplh tphl VOH VOL Output Waveform 1 S1 at VLOAD (see Note B) tpzl tplz VOL + V VLOAD/2 VOL Output tphl tplh VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOH VOL Output Waveform 2 S1 at GND (see Note B) tpzh tphz VOH V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOH 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6

8 MECHANICAL DATA MCFP002A JANUARY 1995 REVISED FEBRUARY 2002 W (R-GDFP-F) CERAMIC DUAL FLATPACK (1,) (0,66) (6,60) (5,97) Base and Seating Plane (2,03) (1,) (0,20) (0,10) (7,11) MAX (0,48) (0,38) (1,27) (9,91) (8,51) (0,13) MIN 4 Places (9,) (6,35) (9,) (6,35) / C 02/02 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 1835 GDFP1-F and JEDEC MO-092AB

9 MECHANICAL DATA MLCC006B OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) (9,09) (7,80) (9,09) A SQ B SQ (11,23) (16,26) (18,78) (23,83) 1.1 (28,99) (11,63) (16,76) (19,32) (24,43) (29,59) (10,31) (12,58) (12,58) (21,6) (26,6) (11,63) (,22) (,22) (21,8) (27,0) (0,51) (0,25) (2,03) (1,63) (0,51) (0,25) (1,40) (1,) (1,) (0,89) (0,71) (0,54) (1,27) (1,) (0,89) 40400/ D 10/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

11 MECHANICAL DATA MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN (1,27) (0,51) 0.0 (0,35) (0,25) (6,20) (5,80) (0,20) NOM (4,00) (3,81) Gage Plane 1 4 A (0,25) (1,12) (0,40) Seating Plane (1,75) MAX (0,25) (0,10) (0,10) DIM PINS ** 8 16 A MAX (5,00) (8,75) (10,00) A MIN (4,80) (8,55) (9,80) /E 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed (0,15). D. Falls within JEDEC MS-012

13 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane 1 0,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

14 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0,19 8 4,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

15 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2004, Texas Instruments Incorporated

SN54LVTH16374, SN74LVTH V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54LVTH16374, SN74LVTH V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input