SN54ALS880A, SN54AS880, SN74ALS880A, SN74AS880 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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1 N54AL880A, N54A880, N74AL880A, N74A880 DUAL 4-BIT D-TYPE LATCHE WITH 3-TATE OUTPUT DA079A D21, DECEMBER 1982 REVIED MAY tate Buffer-Type Outputs Drive Bus Lines Directly Bus-tructured Pinout AL873B is Alternative Version With Noninverting Outputs Package Optio Include Plastic mall Outline Packages, Both Plastic and Ceramic Chip Carriers, and tandard Plastic and Ceramic 300-mil DIPs Dependable Texas Itruments uality and Reliability description These dual 4-bit registers feature 3-state outputs designed specifically for bus driving. This makes these devices particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The dual 4-bit latches are traparent D-type. When the latch enable input (1C or 2C) is high, the outputs will follow the data (D) inputs in inverted form, according to the function table. When the latch enable input is taken low, the outputs will be latched. When PRE goes low, the outputs go low independently of the clock. The outputs are in a high-impedance state when (output control) is at a high logic level. The N54AL880A and N54A880 are characterized for operation over the full military temperature range of 55 C to 125 C. The N74AL880A and N74A880 are characterized for operation from 0 C to 70 C. FUTION TABLE (each latch) INPUT OUTPUT PRE C D L L X X L L H H H L L H H L H L H L X 0 H X X X Z N54AL880A, N54A JT PACKAGE N74AL880A, N74A DW OR NT PACKAGE (TOP VIEW) D1 2D2 2D3 1PRE D1 2D2 2D3 2D4 2 GND PRE V CC 1C C 2PRE N54AL880A, N54A JT PACKAGE N74AL880A, N74A DW OR NT PACKAGE (TOP VIEW) D4 No internal connection VCC 1C 11 2 GND 2PRE 2C PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 198, Texas Itruments Incorporated POT OFFICE BOX DALLA, TEXA
2 N54AL880A, N54A880, N74AL880A, N74A880 DUAL 4-BIT D-TYPE LATCHE WITH 3-TATE OUTPUT DA079A D21, DECEMBER 1982 REVIED MAY 198 logic symbol C 1 1PRE C 14 2PRE 13 2D1 7 2D2 8 2D3 9 2D4 10 EN EN This symbol is in accordance with ANI/IEEE td and IEC Publication Pin numbers shown are for DW, JT, and NT packages. logic diagram (each quad latch, positive logic) C PRE D1 1 D2 2 D3 3 D4 4 2 POT OFFICE BOX DALLA, TEXA 7525
3 N54AL880A, N54A880, N74AL880A, N74A880 DUAL 4-BIT D-TYPE LATCHE WITH 3-TATE OUTPUT DA079A D21, DECEMBER 1982 REVIED MAY 198 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) upply voltage, V CC V Input voltage V Voltage applied to a disabled 3-state output V Operating free-air temperature range: N54AL880A, N54A C to 125 C N74AL880A, N74A C to 70 C torage temperature range C to 150 C recommended operating conditio N54AL880A N74AL880A MIN NOM MAX MIN NOM MAX VCC upply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current 1 2. ma IOL Low-level output current ma tw Pulse duration PRE low C high tsu etup time, data before C th Hold time, data after C TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TET CONDITION N54AL880A N74AL880A MIN TYP MAX MIN TYP MAX VIK VCC = 4.5 V, II = 18 ma V VCC = 4.5 V to 5.5 V, IOH = 0.4 ma VCC 2 VCC 2 VOH VCC = 4.5 V, IOH = 1 ma V VOL VCC = 4.5 V, IOH = 2. ma VCC = 4.5 V, IOL = 12 ma VCC = 4.5 V, IOL = 24 ma IOZH VCC = 5.5 V, VO = 2.7 V µa IOZL VCC = 5.5 V, VO = 0.4 V µa II VCC = 5.5 V, VI = 7 V ma IIH VCC = 5.5 V, VI = 2.7 V µa IIL VCC = 5.5 V, VI = 0.4 V ma IO VCC = 5.5 V, VO = 2.25 V ma Outputs high ICC VCC = 5.5 V Outputs low ma Outputs disabled All typical values are at VCC = 5 V, TA = 25 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IO. V POT OFFICE BOX DALLA, TEXA
4 N54AL880A, N74AL880A DUAL 4-BIT D-TYPE LATCHE WITH 3-TATE OUTPUT DA079A D21, DECEMBER 1982 REVIED MAY 198 switching characteristics (see Note 1) VCC = 5 V, VCC = 4.5 V to 5.5 V, CL = 50 pf, CL = 50 pf, R1 = 500 Ω, R1 = 500 Ω, FROM TO R2 = 500 Ω, R2 = 500 Ω, (INPUT) (OUTPUT) TA = 25 C TA = MIN to MAX AL880A N54AL880A N74AL880A MIN TYP MAX MIN MAX MIN MAX D C PRE tpzh tpzl tphz tplz NOTE 1: Load circuit and voltage waveforms are shown in ection 1. 4 POT OFFICE BOX DALLA, TEXA 7525
5 N54A880, N74A880 DUAL 4-BIT D-TYPE LATCHE WITH 3-TATE OUTPUT recommended operating conditio DA079A D21, DECEMBER 1982 REVIED MAY 198 N54A880 N74A880 MIN NOM MAX MIN NOM MAX VCC upply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current ma tw Pulse duration PRE low C high tsu etup time, data before C 2 2 th Hold time, data after C 1 1 TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TET CONDITION N54A880 N74A880 MIN TYP MAX MIN TYP MAX VIK VCC = 4.5 V, II = 18 ma V VCC = 4.5 V to 5.5 V, IOH = 2 ma VCC 2 VCC 2 VOH VCC = 4.5 V, IOH = 12 ma V VOL VCC = 4.5 V, IOH = 15 ma VCC = 4.5 V, IOL = 32 ma VCC = 4.5 V, IOL = 48 ma IOZH VCC = 5.5 V, VO = 2.7 V µa IOZL VCC = 5.5 V, VO = 0.4 V µa II VCC = 5.5 V, VI = 7 V ma IIH VCC = 5.5 V, VI = 2.7 V µa IIL VCC = 5.5 V, VI = 0.4 V ma IO VCC = 5.5 V, VO = 2.25 V ma Outputs high ICC VCC = 5.5 V Outputs low ma Outputs disabled All typical values are at VCC = 5 V, TA = 25 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IO. V POT OFFICE BOX DALLA, TEXA
6 N54A880, N74A880 DUAL 4-BIT D-TYPE LATCHE WITH 3-TATE OUTPUT DA079A D21, DECEMBER 1982 REVIED MAY 198 switching characteristics (see Note 1) VCC = 4.5 V to 5.5 V, CL = 50 pf, R1 = 500 Ω FROM TO R2 = 500 Ω (INPUT) (OUTPUT) TA = MIN to MAX N54A880 N74A880 MIN MAX MIN MAX D C PRE tpzh tpzl tphz tplz NOTE 1: Load circuit and voltage waveforms are shown in ection 1. POT OFFICE BOX DALLA, TEXA 7525
description VCC 1PRE 1OC 1D1 1C 1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4 2C 2PRE 1D2 1D3 1D4 2D1 2D2 2D3 2D4 2OC GND 1PRE 1OC 1Q1 1D1 1Q2 1Q3 1Q4 1D2 1D3 1D4
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SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Typical V OLP (Output Ground Bounce) < 1 V at V CC = 5 V, T A = 25 C Distributed
AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations
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~ > TEXAS~ SN5427, SN54LS27, SN7427, SN74LS27 TRIPLE 3-INPUT POSITIVE-NOR GATES. Vee INSTRUMENTS POST OFOICE BOX OALLAS.
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PI74FCT373T PI74FCT573T Octal Transparent Latches
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IDTQS3257 QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH QUAD 2:1 MUX/DEMUX DESCRIPTION: FUNCTIONAL BLOCK DIAGRAM FEATURES: APPLICATIONS:
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QL ,000 Usable PLD Gate pasic 3 FPGA Combining High Performance and High Density
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COM L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25. Programmable AND Array (44 x 132) OUTPUT LOGIC MACRO CELL OUTPUT LOGIC MACRO CELL
FINAL COM L: H-5/7//5/25, -/5/25 IND: H-/5/2/25 PALCE22V Family 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS As fast as 5-ns propagation delay and 42.8 MHz fmax (external) Low-power
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SN54ABT2241, SN74ABT2241 OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS
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CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9
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3.3 VOLT CMOS SyncBiFIFO TM 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2. Mail 1. Register. RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36
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3.3V ZERO DELAY CLOCK BUFFER
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IDT54/74FCT373T/AT/CT
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AT28C256 Features Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms
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