FPGA BASED IMPLEMENTATION OF STM-16 FRAMER IP CORE

Transcription

1 FPGA BASED IMPLEMENTATION OF STM-16 FRAMER IP CORE 1 T.SHIVARAJA, 2 RASHMI PRIYADARSHINI, 3 RAJA JITENDRA NAYAKA 1 Mtech-4th Sem,ECE department, RITM Yelahanka Bangalore, Karnataka, India 2 Asst. Professor, ECE department, RITM Bangalore, Karnataka, India. 3 Senior Engineer, ITI Limited, Bangalore, Karnataka, India. Abstract- This paper proposes the FPGA based implementation of STM-16 Framer IP core. It mainly focuses on multiplexing STM-1 Frames to form STM-16 Frames and transmission and reception of STM-16 frame. It scrambles the transmitted STM-16 Frames and descrambles the received STM-16 frames, so Scrambling / De-Scrambling can be enabled or disabled. The design is implemented using VHDL and simulated on Xilinx ISE For debugging Chip scope Analyzer is used. The designed STM-1 framer can be used for generation and analysis of STM-16 frame that has a data rate of Mbps. Key Word- STM (Synchronous transmission module). I. INTRODUCTION The SDH (synchronous digital hierarchy) is a hierarchical set of digital transport structures and it is standardized for the transport of suitably adapted payloads over physical transmission networks. The SDH defines a structure which enables plesiochronous signals to be combined together and encapsulated within a standard SDH signal. The ITU- T recommendations define a number of transmission rates within the SDH. The STM-16 has a speed of Gbit/s (where STM stands for Synchronous Transport Module ) [1]. STM-16 signal can carry a number of lower bit rate signals as payload and allows existing PDH signals to be carried over a synchronous network. The SDH defines a number of containers which are corresponding to an existing plesiochronous rate. Information from the plesiochronous container is mapped into the relevant container. The way in which this is done is similar to the bit stuffing procedure carried out in a conventional PDH multiplexer. SDH is currently the dominant choice for metropolitan-area networks as well as for accessing wavelength division multiplexing networks in wide-area networks [2]. The purpose of this paper is to carry multiple digital signals on a single medium and it also describes whether the data that is transmitted is received correctly or not. The above figure shows the STM-1 Frame which is divided into two parts in which each square represents 8 bits (1byte).First nine columns represents the Section Overhead (SOH) and next 261 columns represents the virtual container at level four(vc- 4).The SOH dedicates the three rows for a regenerator section overhead (RSOH) and six rows for the multiplexer section overhead (MSOH). The VC-4 contains one column for the VC-4 path overhead (VC-4 POH) and remaining 260 columns for payload data ( Mbit/s) [3]. III. SDH MULTIPLEXING According to the ITU-T standard G.707 the specification of STM-16 Frame are as follows: Number of rows in a frame = 9 rows. Number of columns in a frame = = 4320 columns. Number of bytes/frame = 9*4320 = 38,880 bytes. Number of bits/frame = 9*4320*8 = 3, 11,040 bits. Number of bits per second = 9*4320*8*8000 = bits per second = Mbits/s(2.488Gbits/s). IV. SDH OVERHEAD [4] The overhead and transport functions are dividing into layers. They are: II. SDH FRAME STRUCTURE Fig.2.1: Basic Overhead Structure. Regenerator Section Multiplex Section Path The layers have a hierarchical relationship. This section details the different SDH overhead information, specifically: Regenerator Section Overhead Multiplex Overhead Path Overhead 48

2 A. Regenerator Section Overhead The Regenerator Section Overhead contains only the information required for the elements located at both ends of a section. This might be two regenerators or two pieces of line terminating equipment. The Regenerator Section Overhead is found in the first three rows of Columns 1 through 9 of the STM-1 frame (see Figure 4.1). AU pointer function is to link between the section overhead and the associated virtual container(s). C. Multiplexer Section Overhead (MSOH) The Multiplex Section Overhead contains the information required between the multiplex section termination equipment at each end of the Multiplex section (that is, between consecutive network elements excluding the regenerators). The Multiplex Section Overhead is found in Rows 5 to 9 of Columns 1 through 9 of the STM-1 frame (see Figure 4.2). Fig.4.1: STM-1 Regenerator section overhead. 1) Framing (A1, A2 Bytes): The six framing bytes carry the framing pattern, and are used to indicate the start of an STM-1 frame. 2) Channel Identifier (C1 Byte): The C1 byte is used to identify STM-1 frames within a higher-level SDH frame (STM-N, where the standardized values of N are 4, 16, etc.). The byte carries the binary representation of the STM-1 frame number in the STM-N frame. 3) Parity Check (B1 Byte): A 8-bit wide bitinterleaved parity (BIP-8) checksum is calculated over all the bits in the STM-1 frame, to permit error monitoring over the regenerator section. The computed even-parity checksum is placed in the RSOH of the following STM-1 frame. 4) Data Communication Channel (D1, D2, D3 Bytes): The 192 kbps Data Communication Channel (DCC) provides the capability to transfer network management and maintenance information between regenerator sections terminating equipment. 5) Orderwire Channel (E1 Byte): The E1 byte is used to provide a local orderwire channel for voice communications between regenerators and remote terminal locations. 6) User Communication Channel (F1 byte): The F1 byte is intended to provide the network operator with a channel that is terminated at each regenerator location, and can carry proprietary communications. The information transmitted on this channel can be passed unmodified through a regenerator, or can be overwritten by data generated by the regenerator. B. AU Pointers (H1, H2, H3bytes) The AU (Administration Unit) pointer bytes are used to enable the transfer of STM-1 frames within STM- N frames, and then processed by multiplexer section terminating equipment. Separate pointers are provided to each STM-1 frame in an STM-N frame. Fig.4.2: STM-1 Multiplex section overhead. 1) Parity Check (B2 Bytes): A 24-bit wide bitinterleaved parity (BIP) checksum is calculated over all the bits in the STM-1 frame (except those in the regenerator section overhead). The computed checksum is placed in the MSOH of the following STM-1 frame. 2) Protection Switching (K1, K2 Bytes): The K1 and K2 bytes carry the information needed to activate/deactivate the switching between the main and protection paths on a multiplexer section. 3) Data Communication Channel (D4 to D12 Bytes): Bytes D4 to D12 provide a 576 kbps data communication channel (DCC) between multiplexer section termination equipment. This channel is used to carry network administration and maintenance information. 4) Orderwire Channel (E2 Byte): The E2 byte is used to provide a local orderwire channel for voice communications between multiplexer sections terminating equipment. D. Higher-Order Path Overhead(VC-4/VC-3) The Path Overhead is assigned to, and transported with the Virtual Container from the time it s created by path terminating equipment until the payload is demultiplexed at the termination point in a piece of path terminating equipment. The Path Overhead is found in Rows 1 to 9 of the first column of the VC-4 or VC-3(See Figure 4.3). Fig.4.3: Higher-order path overhead (VC-4/VC-3). 49

3 1) Path Trace Message (J1 Byte): The J1 byte is used to repetitively transmit a 64-byte string (message). The message is transmitted one byte per VC-4 frame. A unique message is assigned to each path in an SDH network. Therefore, the path trace message can be used to check continuity between any location on a transmission path and the path source. 2) Parity Check (B3 Byte): It is an 8-bit wide bitinterleaved parity even checksum which is used for error performance monitoring on the path and it is calculated over all the bits of the previous VC-4. The computed value is placed in the B3 byte. 3) Signal Label (C2 Byte): The signal label byte, C2, indicates the structure of the VC-4 container. The signal label can assume 256 values, however two of these values are of particular importance: The all 0 s code represents the VC-4 unequipped state (the VC-4 does not carry any tributary signals). The code represents the VC-4 equipped state. 4) Path Status (G1 Byte): The G1 byte is used to send status and performance monitoring information from the receive side of the path terminating equipment to the path originating equipment. This allows the status and performance of a path to be monitored from either end, or at any point along the path. 5) Multiframe Indication (H4 byte): The H4 byte is used as a payload multiframe indicator and provides support for complex payload structures. 6) User Communication Channel (F2 Byte): The F2 byte supports a user channel that enables proprietary network operator communications between path terminating equipment. V.STM-16 Framer Architecture [3] Three transmission levels (STM-1, STM-4, and STM- 16) have been defined for the SDH hierarchy. As Figure 5.1 shows, the ITU has specified that an STM- 4 signal should be created by byte interleaving four STM-1 signals. The basic frame rate remains 8,000 frames per second, but the capacity is quadrupled, resulting in a bit rate of 4 x mbps, or mbps. The STM-4 signal can then be further multiplexed with three additional STM-4s to form an STM-16 signal, having data rate of mbps.table 5.1 lists the defined SDH frame formats, their bit rates, and the maximum number of 64 Kbit/s telephony channels that can be carried at each rate. TABLE.5.1- SDH Levels Fig.5.1.STM-16 Framer Architecture. V. B1,B2,B3 PARITY BYTE CALCULATION FOR STM FRAMES A) BIP Definition Bit Interleaved Parity (BIP-X) code is defined as a method of error monitoring. With even parity (as opposed to odd parity) an X-bit code is generated by the transmitting equipment over a specified portion (also called block ) of the frame. The results of the BIP check for each link section of the network are inserted into parity bytes known as: B1, B2, and B3.Fig.6.1 show the Parity bytes representation. Fig.6.1: B1,B2,B3, Parity bytes representation. B) Block Concept The function of the SDH parity bytes (B1, B2, and B3) is more easily understood if they are associated with the definition of the Block. A set of consecutive bits associated with the path or the section, each bit belongs to one and only one block and consecutive bits may not be contiguous in time. The Fig 6.2 shows the Parity Byte with Monitored Block. 50 Fig 6.2. Parity Byte with Monitored Block

4 1) Parity Byte- B1: B1 byte is calculated over all bits of the previous STM-n/OC-n frame after it has been scrambled. This calculated value of B1 is then placed in the following frame before it is scrambled. The value of the parity byte (B1) is calculated over 9 rows by 270*16(for STM-16) columns. This represents 12, 44,160 bits which are protected by 8 parity bits. The Fig.6.3. Indicating representation of BIP- 8 code. VI. BIP MECHANISM IN SDH/SONET NETWORKS All the BIPs are calculated over their respective portion and the results are placed in the following. All the BIPs are calculated prior to scrambling except B1 which is calculated after the frame has been scrambled. The following example illustrates this specific process with the B1 byte: Fig 6.3: representation of BIP-8 code. 2) Parity Byte-B2: B2 bytes are calculated prior to scrambling, but exclude the Regenerator/Section overhead bytes (A1, A2, J0, B1, E1, D1, D2, D3, etc...). The B2 bytes are then placed in the appropriate column, of the following frame before it is scrambled. B2 is a 4 x 24 BIP-1. Fig.7.1.Transmiter side. Fig.7.2. Receiver side. VII. SIMULATION AND RESULTS A) Simulation result of STM-16 framer IP Core. Fig 6.4: B2 Byte Calculation. 3) Parity Byte- B3: B3 is a BIP-8. B3 specifically does not include the SOH portion of the frame in its calculation which is made prior to scrambling. The result of the B3 calculation is placed in the frame as shown in below Fig 6.5.In the Demux side we are checking the B1, B2 and B3 parity of the received frames. The calculated parity bytes are cross checked with the received parity bytes. The results are given to the Error Status Module to generate the error signals. In the Mux side, we are generating B1, B2 and B3 parity bytes for the encrypted payload. These newly generated parity bytes are multiplexed with the SDH frame. B) BIP-1 at the end of the Frame. Fig.6.5: B3 Byte Calculation. 51

5 C) Analysis of STM-16 Framer IP Core Output using Chipscope Analyzer De-framer checks whether the obtained data is error free or not and also check the overhead bytes to determine the errors in the Section Overhead. The STM-16 provides a highly secured high speed data transmission at Gbps and it can support 30,720 Telephony Channels. REFERENCES [1] ITU-T Recommendation G.707/Y.1322, Network node interface for Synchronous Digital Hierarchy (SDH), Telecommunication Standardization Sector of ITU. Geneva, January CONCLUSION The development of the STM-16 framer IP core support Asynchronous Transport Mode. It can be used for moving voice and data. The STM-16 Framer has been designed and can accommodate 38,880 user data. That will be multiplexed in a single Frame. The [2] R. Clauberg "Data aggregation architectures for single chip SDH/SONET framers", IBM J. RES & DEV. VOL. 47 NO.2/3 March/May [3] The Fundamentals of SDH. [4] SDH Telecommunications Standard Primer. [5] Understanding Error Checking Using Parity Bytes in SDH/SONET Networks by Arnaud WROBLEWSKI 52